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2020-08-25x86: Change CTZ_DEFINED_VALUE_AT_ZERO to return 0/2H.J. Lu1-2/+2
2020-08-25hppa: PR middle-end/87256: Improved hppa_rtx_costs avoids synth_mult madness.Roger Sayle1-34/+138
2020-08-25hppa: Improve expansion of ashldi3 when !TARGET_64BITRoger Sayle1-1/+33
2020-08-25aarch64: Update feature macro nameRichard Sandiford1-1/+1
2020-08-25aarch64: Tweaks to the handling of fixed-length SVE typesRichard Sandiford1-17/+113
2020-08-25aarch64: Update the mangling of single SVE vectors and predicatesRichard Sandiford1-1/+1
2020-08-25MIPS: Fix __builtin_longjmp (PR 64242)Andrew Pinski1-1/+11
2020-08-25Refine typo to fix ICE.liuhongt1-1/+1
2020-08-24arm: Fix -mpure-code support/-mslow-flash-data for armv8-m.base [PR94538]Christophe Lyon1-12/+54
2020-08-23x86: Add target("general-regs-only") function attributeH.J. Lu1-3/+41
2020-08-22Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.liuhongt1-3/+3
2020-08-21Enable bitwise operation for type mask.liuhongt4-63/+214
2020-08-21According to instruction_tables.pdfliuhongt1-4/+4
2020-08-21Enable direct movement between gpr and mask registers in pass_reload.liuhongt3-3/+6
2020-08-21x86: Add cost model for operation of mask registers.H.J. Lu3-0/+185
2020-08-20vxworks: Fix GCC selftests for *-wrs-vxworks7-* targetsIain Buclaw1-5/+11
2020-08-20arm: Require MVE memory operand for destination of vst1q intrinsicJoe Ramsay1-2/+2
2020-08-19rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro defi...Carl Love3-322/+347
2020-08-19rs6000: Enable more sibcalls when TOC is not preservedBill Schmidt1-15/+15
2020-08-19i386: Use code_for_ instead of gen_ for parameterized names more.Uros Bizjak1-17/+19
2020-08-19AArch64: Remove "fndecl && TREE_PUBLIC (fndecl)" in aarch64_init_cumulative_argsPeixin Qiao1-1/+0
2020-08-18rs6000: Rename instruction xvcvbf16sp to xvcvbf16spnPeter Bergner3-5/+5
2020-08-18rs6000: unaligned VSX in memcpy/memmove expansionAaron Sawdey3-16/+105
2020-08-18i386: Rewrite restore_stack_nonlocal expander [PR96536].Uros Bizjak1-72/+43
2020-08-18Don't use pinsr/pextr for struct initialization/extraction.liuhongt1-2/+0
2020-08-17i386: Use parametrized pattern names some more.Uros Bizjak3-65/+49
2020-08-17Force ENDBR immediate into memory.liuhongt2-0/+37
2020-08-14i386: Improve LWP builtin expanders.Uros Bizjak3-62/+67
2020-08-14C-SKY: Fix assembling error with -mfloat-abi=hard.Jojo R2-0/+4
2020-08-13i386: Improve CET builtin expanders.Uros Bizjak4-107/+78
2020-08-13rs6000: ICE when using an MMA type as a function param or return value [PR96506]Peter Bergner1-1/+33
2020-08-13Revert "AArch64: Add if condition in aarch64_function_value [PR96479]"Richard Sandiford1-4/+0
2020-08-13Merge two define_insn: <avx512>_blendm<mode>, <avx512>_load<mode>_mask.liuhongt1-19/+15
2020-08-12PR target/96558: Only call ix86_expand_clear with GENERAL_REGS.Roger Sayle1-1/+1
2020-08-12AArch64: Add if condition in aarch64_function_value [PR96479]Peixin Qiao1-0/+4
2020-08-12Fix up flag_cunroll_grow_size handling in presence of optimize attr [PR96535]Jakub Jelinek1-17/+33
2020-08-12[nvptx] Fix array dimension in nvptx_assemble_decl_beginTom de Vries1-2/+2
2020-08-12x86_64: Use peephole2 to eliminate redundant moves.Roger Sayle1-0/+10
2020-08-12IBM Z: Fix PR96308Andreas Krebbel1-0/+25
2020-08-12IBM Z: Fix PR96456Andreas Krebbel2-3/+8
2020-08-10i386: Improve code generation of smin(x,0) with -m32.Roger Sayle1-1/+11
2020-08-10Using UNSPEC for vector compare to mask register.liuhongt4-107/+21
2020-08-08rs6000: MMA built-ins reject typedefs of MMA typesPeter Bergner1-17/+31
2020-08-07bpf: remove trailing whitespaces from source filesJose E. Marchesi3-3/+1
2020-08-07Power10: Add BRD, BRW, and BRH support.Michael Meissner1-20/+24
2020-08-07PR96493, powerpc local call linkage failureAlan Modra1-1/+6
2020-08-07mmix: fix gcc.dg/loop-9.c by more accurate move insnsHans-Peter Nilsson1-12/+36
2020-08-06arm: Clear canary value after stack_protect_test [PR96191]Richard Sandiford2-5/+9
2020-08-06rs6000: Don't ICE when spilling an MMA accumulatorPeter Bergner1-8/+14
2020-08-06bpf: more flexible support for kernel helpersJose E. Marchesi3-505/+391
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