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2022-10-25rs6000: Add CCANY; replace <un>signed by <mode:CCANY>Segher Boessenkool3-20/+19
2022-10-25Remove znver4 instruction reservationsTejas Joshi1-813/+36
2022-10-25MIPS: add builtime option for -mcompact-branchesYunQiang Su1-1/+2
2022-10-25MIPS: Not trigger error for pre-R6 and -mcompact-branches=alwaysYunQiang Su2-15/+15
2022-10-25MIPS: fix building on multiarch platformYunQiang Su2-1/+22
2022-10-24[AArch64] Improve immediate expansion [PR106583]Wilco Dijkstra1-225/+260
2022-10-24RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng2-10/+34
2022-10-24RISC-V: Support (set (mem) (const_poly_int))Ju-Zhe Zhong1-0/+12
2022-10-24RISC-V: Replace CONSTEXPR with constexprJu-Zhe Zhong4-11/+11
2022-10-24RISC-V: Remove unused TI/TF vector modes.Ju-Zhe Zhong1-4/+0
2022-10-24RISC-V: Fix REG_CLASS_CONTENTS.Ju-Zhe Zhong1-1/+1
2022-10-22Fix uninitialized variable warnings.Michael Eager1-5/+14
2022-10-22xtensa: Make register A0 allocable for the CALL0 ABITakayuki 'January June' Suwa1-4/+10
2022-10-21i386: Fix up BFmode comparisons in conditional moves [PR107322]Jakub Jelinek1-0/+37
2022-10-21Enable AMD znver4 support and add instruction reservationsTejas Joshi9-41/+983
2022-10-21RISC-V: Add type attribute for atomic instructions.Monk Chiang2-6/+11
2022-10-21RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.Ju-Zhe Zhong11-1/+549
2022-10-21RISC-V: Add RVV intrinsic basic framework.Ju-Zhe Zhong5-81/+1063
2022-10-21i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.Haochen Jiang1-11/+50
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling9-21/+217
2022-10-21Support Intel AVX-IFMAHongyu Wang13-68/+195
2022-10-20amdgcn: Use FLAT addressing for all functions with pointer arguments [PR105421]Julian Brown1-6/+9
2022-10-20aarch64: Commonise some folding codeRichard Sandiford3-7/+10
2022-10-20aarch64: Use using directives to inherit constructorsRichard Sandiford3-87/+24
2022-10-20aarch64: Replace CONSTEXPR with constexprRichard Sandiford5-83/+83
2022-10-20aarch64: Prevent generation of /M BRKAS and BRKBSRichard Sandiford1-14/+10
2022-10-20aarch64: Fix matching of BRKNSRichard Sandiford2-8/+64
2022-10-19gcc: Add 'mcf' thread model support from mcfgthreadLIU Hao2-1/+13
2022-10-19IBM zSystems: Fix function_ok_for_sibcall [PR106355]Stefan Schulze Frielinghaus1-23/+24
2022-10-19xtensa: Prepare the transition from Reload to LRATakayuki 'January June' Suwa7-24/+99
2022-10-19s390: Fix bootstrap error with checking and -m31.Robin Dapp1-3/+4
2022-10-19i386: Fix up __bf16 handling on ia32Jakub Jelinek2-10/+9
2022-10-19Canonicalize vec_perm index to make the first index come from the first vector.liuhongt1-0/+17
2022-10-17Fix bogus RTL on the H8.Jeff Law2-41/+69
2022-10-17More infrastructure to avoid bogus RTL on H8.Jeff Law3-0/+35
2022-10-17Remove accidential commitsJeff Law12-31671/+0
2022-10-17Enable REE for H8Jeff Law12-0/+31671
2022-10-17Add missing splitter for H8Jeff Law1-0/+18
2022-10-17GCN: Restore build with GCC 4.8Thomas Schwinge1-7/+7
2022-10-17RISC-V: Fix format[NFC]Ju-Zhe Zhong1-1/+1
2022-10-17RISC-V: Reorganize mangle_builtin_type.[NFC]Ju-Zhe Zhong1-13/+13
2022-10-16Add new constraints for upcoming autoinc fixesJeff Law2-0/+37
2022-10-16Rename "z" constraint to "Zz" on the H8/300Jeff Law2-5/+5
2022-10-15Fix bug in register move costing on H8/300Jeff Law1-1/+1
2022-10-14Fix PR target/107248Eric Botcazou1-12/+12
2022-10-14middle-end, c++, i386, libgcc: std::bfloat16_t and __bf16 arithmetic supportJakub Jelinek4-69/+94
2022-10-13machmode: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE mean...Jakub Jelinek1-1/+1
2022-10-13[AArch64] Improve bit tests [PR105773]Wilco Dijkstra3-44/+72
2022-10-12RISC-V: Remove TUPLE size macro define. [NFC]Ju-Zhe Zhong1-3/+0
2022-10-12RISC-V: Apply clang-format for riscv-vector-builtins.* [NFC]Ju-Zhe Zhong3-7/+6
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