| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-11-08 | i386: Improve vector [GL]E{,U} comparison against vector constants [PR107546] | Jakub Jelinek | 3 | -11/+94 |
| 2022-11-08 | Revert "i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor}" | konglin1 | 2 | -28/+3 |
| 2022-11-08 | Add m_CORE_ATOM for atom cores | Haochen Jiang | 2 | -31/+41 |
| 2022-11-07 | bpf: cleanup missed refactor | David Faust | 1 | -23/+1 |
| 2022-11-07 | Initial Grand Ridge support | Hu, Lin1 | 4 | -1/+15 |
| 2022-11-07 | i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor} | konglin1 | 2 | -3/+28 |
| 2022-11-07 | Support Intel RAO-INT | konglin1 | 9 | -1/+139 |
| 2022-11-07 | Initial Granite Rapids Support | Haochen Jiang | 4 | -2/+17 |
| 2022-11-07 | Support Intel prefetchit0/t1 | Haochen Jiang | 13 | -3/+190 |
| 2022-11-06 | LoongArch: Add fcopysign instructions | Xi Ruoyao | 1 | -1/+21 |
| 2022-11-04 | aarch64: Fix typo in aarch64-sve.md comment | Kyrylo Tkachov | 1 | -2/+2 |
| 2022-11-04 | Remove support for Intel MIC offloading | Thomas Schwinge | 5 | -783/+0 |
| 2022-11-04 | Better integrate default 'sorry' 'TARGET_ASM_CONSTRUCTOR', 'TARGET_ASM_DESTRU... | Thomas Schwinge | 1 | -1/+0 |
| 2022-11-04 | Restore default 'sorry' 'TARGET_ASM_CONSTRUCTOR', 'TARGET_ASM_DESTRUCTOR' | Thomas Schwinge | 1 | -0/+1 |
| 2022-11-04 | Support Intel AMX-FP16 ISA | Hongyu Wang | 7 | -1/+59 |
| 2022-11-04 | Initial Sierra Forest Support | Haochen Jiang | 4 | -1/+16 |
| 2022-11-04 | Support Intel CMPccXADD | Haochen Jiang | 11 | -2/+160 |
| 2022-11-03 | amdgcn: Fix instruction generation for exp2 and log2 operations | Kwok Cheung Yeung | 1 | -6/+14 |
| 2022-11-03 | i386: Fix uninitialized register after peephole2 conversion [PR107404] | Uros Bizjak | 1 | -1/+2 |
| 2022-11-03 | amdgcn: Fix duplicate conditionals [PR107510] | Andrew Stubbs | 1 | -2/+0 |
| 2022-11-02 | RISC-V: Add Zawrs ISA extension support | Christoph Müllner | 2 | -0/+6 |
| 2022-11-02 | rs6000: Byte reverse V8HI on Power8 by vector rotation. | Xionghu Luo | 2 | -7/+16 |
| 2022-11-01 | i386: correct integer division modeling in znver.md | Alexander Monakov | 1 | -18/+21 |
| 2022-11-01 | Fix incorrect digit constraint | liuhongt | 2 | -84/+58 |
| 2022-11-01 | Enable more optimization for 32-bit/64-bit shrd/shld with imm shift count. | liuhongt | 1 | -4/+146 |
| 2022-10-31 | RISC-V: Change constexpr back to CONSTEXPR | Ju-Zhe Zhong | 4 | -11/+11 |
| 2022-10-31 | amdgcn: add fmin/fmax patterns | Andrew Stubbs | 2 | -0/+32 |
| 2022-10-31 | amdgcn: multi-size vector reductions | Andrew Stubbs | 3 | -94/+45 |
| 2022-10-31 | amdgcn: Silence unused parameter warning | Andrew Stubbs | 1 | -1/+1 |
| 2022-10-31 | Support Intel AVX-NE-CONVERT | konglin1 | 13 | -25/+316 |
| 2022-10-31 | i386:: using __bf16 for AVX512BF16 intrinsics | konglin1 | 7 | -117/+180 |
| 2022-10-31 | Enable V4BFmode and V2BFmode. | liuhongt | 5 | -17/+30 |
| 2022-10-29 | d: Make TARGET_D_MINFO_SECTION hooks in elfos.h the language default. | Iain Buclaw | 4 | -32/+4 |
| 2022-10-29 | d: Remove D-specific version definitions from target headers | Iain Buclaw | 19 | -91/+325 |
| 2022-10-28 | Fix signed vs unsigned issue in H8 port | Jeff Law | 2 | -2/+2 |
| 2022-10-28 | c: tree: target: C2x (...) function prototypes and va_start relaxation | Joseph Myers | 23 | -49/+79 |
| 2022-10-28 | Aarch64: Do not define DONT_USE_BUILTIN_SETJMP | Eric Botcazou | 1 | -4/+0 |
| 2022-10-27 | x86: Replace ne:CCC/ne:CCO with UNSPEC_CC_NE in neg patterns | H.J. Lu | 1 | -20/+25 |
| 2022-10-27 | aarch64: Reinstate some uses of CONSTEXPR | Richard Sandiford | 8 | -62/+62 |
| 2022-10-27 | RISC-V: Limit regs use for z*inx extension. | Jiawei | 2 | -6/+20 |
| 2022-10-27 | RISC-V: Target support for z*inx extension. | Jiawei | 4 | -44/+46 |
| 2022-10-27 | RISC-V: Minimal support of z*inx extension. | Jiawei | 3 | -0/+18 |
| 2022-10-26 | bpf: add preserve_field_info builtin | David Faust | 3 | -75/+334 |
| 2022-10-26 | xtensa: Fix out-of-bounds array access in the movdi pattern | Takayuki 'January June' Suwa | 1 | -3/+4 |
| 2022-10-26 | RISC-V: Fix epilogue generation for barrier. | Ju-Zhe Zhong | 1 | -2/+2 |
| 2022-10-26 | RISC-V: ADJUST_NUNITS according to -march. | Ju-Zhe Zhong | 5 | -53/+50 |
| 2022-10-26 | RISC-V: Support load/store in mov<mode> pattern for RVV modes. | Ju-Zhe Zhong | 11 | -27/+645 |
| 2022-10-26 | RISC-V: Recognized Svinval and Svnapot extensions | Monk Chiang | 2 | -0/+9 |
| 2022-10-26 | RISC-V: Adjust table indentation in commnet for riscv-modes.def | Ju-Zhe Zhong | 1 | -23/+23 |
| 2022-10-26 | rs6000: cannot_force_const_mem for HIGH code rtx[PR106460] | Jiufu Guo | 1 | -2/+5 |
