aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Collapse)AuthorFilesLines
2024-11-05Reorganize the CPU feature detectionAntoni Boucher2-97/+96
Move the code from i386-rust.cc to i386-rust-and-jit.inc so that it can be reused by libgccjit. gcc/ChangeLog: * config/i386/i386-rust-and-jit.inc: New file. * config/i386/i386-rust.cc: Move code to i386-rust-and-jit.inc.
2024-03-09AVR: Fix typos in comment, indentation glitches in avr.md.Georg-Johann Lay1-44/+43
gcc/ * config/avr/avr.md: Fix typos in comment, indentation glitches and some other nits.
2024-03-09LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to ↵Xi Ruoyao2-2/+15
allow the IE to LE linker relaxation In Binutils we need to make IE to LE relaxation only allowed when there is an R_LARCH_RELAX after R_LARCH_TLE_IE_PC_{HI20,LO12} so an invalid "partial" relaxation won't happen with the extreme code model. So if we are emitting %ie_pc_{hi20,lo12} in a non-extreme code model, emit an R_LARCH_RELAX to allow the relaxation. The IE to LE relaxation does not require the pcalau12i and the ld instruction to be adjacent, so we don't need to limit ourselves to use the macro. For the distro maintainers backporting changes: this change depends on r14-8721, without r14-8721 R_LARCH_RELAX can be emitted mistakenly in the extreme code model. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand_reloc): Support 'Q' for R_LARCH_RELAX for TLS IE. (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS IE. * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/tls-ie-relax.c: New test. * gcc.target/loongarch/tls-ie-norelax.c: New test. * gcc.target/loongarch/tls-ie-extreme.c: New test.
2024-03-09AVR: Add cost computation for some insn combine patterns.Georg-Johann Lay2-11/+49
gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for usum_widenqihi and add_zero_extend1. [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend, sub+sign_extend. * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2): Compute exact insn lengths. (*usum_widenqihi3): Allow input operands to commute.
2024-03-09i386: Regenerate i386.opt.urlsJakub Jelinek1-0/+3
When I've added the -mnoreturn-no-callee-saved-registers option to i386.opt, I forgot to regenerate i386.opt.urls and Mark's CI kindly reminded me of that. Fixed thusly. 2024-03-09 Jakub Jelinek <jakub@redhat.com> * config/i386/i386.opt.urls: Regenerate.
2024-03-09LoongArch: Fixed an issue with the implementation of the template ↵Lulu Cheng1-11/+35
atomic_compare_and_swapsi. If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be implemented through "ll.w+sc.w". In the implementation of the instruction sequence, it is necessary to determine whether the two registers are equal. Since LoongArch's comparison instructions do not distinguish between 32-bit and 64-bit, the two operand registers that need to be compared are symbolically extended, and one of the operand registers is obtained from memory through the "ll.w" instruction, which can ensure that the symbolic expansion is carried out. However, the value of the other operand register is not guaranteed to be the value of the sign extension. gcc/ChangeLog: * config/loongarch/sync.md (atomic_cas_value_strong<mode>): In loongarch64, a sign extension operation is added when operands[2] is a register operand and the mode is SImode. gcc/testsuite/ChangeLog: * g++.target/loongarch/atomic-cas-int.C: New test.
2024-03-08bpf: add size threshold for inlining mem builtinsDavid Faust2-1/+29
BPF cannot fall back on library calls to implement memmove, memcpy and memset, so we attempt to expand these inline always if possible. However, this inline expansion was being attempted even for excessively large operations, which could result in gcc consuming huge amounts of memory and hanging. Add a size threshold in the BPF backend below which to always expand these operations inline, and introduce an option -minline-memops-threshold= to control the threshold. Defaults to 1024 bytes. gcc/ * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do not attempt inline expansion if size is above threshold. * config/bpf/bpf.opt (-minline-memops-threshold): New option. * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>: Document. gcc/testsuite/ * gcc.target/bpf/inline-memops-threshold-1.c: New test. * gcc.target/bpf/inline-memops-threshold-2.c: New test.
2024-03-08AVR: Add an insn combine pattern for offset computation.Georg-Johann Lay2-0/+44
Computing uint16_t += 2 * uint8_t can occur when an offset into a 16-bit array is computed. Without this pattern is costs six instructions: A move (1), a zero-extend (1), a shift (2) and an addition (2). With this pattern it costs 4. gcc/ * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern. * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
2024-03-08i386: Guard noreturn no-callee-saved-registers optimization with ↵Jakub Jelinek2-2/+8
-mnoreturn-no-callee-saved-registers [PR38534] The following patch hides the noreturn no_callee_saved_registers (except bp) optimization with a not enabled by default option. The reason is that most noreturn functions should be called just once in a program (unless they are recursive or invoke longjmp or similar, for exceptions we already punt), so it isn't that essential to save a few instructions in their prologue, but more importantly because it interferes with debugging. And unlike most other optimizations, doesn't actually make it harder to debug the given function, which can be solved by recompiling the given function if it is too hard to debug, but makes it harder to debug the callers of that noreturn function. Those can be from a different translation unit, different binary or even different package, so if e.g. glibc abort needs to use all of the callee saved registers (%rbx, %rbp, %r12, %r13, %r14, %r15), debugging any programs which abort will be harder because any DWARF expressions which use those registers will be optimized out, not just in the immediate caller, but in other callers as well until some frame restores a particular register from some stack slot. 2024-03-08 Jakub Jelinek <jakub@redhat.com> PR target/38534 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New option. * config/i386/i386-options.cc (ix86_set_func_type): Don't use TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless ix86_noreturn_no_callee_saved_registers is enabled. * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document. * gcc.target/i386/pr38534-1.c: Add -mnoreturn-no-callee-saved-registers to dg-options. * gcc.target/i386/pr38534-2.c: Likewise. * gcc.target/i386/pr38534-3.c: Likewise. * gcc.target/i386/pr38534-4.c: Likewise. * gcc.target/i386/pr38534-5.c: Likewise. * gcc.target/i386/pr38534-6.c: Likewise. * gcc.target/i386/pr114097-1.c: Likewise. * gcc.target/i386/stack-check-17.c: Likewise.
2024-03-08RISC-V: Fix ICE in riscv vector costsdemin.han1-0/+2
The following code can result in ICE: -march=rv64gcv --param riscv-autovec-lmul=dynamic -O3 char *jpeg_difference7_input_buf; void jpeg_difference7(int *diff_buf) { unsigned width; int samp, Rb; while (--width) { Rb = samp = *jpeg_difference7_input_buf; *diff_buf++ = -(int)(samp + (long)Rb >> 1); } } One biggest_mode update missed in one branch and trigger assertion fail. gcc_assert (biggest_size >= mode_size); Tested On RV64 and no regression. PR target/114264 gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc: Fix ICE gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: New test. Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-03-07AArch64: memcpy/memset expansions should not emit LDP/STP [PR113618]Wilco Dijkstra1-47/+21
The new RTL introduced for LDP/STP results in regressions due to use of UNSPEC. Given the new LDP fusion pass is good at finding LDP opportunities, change the memcpy, memmove and memset expansions to emit single vector loads/stores. This fixes the regression and enables more RTL optimization on the standard memory accesses. Handling of unaligned tail of memcpy/memmove is improved with -mgeneral-regs-only. SPEC2017 performance improves slightly. Codesize is a bit worse due to missed LDP opportunities as discussed in the PR. gcc/ChangeLog: PR target/113618 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove. (aarch64_expand_cpymem): Emit single load/store only. (aarch64_set_one_block): Emit single stores only. gcc/testsuite/ChangeLog: PR target/113618 * gcc.target/aarch64/pr113618.c: New test.
2024-03-07rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]Jeevitha1-2/+2
When we expand the __builtin_vsx_splat_2di built-in, we were allowing immediate value for second operand which causes an unrecognizable insn ICE. Even though the immediate value was forced into a register, it wasn't correctly assigned to the second operand. So corrected the assignment of op1 to operands[1]. 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com> gcc/ PR target/113950 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1 and simplify else if with else. gcc/testsuite/ PR target/113950 * gcc.target/powerpc/pr113950.c: New testcase.
2024-03-07LoongArch: Use /lib instead of /lib64 as the library search path for MUSL.Yang Yujie2-1/+26
gcc/ChangeLog: * config.gcc: Add a case for loongarch*-*-linux-musl*. * config/loongarch/linux.h: Disable the multilib-compatible treatment for *musl* targets. * config/loongarch/musl.h: New file.
2024-03-07RISC-V: Refactor expand_vec_cmp [NFC]demin.han2-31/+15
There are two expand_vec_cmp functions. They have same structure and similar code. We can use default arguments instead of overloading. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-03-06i386: Fix and improve insn constraint for V2QI arithmetic/shift insnsUros Bizjak1-10/+23
optimize_function_for_size_p predicate is not stable during optab selection, because it also depends on node->count/node->frequency of the current function, which are updated during IPA, so they may change between early opts and late opts. Use optimize_size instead - optimize_size implies optimize_function_for_size_p (cfun), so if a named pattern uses "&& optimize_size" and the insn it splits into uses optimize_function_for_size_p (cfun), it shouldn't fail. PR target/114232 gcc/ChangeLog: * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only. (<plusminus:insn>v2qi3): Enable for optimize_size instead of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only. (<any_shift:insn>v2qi3): Enable for optimize_size instead of optimize_function_for_size_p.
2024-03-06RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].Robin Dapp1-48/+48
Three-operand instructions like vmacc are modeled with an implicit output reload when the output does not match one of the operands. For this we use vmv.v.v which is subject to length masking. In a situation where the current vl is less than the full vlenb and the fma's result value is used as input for a vector reduction (which is never length masked) we effectively only reduce vl elements. The masked-out elements are relevant for the reduction, though, leading to a wrong result. This patch replaces the vmv reloads by full-register reloads. gcc/ChangeLog: PR target/114200 PR target/114202 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114200.c: New test. * gcc.target/riscv/rvv/autovec/pr114202.c: New test.
2024-03-06RISC-V: Adjust vec unit-stride load/store costs.Robin Dapp2-10/+86
Scalar loads provide offset addressing while unit-stride vector instructions cannot. The offset must be loaded into a general-purpose register before it can be used. In order to account for this, this patch adds an address arithmetic heuristic that keeps track of data reference operands. If we haven't seen the operand before we add the cost of a scalar statement. This helps to get rid of an lbm regression when vectorizing (roughly 0.5% fewer dynamic instructions). gcc5 improves by 0.2% and deepsjeng by 0.25%. wrf and nab degrade by 0.1%. This is because before we now adjust the cost of SLP as well as loop-vectorized instructions whereas we would only adjust loop-vectorized instructions before. Considering higher scalar_to_vec costs (3 vs 1) for all vectorization types causes some snippets not to get vectorized anymore. Given these costs the decision looks correct but appears worse when just counting dynamic instructions. In total SPECint 2017 has 4 bln dynamic instructions less and SPECfp 0.7 bln. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move... (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store offset handling. (costs::add_stmt_cost): Also adjust cost for statements without stmt_info. * config/riscv/riscv-vector-costs.h: Define zero constant. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c: New test.
2024-03-06ARM: Fix conditional execution [PR113915]Wilco Dijkstra2-2/+9
By default most patterns can be conditionalized on Arm targets. However Thumb-2 predication requires the "predicable" attribute be explicitly set to "yes". Most patterns are shared between Arm and Thumb(-2) and are marked with "predicable". Given this sharing, it does not make sense to use a different default for Arm. So only consider conditional execution of instructions that have the predicable attribute set to yes. This ensures that patterns not explicitly marked as such are never conditionally executed. gcc/ChangeLog: PR target/113915 * config/arm/arm.md (NOCOND): Improve comment. (arm_rev*) Add predicable. * config/arm/arm.cc (arm_final_prescan_insn): Add check for PREDICABLE_YES. gcc/testsuite/ChangeLog: PR target/113915 * gcc.target/arm/builtin-bswap-1.c: Fix test to allow conditional execution both for Arm and Thumb-2.
2024-03-06[PR target/113001] Fix incorrect operand swapping in conditional moveJeff Law1-2/+0
This bug totally fell off my radar. Sorry about that. We have some special casing the conditional move expander to simplify a conditional move when comparing a register against zero and that same register is one of the arms. Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or (ne (reg) (const_int 0)) where reg is the false arm need not use the fully generalized conditional move, thus saving an instruction for those cases. In the NE case we swapped the operands, but didn't swap the condition, which led to the ICE due to an unrecognized pattern. THe backend actually has distinct patterns for those two cases. So swapping the operands is neither needed nor advisable. Regression tested on rv64gc and verified the new tests pass. Pushing to the trunk. PR target/113001 PR target/112871 gcc/ * config/riscv/riscv.cc (expand_conditional_move): Do not swap operands when the comparison operand is the same as the false arm for a NE test. gcc/testsuite * gcc.target/riscv/zicond-ice-3.c: New test. * gcc.target/riscv/zicond-ice-4.c: New test.
2024-03-06i386: Eliminate common code from x86_32 TARGET_MACHO part in ix86_expand_moveUros Bizjak1-26/+11
Eliminate common code from x86_32 TARGET_MACHO part in ix86_expand_move and use generic code instead. No functional changes. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]: Eliminate common code and use generic code instead.
2024-03-06AVR: Adjust rtx cost of plus + zero_extend.Georg-Johann Lay1-0/+7
gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust rtx cost.
2024-03-06aarch64: Define out-of-class static constantsRichard Sandiford1-0/+3
While reworking the aarch64 feature descriptions, I forgot to add out-of-class definitions of some static constants. This could lead to a build failure with some compilers. This was seen with some WIP to increase the number of extensions beyond 64. It's latent on trunk though, and a regression from before the rework. gcc/ * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add out-of-class definitions of static constants.
2024-03-06i386: Fix up the vzeroupper REG_DEAD/REG_UNUSED note workaround [PR114190]Jakub Jelinek1-0/+1
When writing the rest_of_handle_insert_vzeroupper workaround to manually remove all the REG_DEAD/REG_UNUSED notes from the IL, I've missed that there is a df_analyze () call right after it and that the problems added earlier in the pass, like df_note_add_problem () done during mode switching, doesn't affect just the next df_analyze () call right after it, but all other df_analyze () calls until the end of the current pass where df_finish_pass removes the optional problems. So, as can be seen on the following patch, the workaround doesn't actually work there, because while rest_of_handle_insert_vzeroupper carefully removes all REG_DEAD/REG_UNUSED notes, the df_analyze () call at the end of the function immediately adds them in again (so, I must say I have no idea why the workaround worked on the earlier testcases). Now, I could move the df_analyze () call just before the REG_DEAD/REG_UNUSED note removal loop, but I think the following patch is better, because the df_analyze () call doesn't have to recompute the problem when we don't care about it and will actively strip all traces of it away. 2024-03-06 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/114190 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper): Call df_remove_problem for df_note before calling df_analyze. * gcc.target/i386/avx-pr114190.c: New test.
2024-03-05aarch64: Remove SME2.1 forms of LUTI2/4Richard Sandiford3-90/+3
I was over-eager when adding support for strided SME2 instructions and accidentally included forms of LUTI2 and LUTI4 that are only available with SME2.1, not SME2. This patch removes them for now. We're planning to add proper support for SME2.1 in the GCC 15 timeframe. Sorry for the blunder :( gcc/ * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive and luti_strided. * config/aarch64/aarch64-sme.md (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute. (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete. (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise. * config/aarch64/aarch64-early-ra.cc (is_stride_candidate) (early_ra::maybe_convert_to_strided_access): Remove support for strided LUTI2 and LUTI4. gcc/testsuite/ * gcc.target/aarch64/sme/strided_1.c (test5): Remove.
2024-03-05arm: check for low register before applying peephole [PR113510]Richard Earnshaw1-1/+1
For thumb1, when using a peephole to fuse mov reg, #const add reg, reg, SP into add reg, SP, #const we must first check that reg is a low register, otherwise we will ICE when trying to recognize the resulting insn. gcc/ChangeLog: PR target/113510 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use low_register_operand.
2024-03-05AVR: Add two RTL peepholes.Georg-Johann Lay1-3/+58
Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST because 1) the first insn may use MOVW for "X = Y", and 2) the operation may be more efficient when performed with a constant, for example when ADIW or SBIW can be used, or some bytes of the constant are 0x00 or 0xff. gcc/ * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND in HI, PSI, SI that swap operation order from "X = CST, X o= Y" to "X = Y, X o= CST".
2024-03-05LoongArch: Allow s9 as a register aliasXi Ruoyao1-0/+1
The psABI allows using s9 as an alias of r22. gcc/ChangeLog: * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add s9 as an alias of r22. gcc/testsuite/ChangeLog: * gcc.target/loongarch/regname-fp-s9.c: New test.
2024-03-05AVR: Improve output of insn "*insv.any_shift.<mode>_split".Roger Sayle4-51/+244
The instructions printed by insn "*insv.any_shift.<mode>_split" were sub-optimal. The code to print the improved output is lengthy and performed by new function avr_out_insv. As it turns out, the function can also handle shift-offsets of zero, which is "*andhi3", "*andpsi3" and "*andsi3". Thus, these tree insns get a new 3-operand alternative where the 3rd operand is an exact power of 2. gcc/ * config/avr/avr-protos.h (avr_out_insv): New proto. * config/avr/avr.cc (avr_out_insv): New function. (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case. (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs. * config/avr/avr.md (define_attr "adjust_len") Add insv. (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3): Add constraint alternative where the 3rd operand is a power of 2, and the source register may differ from the destination. (*insv.any_shift.<mode>_split): Call avr_out_insv to output instructions. Set attr "length" to "insv". * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints. gcc/testsuite/ * gcc.target/avr/torture/insv-anyshift-hi.c: New test. * gcc.target/avr/torture/insv-anyshift-si.c: New test.
2024-03-05i386: For noreturn functions save at least the bp register if it is used ↵Jakub Jelinek3-17/+33
[PR114116] As mentioned in the PR, on x86_64 currently a lot of ICEs end up with crashes in the unwinder like: during RTL pass: expand pr114044-2.c: In function ‘foo’: pr114044-2.c:5:3: internal compiler error: in expand_fn_using_insn, at internal-fn.cc:208 5 | __builtin_clzg (a); | ^~~~~~~~~~~~~~~~~~ 0x7d9246 expand_fn_using_insn ../../gcc/internal-fn.cc:208 pr114044-2.c:5:3: internal compiler error: Segmentation fault 0x1554262 crash_signal ../../gcc/toplev.cc:319 0x2b20320 x86_64_fallback_frame_state ./md-unwind-support.h:63 0x2b20320 uw_frame_state_for ../../../libgcc/unwind-dw2.c:1013 0x2b2165d _Unwind_Backtrace ../../../libgcc/unwind.inc:303 0x2acbd69 backtrace_full ../../libbacktrace/backtrace.c:127 0x2a32fa6 diagnostic_context::action_after_output(diagnostic_t) ../../gcc/diagnostic.cc:781 0x2a331bb diagnostic_action_after_output(diagnostic_context*, diagnostic_t) ../../gcc/diagnostic.h:1002 0x2a331bb diagnostic_context::report_diagnostic(diagnostic_info*) ../../gcc/diagnostic.cc:1633 0x2a33543 diagnostic_impl ../../gcc/diagnostic.cc:1767 0x2a33c26 internal_error(char const*, ...) ../../gcc/diagnostic.cc:2225 0xe232c8 fancy_abort(char const*, int, char const*) ../../gcc/diagnostic.cc:2336 0x7d9246 expand_fn_using_insn ../../gcc/internal-fn.cc:208 Segmentation fault (core dumped) The problem are the PR38534 r14-8470 changes which avoid saving call-saved registers in noreturn functions. If such functions ever touch the bp register but because of the r14-8470 changes don't save it in the prologue, the caller or any other function in the backtrace uses a frame pointer and the noreturn function or anything it calls directly or indirectly calls backtrace, then the unwinder crashes, because bp register contains some unrelated value, but in the frames which do use frame pointer CFA is based on the bp register. In theory this could happen with any other call-saved register, e.g. code written by hand in assembly with .cfi_* directives could use any other call-saved register as register into which store the CFA or something related to that, but in reality at least compiler generated code and usual assembly probably just making sure bp doesn't contain garbage could be enough for backtrace purposes. In the debugger of course it will not be enough, the values of the arguments etc. can be lost (if DW_CFA_undefined is emitted) or garbage. So, I think for noreturn function we should at least save the bp register if we use it. If user asks for it using no_callee_saved_registers attribute, let's honor what is asked for (but then it is up to the user to make sure e.g. backtrace isn't called from the function or anything it calls). As discussed in the PR, whether to save bp or not shouldn't be based on whether compiling with -g or -g0, because we don't want code generation changes without/with debugging, it would also break -fcompare-debug, and users can call backtrace(3), that doesn't use debug info, just unwind info, even backtrace_symbols{,_fd}(3) don't use debug info but just looks at dynamic symbol table. The patch also adds check for no_caller_saved_registers attribute in the implicit addition of not saving callee saved register in noreturn functions, because on I think __attribute__((no_caller_saved_registers, noreturn)) will otherwise error that no_caller_saved_registers and no_callee_saved_registers attributes are incompatible (but user didn't specify anything like that). 2024-03-05 Jakub Jelinek <jakub@redhat.com> PR target/114116 * config/i386/i386.h (enum call_saved_registers_type): Add TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator. * config/i386/i386-options.cc (ix86_set_func_type): Remove has_no_callee_saved_registers variable, add no_callee_saved_registers instead, initialize it depending on whether it is no_callee_saved_registers function or not. Don't set it if no_caller_saved_registers attribute is present. Adjust users. * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like TYPE_NO_CALLEE_SAVED_REGISTERS. (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP. * gcc.target/i386/pr38534-1.c: Allow push/pop of bp. * gcc.target/i386/pr38534-4.c: Likewise. * gcc.target/i386/pr38534-2.c: Likewise. * gcc.target/i386/pr38534-3.c: Likewise. * gcc.target/i386/pr114097-1.c: Likewise. * gcc.target/i386/stack-check-17.c: Expect no pop on ! ia32.
2024-03-05RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]Pan Li1-4/+0
Cleanup mode_size related code which is not used anymore. Below tests are passed for this patch. * The RVV fully regresssion test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused mode_size related code. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-04bpf: add inline memset expansionDavid Faust3-0/+84
Similar to memmove and memcpy, the BPF backend cannot fall back on a library call to implement __builtin_memset, and should always expand calls to it inline if possible. This patch implements simple inline expansion of memset in the BPF backend in a verifier-friendly way. Similar to memcpy and memmove, the size must be an integer constant, as is also required by clang. gcc/ * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype. * config/bpf/bpf.cc (bpf_expand_setmem): New. * config/bpf/bpf.md (setmemdi): New define_expand. gcc/testsuite/ * gcc.target/bpf/memset-1.c: New test.
2024-03-04arm: Fix a wrong attribute use and remove unused unspecs and iteratorsAndre Vieira3-10/+4
This patch fixes the erroneous use of a mode attribute without a mode iterator in the pattern and removes unused unspecs and iterators. gcc/ChangeLog: * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U cases. (VMLALDAVXQ): Remove iterator. (VMLALDAVXQ_P): Likewise. (VMLALDAVAXQ): Likewise. * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED> mode iterator attribute with V4BI mode. * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U): Remove unused unspecs.
2024-03-04arm: Annotate instructions with mve_safe_imp_xlane_predAndre Vieira3-0/+26
This patch annotates some MVE across lane instructions with a new attribute. We use this attribute to let the compiler know that these instructions can be safely implicitly predicated when tail predicating if their operands are guaranteed to have zeroed tail predicated lanes. These instructions were selected because having the value 0 in those lanes or 'tail-predicating' those lanes have the same effect. gcc/ChangeLog: * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute. * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator attribute. * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u, vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u, vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u, vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s, vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s, vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u, vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u, vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s, vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s, vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
2024-03-04arm: Add define_attr to to create a mapping between MVE predicated and ↵Stam Markianos-Wright4-305/+625
unpredicated insns This patch adds an attribute to the mve md patterns to be able to identify predicable MVE instructions and what their predicated and unpredicated variants are. This attribute is used to encode the icode of the unpredicated variant of an instruction in its predicated variant. This will make it possible for us to transform VPT-predicated insns in the insn chain into their unpredicated equivalents when transforming the loop into a MVE Tail-Predicated Low Overhead Loop. For example: `mve_vldrbq_z_<supf><mode> -> mve_vldrbq_<supf><mode>`. gcc/ChangeLog: * config/arm/arm.md (mve_unpredicated_insn): New attribute. * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define. (MVE_VPT_UNPREDICATED_INSN_P): Likewise. (MVE_VPT_PREDICABLE_INSN_P): Likewise. * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute. * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute. (arm_vcx1q<a>v16qi): Likewise. (arm_vcx1qav16qi): Likewise. (arm_vcx1qv16qi): Likewise. (arm_vcx2q<a>_p_v16qi): Likewise. (arm_vcx2q<a>v16qi): Likewise. (arm_vcx2qav16qi): Likewise. (arm_vcx2qv16qi): Likewise. (arm_vcx3q<a>_p_v16qi): Likewise. (arm_vcx3q<a>v16qi): Likewise. (arm_vcx3qav16qi): Likewise. (arm_vcx3qv16qi): Likewise. (@mve_<mve_insn>q_<supf><mode>): Likewise. (@mve_<mve_insn>q_int_<supf><mode>): Likewise. (@mve_<mve_insn>q_<supf>v4si): Likewise. (@mve_<mve_insn>q_n_<supf><mode>): Likewise. (@mve_<mve_insn>q_r_<supf><mode>): Likewise. (@mve_<mve_insn>q_f<mode>): Likewise. (@mve_<mve_insn>q_m_<supf><mode>): Likewise. (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise. (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise. (@mve_<mve_insn>q_m_f<mode>): Likewise. (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise. (@mve_<mve_insn>q_p_<supf>v4si): Likewise. (@mve_<mve_insn>q_p_<supf><mode>): Likewise. (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise. (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise. (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise. (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise. (mve_v<absneg_str>q_f<mode>): Likewise. (mve_<mve_addsubmul>q<mode>): Likewise. (mve_<mve_addsubmul>q_f<mode>): Likewise. (mve_vadciq_<supf>v4si): Likewise. (mve_vadciq_m_<supf>v4si): Likewise. (mve_vadcq_<supf>v4si): Likewise. (mve_vadcq_m_<supf>v4si): Likewise. (mve_vandq_<supf><mode>): Likewise. (mve_vandq_f<mode>): Likewise. (mve_vandq_m_<supf><mode>): Likewise. (mve_vandq_m_f<mode>): Likewise. (mve_vandq_s<mode>): Likewise. (mve_vandq_u<mode>): Likewise. (mve_vbicq_<supf><mode>): Likewise. (mve_vbicq_f<mode>): Likewise. (mve_vbicq_m_<supf><mode>): Likewise. (mve_vbicq_m_f<mode>): Likewise. (mve_vbicq_m_n_<supf><mode>): Likewise. (mve_vbicq_n_<supf><mode>): Likewise. (mve_vbicq_s<mode>): Likewise. (mve_vbicq_u<mode>): Likewise. (@mve_vclzq_s<mode>): Likewise. (mve_vclzq_u<mode>): Likewise. (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise. (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise. (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise. (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise. (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise. (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise. (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise. (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise. (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise. (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise. (mve_vcvtaq_<supf><mode>): Likewise. (mve_vcvtaq_m_<supf><mode>): Likewise. (mve_vcvtbq_f16_f32v8hf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtbq_m_f16_f32v8hf): Likewise. (mve_vcvtbq_m_f32_f16v4sf): Likewise. (mve_vcvtmq_<supf><mode>): Likewise. (mve_vcvtmq_m_<supf><mode>): Likewise. (mve_vcvtnq_<supf><mode>): Likewise. (mve_vcvtnq_m_<supf><mode>): Likewise. (mve_vcvtpq_<supf><mode>): Likewise. (mve_vcvtpq_m_<supf><mode>): Likewise. (mve_vcvtq_from_f_<supf><mode>): Likewise. (mve_vcvtq_m_from_f_<supf><mode>): Likewise. (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise. (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise. (mve_vcvtq_m_to_f_<supf><mode>): Likewise. (mve_vcvtq_n_from_f_<supf><mode>): Likewise. (mve_vcvtq_n_to_f_<supf><mode>): Likewise. (mve_vcvtq_to_f_<supf><mode>): Likewise. (mve_vcvttq_f16_f32v8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvttq_m_f16_f32v8hf): Likewise. (mve_vcvttq_m_f32_f16v4sf): Likewise. (mve_vdwdupq_m_wb_u<mode>_insn): Likewise. (mve_vdwdupq_wb_u<mode>_insn): Likewise. (mve_veorq_s><mode>): Likewise. (mve_veorq_u><mode>): Likewise. (mve_veorq_f<mode>): Likewise. (mve_vidupq_m_wb_u<mode>_insn): Likewise. (mve_vidupq_u<mode>_insn): Likewise. (mve_viwdupq_m_wb_u<mode>_insn): Likewise. (mve_viwdupq_wb_u<mode>_insn): Likewise. (mve_vldrbq_<supf><mode>): Likewise. (mve_vldrbq_gather_offset_<supf><mode>): Likewise. (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise. (mve_vldrbq_z_<supf><mode>): Likewise. (mve_vldrdq_gather_base_<supf>v2di): Likewise. (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise. (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise. (mve_vldrdq_gather_base_z_<supf>v2di): Likewise. (mve_vldrdq_gather_offset_<supf>v2di): Likewise. (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise. (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise. (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise. (mve_vldrhq_<supf><mode>): Likewise. (mve_vldrhq_fv8hf): Likewise. (mve_vldrhq_gather_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_offset_fv8hf): Likewise. (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise. (mve_vldrhq_gather_offset_z_fv8hf): Likewise. (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise. (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise. (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise. (mve_vldrhq_z_<supf><mode>): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrwq_<supf>v4si): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_gather_base_<supf>v4si): Likewise. (mve_vldrwq_gather_base_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_z_<supf>v4si): Likewise. (mve_vldrwq_gather_base_z_fv4sf): Likewise. (mve_vldrwq_gather_offset_<supf>v4si): Likewise. (mve_vldrwq_gather_offset_fv4sf): Likewise. (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise. (mve_vldrwq_gather_offset_z_fv4sf): Likewise. (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise. (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise. (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise. (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise. (mve_vldrwq_z_<supf>v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vmvnq_s<mode>): Likewise. (mve_vmvnq_u<mode>): Likewise. (mve_vornq_<supf><mode>): Likewise. (mve_vornq_f<mode>): Likewise. (mve_vornq_m_<supf><mode>): Likewise. (mve_vornq_m_f<mode>): Likewise. (mve_vornq_s<mode>): Likewise. (mve_vornq_u<mode>): Likewise. (mve_vorrq_<supf><mode>): Likewise. (mve_vorrq_f<mode>): Likewise. (mve_vorrq_m_<supf><mode>): Likewise. (mve_vorrq_m_f<mode>): Likewise. (mve_vorrq_m_n_<supf><mode>): Likewise. (mve_vorrq_n_<supf><mode>): Likewise. (mve_vorrq_s<mode>): Likewise. (mve_vorrq_s<mode>): Likewise. (mve_vsbciq_<supf>v4si): Likewise. (mve_vsbciq_m_<supf>v4si): Likewise. (mve_vsbcq_<supf>v4si): Likewise. (mve_vsbcq_m_<supf>v4si): Likewise. (mve_vshlcq_<supf><mode>): Likewise. (mve_vshlcq_m_<supf><mode>): Likewise. (mve_vshrq_m_n_<supf><mode>): Likewise. (mve_vshrq_n_<supf><mode>): Likewise. (mve_vstrbq_<supf><mode>): Likewise. (mve_vstrbq_p_<supf><mode>): Likewise. (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise. (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise. (mve_vstrdq_scatter_base_<supf>v2di): Likewise. (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise. (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise. (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise. (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise. (mve_vstrhq_<supf><mode>): Likewise. (mve_vstrhq_fv8hf): Likewise. (mve_vstrhq_p_<supf><mode>): Likewise. (mve_vstrhq_p_fv8hf): Likewise. (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise. (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. (mve_vstrwq_<supf>v4si): Likewise. (mve_vstrwq_fv4sf): Likewise. (mve_vstrwq_p_<supf>v4si): Likewise. (mve_vstrwq_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_<supf>v4si): Likewise. (mve_vstrwq_scatter_base_fv4sf): Likewise. (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise. (mve_vstrwq_scatter_base_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise. (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
2024-03-04Regenerate opt.urlsMark Wielaard5-6/+24
There were several commits that didn't regenerate the opt.urls files. Fixes: 438ef143679e ("rs6000: Neuter option -mpower{8,9}-vector") Fixes: 50c549ef3db6 ("gccrs: enable -Winfinite-recursion warnings by default") Fixes: 25bb8a40abd9 ("Move docs for -Wuse-after-free and -Wuseless-cast") Fixes: 48448055fb70 ("AVR: Support .rodata in Flash for AVR64* and AVR128*") Fixes: 42503cc257fb ("AVR: Document option -mskip-bug") Fixes: 7de5bb642c12 ("i386: [APX] Document inline asm behavior and new switch") Fixes: 49a14ee488b8 ("Add -mevex512 into invoke.texi") Fixes: 4666cbde5e6d ("Sort warning options in c-family/c.opt.") Fixes: cda383616183 ("AVR: target/114100 - Better indirect accesses for reduced Tiny") gcc/c-family/ChangeLog: * c.opt.urls: Regenerate. gcc/ChangeLog: * common.opt.urls: Regenerate. * config/avr/avr.opt.urls: Likewise. * config/i386/i386.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rs6000/rs6000.opt.urls: Likewise. gcc/rust/ChangeLog: * lang.opt.urls: Regenerate.
2024-03-04i386: Fix ICEs with SUBREGs from vector etc. constants to XFmode [PR114184]Jakub Jelinek1-0/+14
The Intel extended format has the various weird number categories, pseudo denormals, pseudo infinities, pseudo NaNs and unnormals. Those are not representable in the GCC real_value and so neither GIMPLE nor RTX VIEW_CONVERT_EXPR/SUBREG folding folds those into constants. As can be seen on the following testcase, because it isn't folded (since GCC 12, before that we were folding it) we can end up with a SUBREG of a CONST_VECTOR or similar constant, which isn't valid general_operand, so we ICE during vregs pass trying to recognize the move instruction. Initially I thought it is a middle-end bug, the movxf instruction has general_operand predicate, but the middle-end certainly never tests that predicate, seems moves are special optabs. And looking at other mov optabs, e.g. for vector modes the i386 patterns use nonimmediate_operand predicate on the input, yet ix86_expand_vector_move deals with CONSTANT_P and SUBREG of CONSTANT_P arguments which if the predicate was checked couldn't ever make it through. The following patch handles this case similarly to the ix86_expand_vector_move's SUBREG of CONSTANT_P case, does it just for XFmode because I believe that is the only mode that needs it from the scalar ones, others should just be folded. 2024-03-04 Jakub Jelinek <jakub@redhat.com> PR target/114184 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or register. * gcc.target/i386/pr114184.c: New test.
2024-03-03AVR: Use more C++ ish coding style.Georg-Johann Lay5-295/+202
gcc/ * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED. Use bool in place of int for boolean logic (if possible). Move declarations to definitions (if possible). * config/avr/avr.md: Use C++ comments. Fix some indentation glitches. * config/avr/avr-dimode.md: Same. * config/avr/constraints.md: Same. * config/avr/predicates.md: Same.
2024-03-03alpha: Introduce UMUL_HIGHPART rtx_code [PR113720]Uros Bizjak1-34/+3
umuldi3_highpart expander does: if (REG_P (operands[2])) operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); on register_operand predicate, which also allows SUBREG RTX. So, subregs were emitted without ZERO_EXTEND RTX. But nowadays we have UMUL_HIGHPART that allows us to fix this issue while also simplifying the instruction RTX. PR target/113720 gcc/ChangeLog: * config/alpha/alpha.md (umuldi3_highpart): Remove expander. (*umuldi3_highpart_reg): Rename to umuldi3_highpart and simplify insn RTX using UMUL_HIGHPART rtx_code. (*umuldi3_highpart_const): Remove.
2024-03-03AVR: ad target/114100 - Don't print unused frame pointer adjustments.Georg-Johann Lay2-16/+21
Without -mfuse-add, when fake reg+offset addressing is used, the output routines are saving some instructions when the base reg is unused after. This patch adds that optimization for the case when the base is the frame pointer and the frame pointer adjustments are split away from the move insn by -mfuse-add in .split2. Direct usage of reg_unused_after is not possible because that function looks at the destination of the current insn, which won't work for offsetting the frame pointer in printing PLUS code. It can use an extended version of _reg_unused_after though. gcc/ PR target/114100 * config/avr/avr-protos.h (_reg_unused_after): Remove proto. * config/avr/avr.cc (_reg_unused_after): Make static. And add 3rd argument to skip the current insn. (reg_unused_after): Adjust call of reg_unused_after. (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output unneeded frame pointer adjustments.
2024-03-03AVR: ad target/92792 - Remove insn attribute "cc" and its (dead) uses.Georg-Johann Lay3-51/+16
The backend has remains of cc0 condition code. Unfortunately, all that information is useless with CCmode, and their use was removed with the removal of NOTICE_UPDATE_CC in PR92729 with r12-226 and r12-327. gcc/ PR target/92729 * config/avr/avr.md (define_attr "cc"): Remove. * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument from prototype. * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and its uses. Add insn argument. (avr_out_plus_symbol): Remove pcc argument and its uses. (avr_out_plus): Remove pcc argument and its uses. Adjust calls of avr_out_plus_symbol and avr_out_plus_1. (avr_out_round): Adjust call of avr_out_plus.
2024-03-03AVR: Fix a typo in avr.cc.Georg-Johann Lay1-2/+3
gcc/ * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo from r14-9273.
2024-03-03SH: Fix 101737Oleg Endo1-1/+2
gcc/ChangeLog: PR target/101737 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input is not an insn, but e.g. a code label.
2024-03-02AVR: Use REG_<n> constants instead of magic numbers <n>.Georg-Johann Lay2-39/+52
There are some places where avr.cc uses magic numbers like 17 that are actually register numbers. This patch defines constants like REG_17 and uses them instead of the magic numbers when a register number is meant. gcc/ * config/avr/avr.md (REG_0, ... REG_36): New define_constants. * config/avr/avr.cc: Use them instead of magic numbers when it means a register number.
2024-03-02AVR: Adjust some comments.Georg-Johann Lay1-10/+18
gcc/ * config/avr/avr.cc: Adjust some comments.
2024-03-02AVR: target/114100 - Factor in -mtiny-stack in frame pointer adjustmentsGeorg-Johann Lay1-5/+8
gcc/ PR target/114100 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust the low part of the frame pointer with 8-bit stack pointer.
2024-03-01[14 regression] Fix insn types in risc-v portJeff Law1-14/+14
So one of the broad goals we've had over the last few months has been to ensure that every insn has a scheduling type and that every insn is associated with an insn reservation in the scheduler. This avoids some amazingly bad behavior in the scheduler. I won't go through the gory details. I was recently analyzing a code quality regression with dhrystone (ugh!) and one of the issues was poor scheduling which lengthened the lifetime of a pseudo and ultimately resulted in needing an additional callee saved register save/restore. This was ultimately tracked down incorrect types on a few patterns. So I did an audit of all the patterns that had types added/changed as part of this effort and found a variety of problems, primarily in the various move patterns and extension patterns. This is a regression relative to gcc-13. Naturally the change in types affects scheduling, which in turn changes the precise code we generate and causes some testsuite fallout. I considered updating the regexps since the change in the resulting output is pretty consistent. But of course the test would still be sensitive to things like load latency. So instead I just turned off the 2nd phase scheduler in the affected tests. Bootstrapped and regression tested on rv64gc-linux-gnu. gcc * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix type attribute. (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. (movdi_32bit, movdi_64bit, movsi_internal): Likewise. (movhi_internal, movqi_internal): Likewise. (movsf_softfloat, movsf_hardfloat): Likewise. (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. (movdf_softfloat): Likewise. gcc/testsuite * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off second phase scheduler. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
2024-03-01AVR: Overhaul help screenGeorg-Johann Lay1-18/+18
gcc/ * config/avr/avr.opt: Overhaul help screen.
2024-03-01RISC-V: Add riscv_vector_cc function attributexuli1-8/+47
Standard vector calling convention variant will only enabled when function has vector argument or returning value by default, however user may also want to invoke function without that during a vectorized loop at some situation, but it will cause a huge performance penalty due to vector register store/restore. So user can declare function with this riscv_vector_cc attribute like below, that could enforce function will use standard vector calling convention variant. void foo() __attribute__((riscv_vector_cc)); [[riscv::vector_cc]] void foo(); // For C++11 and C23 For more details please reference the below link. https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 gcc/ChangeLog: * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc attribute to riscv_attribute_table. (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function. (riscv_fntype_abi): Add riscv_vector_cc attribute check. * doc/extend.texi: Add riscv_vector_cc attribute description. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
2024-03-01RISC-V: Introduce gcc option mrvv-vector-bits for RVVPan Li6-42/+45
This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * scalable * zvl The scalable will pick up the zvl*b in the march as the minimal vlen. For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b and mrvv-vector-bits=scalable. The zvl will pick up the zvl*b in the march as exactly vlen. For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl. The internal option --param=riscv-autovec-preference will be replaced by option -mrvv-vector-bits. Aka: * -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable * -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none. The internal option --param=riscv-autovec-preference is unavailable after this patch. Given below sample for more details: void test_rvv_vector_bits () { vint32m1_t x; asm volatile ("def %0": "=vr"(x)); asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); asm volatile ("use %0": : "vr"(x)); } With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128) csrr t0,vlenb sub sp,sp,t0 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 csrr t0,vlenb add sp,sp,t0 jr ra With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128) addi sp,sp,-16 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 addi sp,sp,16 jr ra The below test are passed for this patch. * The riscv fully regression test. PR target/112817 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove. (enum rvv_vector_bits_enum): New enum for different RVV vector bits. * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update comments for option replacement. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of riscv_autovec_preference to rvv_vector_bits. (vls_mode_valid_p): Ditto. (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to vector chunks and honor new option mrvv-vector-bits. (riscv_override_options_internal): Update comments and rename the vector chunks. * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove internal option param=riscv-autovec-preference. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: Replace param=riscv-autovec-preference to mrvv-vector-bits. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto. * gcc.target/riscv/rvv/autovec/align-1.c: Ditto. * gcc.target/riscv/rvv/autovec/align-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito. * gcc.target/riscv/rvv/autovec/pr110950.c: Diito. * gcc.target/riscv/rvv/autovec/pr110964.c: Diito. * gcc.target/riscv/rvv/autovec/pr110989.c: Diito. * gcc.target/riscv/rvv/autovec/pr111232.c: Diito. * gcc.target/riscv/rvv/autovec/pr111295.c: Diito. * gcc.target/riscv/rvv/autovec/pr111313.c: Diito. * gcc.target/riscv/rvv/autovec/pr112326.c: Diito. * gcc.target/riscv/rvv/autovec/pr112552.c: Diito. * gcc.target/riscv/rvv/autovec/pr112554.c: Diito. * gcc.target/riscv/rvv/autovec/pr112561.c: Diito. * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito. * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112854.c: Diito. * gcc.target/riscv/rvv/autovec/pr112872.c: Diito. * gcc.target/riscv/rvv/autovec/pr112999.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito. * gcc.target/riscv/rvv/autovec/series-1.c: Diito. * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/v-1.c: Diito. * gcc.target/riscv/rvv/autovec/v-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-1.c: Diito. * gcc.target/riscv/rvv/base/cpymem-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-0.c: Diito. * gcc.target/riscv/rvv/base/pr111720-1.c: Diito. * gcc.target/riscv/rvv/base/pr111720-10.c: Diito. * gcc.target/riscv/rvv/base/pr111720-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-3.c: Diito. * gcc.target/riscv/rvv/base/pr111720-4.c: Diito. * gcc.target/riscv/rvv/base/pr111720-5.c: Diito. * gcc.target/riscv/rvv/base/pr111720-6.c: Diito. * gcc.target/riscv/rvv/base/pr111720-7.c: Diito. * gcc.target/riscv/rvv/base/pr111720-8.c: Diito. * gcc.target/riscv/rvv/base/pr111720-9.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito. * gcc.target/riscv/rvv/rvv.exp: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito. * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito. * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay5-1/+832
The Reduced Tiny core does not support indirect addressing with offset, which basically means that every indirect memory access with a size of more than one byte is effectively POST_INC or PRE_DEC. The lack of that addressing mode is currently handled by pretending to support it, and then let the insn printers add and subtract again offsets as needed. For example, the following C code int vars[10]; void inc_var2 (void) { ++vars[2]; } is compiled to: ldi r30,lo8(vars) ; 14 [c=4 l=2] *movhi/4 ldi r31,hi8(vars) subi r30,lo8(-(4)) ; 15 [c=8 l=6] *movhi/2 sbci r31,hi8(-(4)) ld r20,Z+ ld r21,Z subi r30,lo8((4+1)) sbci r31,hi8((4+1)) subi r20,-1 ; 16 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 subi r30,lo8(-(4+1)) ; 17 [c=4 l=4] *movhi/3 sbci r31,hi8(-(4+1)) st Z,r21 st -Z,r20 where the code could be -- and with this patch actually is -- like ldi r30,lo8(vars+4) ; 28 [c=4 l=2] *movhi/4 ldi r31,hi8(vars+4) ld r20,Z+ ; 17 [c=8 l=2] *movhi/2 ld r21,Z+ subi r20,-1 ; 19 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 st -Z,r21 ; 30 [c=4 l=2] *movhi/3 st -Z,r20 This is achieved in two steps: - A post-reload split into "real" instructions during .split2. - A new avr-specific mini pass .avr-fuse-add that runs before RTL peephole and that tries to combine the generated pointer additions into memory accesses to form POST_INC or PRE_DEC. gcc/ PR target/114100 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. * config/avr/avr.opt (-mfuse-add=): New target option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. * config/avr/avr-protos.h (avr_split_tiny_move) (make_avr_pass_fuse_add): New protos. * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses avr_split_tiny_move to split indirect memory accesses. (gen_move_clobbercc): New define_expand helper. * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. (avr_pass_fuse_add): New class from rtl_opt_pass. (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets of PLUS addressing for AVR_TINY. (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
generated by cgit v1.1 at 2025-09-19 23:17:03 +0000