aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Collapse)AuthorFilesLines
2024-02-29AVR: target/114132 - Code sets up a frame pointer without need.Georg-Johann Lay2-1/+10
The condition CUMULATIVE_ARGS.nregs == 0 in avr_frame_pointer_required_p() means that no more argument registers are left, but that's not the same condition that tells whether an argument pointer is required. PR target/114132 gcc/ * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field. * config/avr/avr.cc (avr_init_cumulative_args): Initialize it. (avr_function_arg): Set it. (avr_frame_pointer_required_p): Use it instead of .nregs. gcc/testsuite/ * gcc.target/avr/pr114132-1.c: New test. * gcc.target/avr/torture/pr114132-2.c: New test.
2024-02-28aarch64: Fix memtag builtins vs GC [PR108174]Andrew Pinski1-1/+1
The memtag builtins were being GC'ed away so we end up with a crash sometimes (maybe even wrong code). This fixes that issue by adding GTY on the variable/struct aarch64_memtag_builtin_data. Committed as obvious after a build/test for aarch64-linux-gnu. PR target/108174 gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make static and mark with GTY. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/memtag_4.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-02-29LoongArch: Remove unneeded sign extension after crc/crcc instructionsXi Ruoyao1-0/+11
The specification of crc/crcc instructions is clear that the output is sign-extended to GRLEN. Add a define_insn to tell the compiler this fact and allow it to remove the unneeded sign extension on crc/crcc output. As crc/crcc instructions are usually used in a tight loop, this should produce a significant performance gain. gcc/ChangeLog: * config/loongarch/loongarch.md (loongarch_<crc>_w_<size>_w_extended): New define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/crc-sext.c: New test;
2024-02-29LoongArch: NFC: Deduplicate crc instruction definesXi Ruoyao1-13/+5
Introduce an iterator for UNSPEC_CRC and UNSPEC_CRCC to make the next change easier. gcc/ChangeLog: * config/loongarch/loongarch.md (CRC): New define_int_iterator. (crc): New define_int_attr. (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify into ... (loongarch_<crc>_w_<size>_w): ... here.
2024-02-29RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64Kito Cheng1-0/+9
atomic_compare_and_swapsi will use lr.w to do obtain the original value, which sign extends to DI. RV64 only has DI comparisons, so we also need to sign extend the expected value to DI as otherwise the comparison will fail when the expected value has the 32nd bit set. gcc/ChangeLog: PR target/114130 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign extend the expected value if needed. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114130.c: New. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-28bpf: renames coreout.* files to btfext-out.*.Cupertino Miranda5-7/+7
gcc/ChangeLog: * config.gcc (target_gtfiles): Change coreout to btfext-out. (extra_objs): Change coreout to btfext-out. * config/bpf/coreout.cc: Rename to btfext-out.cc. * config/bpf/btfext-out.cc: Add. * config/bpf/coreout.h: Rename to btfext-out.h. * config/bpf/btfext-out.h: Add. * config/bpf/core-builtins.cc: Change include. * config/bpf/core-builtins.h: Change include. * config/bpf/t-bpf: Accomodate renamed files.
2024-02-28bpf: implementation of func_info in .BTF.ext.Cupertino Miranda3-156/+390
Kernel verifier complains in some particular cases for missing func_info implementation in .BTF.ext. This patch implements it. Strings are cached locally in coreout.cc to avoid adding duplicated strings in the string list. This string deduplication should eventually be moved to the CTFC functions such that this happens widely. With this implementation, the CO-RE relocations information was also simplified and integrated with the FuncInfo structures. gcc/Changelog: PR target/113453 * config/bpf/bpf.cc (bpf_function_prologue): Define target hook. * config/bpf/coreout.cc (brf_ext_info_section) (btf_ext_info): Move from coreout.h (btf_ext_funcinfo, btf_ext_lineinfo): Add struct. (bpf_core_reloc): Rename to btf_ext_core_reloc. (btf_ext): Add static variable. (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN) (bpf_create_or_find_funcinfo, bpt_create_core_reloc) (btf_ext_add_string, btf_funcinfo_type_callback) (btf_add_func_info_for, btf_validate_funcinfo) (btf_ext_info_len, output_btfext_func_info): Add function. (output_btfext_header, bpf_core_reloc_add) (output_btfext_core_relocs, btf_ext_init, btf_ext_output): Change to support new structs. * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo): Move and change in coreout.cc. (btf_add_func_info_for, btf_ext_add_string): Add prototypes. gcc/testsuite/ChangeLog: PR target/113453 * gcc.target/bpf/btfext-funcinfo-nocore.c: Add. * gcc.target/bpf/btfext-funcinfo.c: Add. * gcc.target/bpf/core-attr-5.c: Fix regexp. * gcc.target/bpf/core-attr-6.c: Fix regexp. * gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: Fix regexp. * gcc.target/bpf/core-section-1.c: Fix regexp.
2024-02-28bpf: Always emit .BTF.ext section if generating BTFCupertino Miranda1-11/+9
BPF applications, when generating BTF information should always create a .BTF.ext section. Current implementation was only creating it when -mco-re option was used. This patch makes .BTF.ext always be generated for BPF target objects. The patch also adds conditions around btf_finalize function call such that BTF deallocation happens later for BPF target. For BPF, btf_finalize is only called after .BTF.ext is generated. gcc/ChangeLog: * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext enabled by default for BPF. (bpf_file_end): Call BTF deallocation. (bpf_asm_init_sections): Correct condition. * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF deallocation. (ctf_debuf_finish): Correct condition for calling ctf_debug_finalize.
2024-02-27i386: psrlq is not used for PERM<a,{0},1,2,3,4> [PR113871]Uros Bizjak1-2/+2
Also handle V2BF mode. PR target/113871 gcc/ChangeLog: * config/i386/mmx.md (V248FI): Add V2BF mode. (V24FI_32): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr113871-5a.c: New test. * gcc.target/i386/pr113871-5b.c: New test.
2024-02-27arm: warn about deprecation of iwmmx in mmintrin.hRichard Earnshaw1-0/+3
GCC 13's changes file documents that iwmmx is deprecated. Raise the bar by warning when the mmintrin.h header is included by users, but provide a way to suppress the warning. gcc: * config/arm/mmintrin.h: Warn if this header is included without defining __ENABLE_DEPRECATED_IWMMXT.
2024-02-26AVR: Tag optimization options as "Optimization".Georg-Johann Lay1-4/+4
Some options that are pure optimizations where not tagged as such. gcc/ * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args) (mstrict-X): Tag as "Optimization".
2024-02-26AVR: Dead code removal.Georg-Johann Lay1-7/+2
gcc/ * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2024-02-26x86: Check interrupt instead of noreturn attributeH.J. Lu1-3/+5
ix86_set_func_type checks noreturn attribute to avoid incompatible attribute error in LTO1 on interrupt functions. Since TREE_THIS_VOLATILE is set also for _Noreturn without noreturn attribute, check interrupt attribute for interrupt functions instead. gcc/ PR target/114097 * config/i386/i386-options.cc (ix86_set_func_type): Check interrupt instead of noreturn attribute. gcc/testsuite/ PR target/114097 * gcc.target/i386/pr114097-1.c: New test.
2024-02-26i386: Enable _BitInt support on ia32Jakub Jelinek1-3/+1
Given the https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113837#c9 comment, the following patch just attempts to implement what I think is best for ia32. Compared to https://gitlab.com/x86-psABIs/i386-ABI/-/issues/5 , like that patch for _BitInt(64) or smaller it uses the smallest containing {,un}signed {char,short,int,long long} for passing/returning and layout of variables including in structures for alignment/size, with any extra bits unspecified. Unlike the above proposal, for larger _BitInt (i.e. _BitInt(65)+), it uses passing/returning/layout/alignment of structure containing minimum needed number of 32-bit limbs, again with the extra bits unspecified. This is because most operations (except copy or bitwise ops) on _BitInts aren't really vectorizable and will be under the hood implemented in loops over 32-bit limbs anyway (using 64-bit limbs under the hood would mean often using library implementation for the basic operations) and because ia32 doesn't align even long long/double in structures to 64-bit I think it is better to just use 32-bit alignment for that. And I don't see a reason to waste 32-bit bits say for _BitInt(224) or _BitInt(288) on ia32. So, effectively it is like the x86-64 _BitInt ABI with everything divided by 2, the only exception is that in x86-64 psABI _BitInt(128) is said to be already a structure of 2 limbs, which happens to be passed mostly the same as __int128 (except for alignment). 2024-02-26 Jakub Jelinek <jakub@redhat.com> * config/i386/i386.cc (ix86_bitint_type_info): Add support for !TARGET_64BIT.
2024-02-26i386: Fix up x86_function_profiler -masm=intel support [PR114094]Jakub Jelinek1-1/+1
In my r14-8214 changes I apparently forgot one \n at the end of an instruction. The corresponding AT&T line looks like: "1:\tcall\t*%s@GOTPCREL(%%rip)\n" but the Intel variant was "1:\tcall\t[QWORD PTR %s@GOTPCREL[rip]]" Fixed thusly. 2024-02-26 Jakub Jelinek <jakub@redhat.com> PR target/114094 * config/i386/i386.cc (x86_function_profiler): Add missing new-line to printed instruction. * gcc.target/i386/pr114094.c: New test.
2024-02-25x86: Properly implement AMX-TILE load/store intrinsicsH.J. Lu4-2/+49
ldtilecfg and sttilecfg take a 512-byte memory block. With _tile_loadconfig implemented as extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _tile_loadconfig (const void *__config) { __asm__ volatile ("ldtilecfg\t%X0" :: "m" (*((const void **)__config))); } GCC sees: (parallel [ (asm_operands/v ("ldtilecfg %X0") ("") 0 [(mem/f/c:DI (plus:DI (reg/f:DI 77 virtual-stack-vars) (const_int -64 [0xffffffffffffffc0])) [1 MEM[(const void * *)&tile_data]+0 S8 A128])] [(asm_input:DI ("m"))] (clobber (reg:CC 17 flags))]) and the memory operand size is 1 byte. As the result, the rest of 511 bytes is ignored by GCC. Implement ldtilecfg and sttilecfg intrinsics with a pointer to XImode to honor the 512-byte memory block. gcc/ChangeLog: PR target/114098 * config/i386/amxtileintrin.h (_tile_loadconfig): Use __builtin_ia32_ldtilecfg. (_tile_storeconfig): Use __builtin_ia32_sttilecfg. * config/i386/i386-builtin.def (BDESC): Add __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg. * config/i386/i386-expand.cc (ix86_expand_builtin): Handle IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG. * config/i386/i386.md (ldtilecfg): New pattern. (sttilecfg): Likewise. gcc/testsuite/ChangeLog: PR target/114098 * gcc.target/i386/amxtile-4.c: New test.
2024-02-24Use HOST_WIDE_INT_{C,UC,0,0U,1,1U} macros some moreJakub Jelinek3-5/+5
I've searched for some uses of (HOST_WIDE_INT) constant or (unsigned HOST_WIDE_INT) constant and turned them into uses of the appropriate macros. THere are quite a few cases in non-i386 backends but I've left that out for now. The only behavior change is in build_replicated_int_cst where the left shift was done in HOST_WIDE_INT type but assigned to unsigned HOST_WIDE_INT, which I've changed into unsigned HOST_WIDE_INT shift. 2024-02-24 Jakub Jelinek <jakub@redhat.com> gcc/ * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro. * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro. * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros. * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro. (mk_attr_alt): Use HOST_WIDE_INT_0 macro. * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1 macros. * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro. * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro. * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and HOST_WIDE_INT_UC macros. * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro. * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro. * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro. * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U macros. * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro. * config/i386/constraints.md (define_constraint "L"): Use HOST_WIDE_INT_C macro. * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C macro. (movl + movb peephole2): Likewise. * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise. (const_32bit_mask): Likewise. gcc/objc/ * objc-encoding.cc (encode_array): Use HOST_WIDE_INT_0 macros.
2024-02-23RISC-V: Fix vec_init for simple sequences [PR114028].Robin Dapp1-1/+24
For a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" both halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast in such a case. gcc/ChangeLog: PR target/114028 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): Return false if inner mode is already Pmode. (rvv_builder::is_all_same_sequence): New function. (expand_vec_init): Emit broadcast if sequence is all same. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114028.c: New test.
2024-02-23aarch64: Spread out FPR usage between RA regions [PR113613]Richard Sandiford1-9/+46
early-ra already had code to do regrename-style "broadening" of the allocation, to promote scheduling freedom. However, the pass divides the function into allocation regions and this broadening only worked within a single region. This meant that if a basic block contained one subblock of FPR use, followed by a point at which no FPRs were live, followed by another subblock of FPR use, the two subblocks would tend to reuse the same registers. This in turn meant that it wasn't possible to form LDP/STP pairs between them. The failure to form LDPs and STPs in the testcase was a regression from GCC 13. The patch adds a simple heuristic to prefer less recently used registers in the event of a tie. gcc/ PR target/113613 * config/aarch64/aarch64-early-ra.cc (early_ra::m_current_region): New member variable. (early_ra::m_fpr_recency): Likewise. (early_ra::start_new_region): Bump m_current_region. (early_ra::allocate_colors): Prefer less recently used registers in the event of a tie. Add a comment to explain why we prefer(ed) higher-numbered registers. (early_ra::find_oldest_color): Prefer less recently used registers here too. (early_ra::finalize_allocation): Update recency information for allocated registers. (early_ra::process_blocks): Initialize m_current_region and m_fpr_recency. gcc/testsuite/ PR target/113613 * gcc.target/aarch64/pr113613.c: New test.
2024-02-23aarch64: Tighten early-ra chain test for wide registers [PR113295]Richard Sandiford1-23/+25
Most code in early-ra used is_chain_candidate to check whether we should chain two allocnos. This included both tests that matter for correctness and tests for certain heuristics. Once that test passes for one pair of allocnos, we test whether it's safe to chain the containing groups (which might contain multiple allocnos for x2, x3 and x4 modes). This test used an inline test for correctness only, deliberately skipping the heuristics. However, this instance of the test was missing some handling of equivalent allocnos. This patch fixes things by making is_chain_candidate take a strictness parameter: correctness only, or correctness + heuristics. It then makes the group-chaining test use the correctness version rather than trying to replicate it inline. gcc/ PR target/113295 * config/aarch64/aarch64-early-ra.cc (early_ra::test_strictness): New enum. (early_ra::is_chain_candidate): Add a strictness parameter to control whether only correctness matters, or whether both correctness and heuristics should be used. Handle multiple levels of equivalence. (early_ra::find_related_start): Update call accordingly. (early_ra::strided_polarity_pref): Likewise. (early_ra::form_chains): Likewise. (early_ra::try_to_chain_allocnos): Use is_chain_candidate in correctness mode rather than trying to inline the test. gcc/testsuite/ PR target/113295 * gcc.target/aarch64/pr113295-2.c: New test.
2024-02-23aarch64: Add missing early-ra bookkeeping [PR113295]Richard Sandiford1-0/+27
416.gamess showed up two wrong-code bugs in early-ra. This patch fixes the first of them. It was difficult to reduce the source code to something that would meaningfully show the situation, so the testcase uses a direct RTL sequence instead. In the sequence: (a) register <2> is set more than once (b) register <2> is copied to a temporary (<4>) (c) register <2> is the destination of an FCSEL between <4> and another value (<5>) (d) <4> and <2> are equivalent for <4>'s live range (e) <5>'s and <2>'s live ranges do not intersect, and there is a pseudo-copy between <5> and <2> On its own, (d) implies that <4> can be treated as equivalent to <2>. And on its own, (e) implies that <5> can share <2>'s register. But <4>'s and <5>'s live ranges conflict, meaning that they cannot both share the register together. A bit of missing bookkeeping meant that the mechanism for detecting this didn't fire. We therefore ended up with an FCSEL in which both inputs were the same register. gcc/ PR target/113295 * config/aarch64/aarch64-early-ra.cc (early_ra::find_related_start): Account for definitions by shared registers when testing for a single register definition. (early_ra::accumulate_defs): New function. (early_ra::record_copy): If A shares B's register, fold A's definition information into B's. Fold A's use information into B's. gcc/testsuite/ PR target/113295 * gcc.dg/rtl/aarch64/pr113295-1.c: New test.
2024-02-23x86-64: Check R_X86_64_CODE_6_GOTTPOFF supportH.J. Lu1-1/+5
If assembler and linker supports add %reg1, name@gottpoff(%rip), %reg2 with R_X86_64_CODE_6_GOTTPOFF, we can generate it instead of mov name@gottpoff(%rip), %reg2 add %reg1, %reg2 gcc/ * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1 if R_X86_64_CODE_6_GOTTPOFF is supported. * config.in: Regenerated. * configure: Likewise. * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported. gcc/testsuite/ * gcc.target/i386/apx-ndd-tls-1b.c: New test. * lib/target-supports.exp (check_effective_target_code_6_gottpoff_reloc): New.
2024-02-23arm: fix ICE with vectorized reciprocal division [PR108120]Richard Earnshaw1-2/+2
The expand pattern for reciprocal division was enabled for all math optimization modes, but the patterns it was generating were not enabled unless -funsafe-math-optimizations were enabled, this leads to an ICE when the pattern we generate cannot be recognized. Fixed by only enabling vector division when doing unsafe math. gcc: PR target/108120 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3. Gate with ARM_HAVE_NEON_<MODE>_ARITH. gcc/testsuite: PR target/108120 * gcc.target/arm/neon-recip-div-1.c: New file.
2024-02-23RISC-V: Point our Python scripts at python3Palmer Dabbelt2-2/+2
This builds for me, and I frequently have python-is-python3 type packages installed so I think I've been implicitly testing it for a while. Looks like Kito's tested similar configurations, and the bugzilla indicates we should be moving over. gcc/ChangeLog: PR other/109668 * config/riscv/arch-canonicalize: Move to python3 * config/riscv/multilib-generator: Likewise
2024-02-22invoke.texi: Fix some skipping UrlSuffix problem for MIPSYunQiang Su1-2/+10
The problem is that, there are these lines in mips.opt.urls: ; skipping UrlSuffix for 'mabi=' due to finding no URLs ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs These lines is not fixed by this patch due to that we don't document these options: ; skipping UrlSuffix for 'mlra' due to finding no URLs ; skipping UrlSuffix for 'mdebug' due to finding no URLs ; skipping UrlSuffix for 'meb' due to finding no URLs ; skipping UrlSuffix for 'mel' due to finding no URLs gcc * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix problem of mabi=, mno-flush-func, mexplicit-relocs; add missing leading - of mbranch-cost option. * config/mips/mips.opt.urls: Regenerate.
2024-02-21rs6000: Neuter option -mpower{8,9}-vector [PR109987]Kewen Lin6-81/+22
As PR109987 and its duplicated bugs show, -mno-power8-vector (and -mno-power9-vector) cause some problems and as Segher pointed out in [1] they are workaround options, so this patch is to remove -m{no,}-power{8,9}-options. Like what we did for option -mdirect-move before, this patch still keep the corresponding internal flags and they are automatically set based on -mcpu. The test suite update takes some efforts, it consists of some aspects: - effective target powerpc_p{8,9}vector_ok are removed and replaced with powerpc_vsx_ok. - Some cases having -mpower{8,9}-vector are updated with -mvsx, some of them already have -mdejagnu-cpu. For those that don't have -mdejagnu-cpu, if -mdejagnu-cpu is needed for the test point, then it's appended; otherwise, add additional-options -mdejagnu-cpu=power{8,9} if has_arch_pwr{8,9} isn't satisfied. - Some test cases are updated with explicit -mvsx. - Some test cases with those two option mixed are adjusted to keep the test points, like -mpower8-vector -mno-power9-vector are updated with -mdejagnu-cpu=power8 -mvsx etc. - Some test cases with -mno-power{8,9}-vector are updated by replacing -mno-power{8,9}-vector with -mno-vsx, or just removing it. - For some cases, we don't always specify -mdejagnu-cpu to avoid to restrict the testing coverage, it would check has_arch_pwr{8,9} and appended that as need. - For vect test cases run, it doesn't specify -mcpu=power9 for power10 and up. Bootstrapped and regtested on: - powerpc64-linux-gnu P7/P8/P9 {-m32,-m64} - powerpc64le-linux-gnu P8/P9/P10 Although it's stage4 now, as the discussion in PR113115 we are still eager to neuter these two options, so is it ok for trunk? [1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html PR target/109987 gcc/ChangeLog: * config/rs6000/constraints.md (we): Update internal doc without referring to option -mpower9-vector. * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector special handlings. * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS, OTHER_P8_VECTOR_MASKS): Merge to ... (OTHER_VSX_VECTOR_MASKS): ... here. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove some error message handlings and explicit option mask adjustments on explicit option power{8,9}-vector conflicting with other options. (rs6000_print_isa_options): Update comments. (rs6000_disable_incompatible_switches): Remove power{8,9}-vector related array items and handlings. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector special handlings. * config/rs6000/rs6000.opt: Make option power{8,9}-vector as WarnRemoved. * doc/extend.texi: Remove documentation referring to option -mpower8-vector. * doc/invoke.texi: Remove documentation for option -mpower{8,9}-vector and adjust some documentation referring to them. * doc/md.texi: Update documentation for constraint we. * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok. libgcc/ChangeLog: * config/rs6000/t-float128-hw: Replace options -mpower{8,9}-vector with -mcpu=power9. * configure.ac: Update use of option -mpower9-vector with -mcpu=power9. * configure: Regenerate. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_powerpc_p8vector_ok): Remove. (check_effective_target_powerpc_p9vector_ok): Remove. (check_p8vector_hw_available): Replace -mpower8-vector with -mcpu=power8. (check_p9vector_hw_available): Replace -mpower9-vector with -mcpu=power9. (check_ppc_float128_hw_available): Likewise. (check_vect_support_and_set_flags): Replace -mpower8-vector with -mcpu=power8, replace -mpower9-vector with -mcpu=power9 or nothing if check_power10_hw_available and place -mcpu=970 first if needed to avoid possible overriding. * g++.target/powerpc/altivec-19.C: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-5.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise. * gcc.target/powerpc/builtins-3-p9.c: Likewise. * gcc.target/powerpc/byte-in-either-range-0.c: Likewise. * gcc.target/powerpc/byte-in-either-range-1.c: Likewise. * gcc.target/powerpc/byte-in-range-0.c: Likewise. * gcc.target/powerpc/byte-in-range-1.c: Likewise. * gcc.target/powerpc/byte-in-set-0.c: Likewise. * gcc.target/powerpc/byte-in-set-1.c: Likewise. * gcc.target/powerpc/byte-in-set-2.c: Likewise. * gcc.target/powerpc/clone1.c: Likewise. * gcc.target/powerpc/ctz-3.c: Likewise. * gcc.target/powerpc/ctz-4.c: Likewise. * gcc.target/powerpc/darn-0.c: Likewise. * gcc.target/powerpc/darn-1.c: Likewise. * gcc.target/powerpc/darn-2.c: Likewise. * gcc.target/powerpc/dform-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-0.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-1.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-10.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-11.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-12.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-13.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-14.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-15.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-17.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-18.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-19.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-2.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-20.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-21.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-22.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-23.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-24.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-25.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-26.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-27.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-28.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-29.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-30.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-31.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-32.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-33.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-34.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-35.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-36.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-37.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-38.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-39.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-4.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-40.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-41.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-42.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-43.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-44.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-45.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-46.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-47.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-48.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-49.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-5.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-50.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-52.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-53.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-54.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-55.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-57.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-58.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-59.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-6.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-60.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-61.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-62.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-63.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-64.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-65.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-66.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-67.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-68.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-69.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-7.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-70.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-72.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-73.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-74.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-75.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-77.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-78.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-79.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-8.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-9.c: Likewise. * gcc.target/powerpc/direct-move-vector.c: Likewise. * gcc.target/powerpc/float128-type-2.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p9.c: Likewise. * gcc.target/powerpc/p9-dimode1.c: Likewise. * gcc.target/powerpc/p9-dimode2.c: Likewise. * gcc.target/powerpc/p9-extract-1.c: Likewise. * gcc.target/powerpc/p9-extract-2.c: Likewise. * gcc.target/powerpc/p9-extract-3.c: Likewise. * gcc.target/powerpc/p9-extract-4.c: Likewise. * gcc.target/powerpc/p9-fpcvt-1.c: Likewise. * gcc.target/powerpc/p9-fpcvt-2.c: Likewise. * gcc.target/powerpc/p9-fpcvt-3.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-1.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-2.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. * gcc.target/powerpc/p9-minmax-1.c: Likewise. * gcc.target/powerpc/p9-minmax-2.c: Likewise. * gcc.target/powerpc/p9-minmax-3.c: Likewise. * gcc.target/powerpc/p9-novsx.c: Likewise. * gcc.target/powerpc/p9-permute.c: Likewise. * gcc.target/powerpc/p9-sign_extend-runnable.c: Likewise. * gcc.target/powerpc/p9-splat-1.c: Likewise. * gcc.target/powerpc/p9-splat-2.c: Likewise. * gcc.target/powerpc/p9-splat-3.c: Likewise. * gcc.target/powerpc/p9-splat-4.c: Likewise. * gcc.target/powerpc/p9-splat-5.c: Likewise. * gcc.target/powerpc/p9-vbpermd.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-8.c: Likewise. * gcc.target/powerpc/p9-vneg.c: Likewise. * gcc.target/powerpc/p9-vparity.c: Likewise. * gcc.target/powerpc/p9-vpermr.c: Likewise. * gcc.target/powerpc/p9-xxbr-1.c: Likewise. * gcc.target/powerpc/p9-xxbr-2.c: Likewise. * gcc.target/powerpc/p9-xxbr-3.c: Likewise. * gcc.target/powerpc/ppc-fortran/pr80108-1.f90: Likewise. * gcc.target/powerpc/ppc-round3.c: Likewise. * gcc.target/powerpc/pr103124.c: Likewise. * gcc.target/powerpc/pr104015-1.c: Likewise. * gcc.target/powerpc/pr106769-p9.c: Likewise. * gcc.target/powerpc/pr107412.c: Likewise. * gcc.target/powerpc/pr110429.c: Likewise. * gcc.target/powerpc/pr66144-1.c: Likewise. * gcc.target/powerpc/pr71186.c: Likewise. * gcc.target/powerpc/pr71309.c: Likewise. * gcc.target/powerpc/pr71670.c: Likewise. * gcc.target/powerpc/pr71698.c: Likewise. * gcc.target/powerpc/pr71720.c: Likewise. * gcc.target/powerpc/pr72853.c: Likewise. * gcc.target/powerpc/pr78056-1.c: Likewise. * gcc.target/powerpc/pr78658.c: Likewise. * gcc.target/powerpc/pr78953.c: Likewise. * gcc.target/powerpc/pr79004.c: Likewise. * gcc.target/powerpc/pr79038-1.c: Likewise. * gcc.target/powerpc/pr79179.c: Likewise. * gcc.target/powerpc/pr79251.p9.c: Likewise. * gcc.target/powerpc/pr79799-1.c: Likewise. * gcc.target/powerpc/pr79799-2.c: Likewise. * gcc.target/powerpc/pr79799-3.c: Likewise. * gcc.target/powerpc/pr79799-5.c: Likewise. * gcc.target/powerpc/pr80695-p9.c: Likewise. * gcc.target/powerpc/pr81348.c: Likewise. * gcc.target/powerpc/pr81622.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. * gcc.target/powerpc/pr90763.c: Likewise. * gcc.target/powerpc/pr96933-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-2.c: Likewise. * gcc.target/powerpc/signbit-2.c: Likewise. * gcc.target/powerpc/vadsdu-0.c: Likewise. * gcc.target/powerpc/vadsdu-1.c: Likewise. * gcc.target/powerpc/vadsdu-2.c: Likewise. * gcc.target/powerpc/vadsdu-3.c: Likewise. * gcc.target/powerpc/vadsdu-4.c: Likewise. * gcc.target/powerpc/vadsdu-5.c: Likewise. * gcc.target/powerpc/vadsdub-1.c: Likewise. * gcc.target/powerpc/vadsdub-2.c: Likewise. * gcc.target/powerpc/vadsduh-1.c: Likewise. * gcc.target/powerpc/vadsduh-2.c: Likewise. * gcc.target/powerpc/vadsduw-1.c: Likewise. * gcc.target/powerpc/vadsduw-2.c: Likewise. * gcc.target/powerpc/vec-extract-4.c: Likewise. * gcc.target/powerpc/vec-init-3.c: Likewise. * gcc.target/powerpc/vec-minmax-1.c: Likewise. * gcc.target/powerpc/vec-minmax-2.c: Likewise. * gcc.target/powerpc/vec-set-char.c: Likewise. * gcc.target/powerpc/vec-set-int.c: Likewise. * gcc.target/powerpc/vec-set-short.c: Likewise. * gcc.target/powerpc/vec_reve_2.c: Likewise. * gcc.target/powerpc/vector_float.c: Likewise. * gcc.target/powerpc/vslv-0.c: Likewise. * gcc.target/powerpc/vslv-1.c: Likewise. * gcc.target/powerpc/vsrv-0.c: Likewise. * gcc.target/powerpc/vsrv-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-10.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-11.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-12.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-13.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-7.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-0.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-11.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-12.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-13.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-9.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-9.c: Likewise. * gcc.target/powerpc/vsx-builtin-msum.c: Likewise. * gcc.target/powerpc/vsx-himode.c: Likewise. * gcc.target/powerpc/vsx-himode2.c: Likewise. * gcc.target/powerpc/vsx-himode3.c: Likewise. * gcc.target/powerpc/vsx-qimode.c: Likewise. * gcc.target/powerpc/vsx-qimode2.c: Likewise. * gcc.target/powerpc/vsx-qimode3.c: Likewise. * g++.target/powerpc/pr65240-1.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.target/powerpc/pr65240-2.C: Likewise. * g++.target/powerpc/pr65240-3.C: Likewise. * g++.target/powerpc/pr65242.C: Likewise. * g++.target/powerpc/pr67211.C: Likewise. * g++.target/powerpc/pr71294.C: Likewise. * g++.target/powerpc/pr84279.C: Likewise. * g++.target/powerpc/pr93974.C: Likewise. * gcc.target/powerpc/atomic-p8.c: Likewise. * gcc.target/powerpc/atomic_load_store-p8.c: Likewise. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/bool2-p8.c: Likewise. * gcc.target/powerpc/bool3-p8.c: Likewise. * gcc.target/powerpc/builtins-1.c: Likewise. * gcc.target/powerpc/builtins-3-p8.c: Likewise. * gcc.target/powerpc/builtins-5.c: Likewise. * gcc.target/powerpc/builtins-9.c: Likewise. * gcc.target/powerpc/crypto-builtin-1.c: Likewise. * gcc.target/powerpc/crypto-builtin-2.c: Likewise. * gcc.target/powerpc/direct-move-double1.c: Likewise. * gcc.target/powerpc/direct-move-float1.c: Likewise. * gcc.target/powerpc/direct-move-long1.c: Likewise. * gcc.target/powerpc/direct-move-vint1.c: Likewise. * gcc.target/powerpc/float128-type-1.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-double.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-char.c: Likewise. * gcc.target/powerpc/fold-vec-neg-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-short.c: Likewise. * gcc.target/powerpc/fold-vec-select-double.c: Likewise. * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c: Likewise. * gcc.target/powerpc/fusion.c: Likewise. * gcc.target/powerpc/fusion2.c: Likewise. * gcc.target/powerpc/mul-vectorize-1.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst-v2.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst.c: Likewise. * gcc.target/powerpc/p8vector-builtin-1.c: Likewise. * gcc.target/powerpc/p8vector-builtin-2.c: Likewise. * gcc.target/powerpc/p8vector-builtin-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-4.c: Likewise. * gcc.target/powerpc/p8vector-builtin-5.c: Likewise. * gcc.target/powerpc/p8vector-builtin-6.c: Likewise. * gcc.target/powerpc/p8vector-builtin-7.c: Likewise. * gcc.target/powerpc/p8vector-fp.c: Likewise. * gcc.target/powerpc/p8vector-int128-1.c: Likewise. * gcc.target/powerpc/p8vector-ldst.c: Likewise. * gcc.target/powerpc/p8vector-vbpermq.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-1.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. * gcc.target/powerpc/ppc-round2.c: Likewise. * gcc.target/powerpc/pr100866-1.c: Likewise. * gcc.target/powerpc/pr100866-2.c: Likewise. * gcc.target/powerpc/pr104239-1.c: Likewise. * gcc.target/powerpc/pr104239-2.c: Likewise. * gcc.target/powerpc/pr104239-3.c: Likewise. * gcc.target/powerpc/pr106769-p8.c: Likewise. * gcc.target/powerpc/pr108396.c: Likewise. * gcc.target/powerpc/pr111449-1.c: Likewise. * gcc.target/powerpc/pr57744.c: Likewise. * gcc.target/powerpc/pr58673-1.c: Likewise. * gcc.target/powerpc/pr58673-2.c: Likewise. * gcc.target/powerpc/pr60137.c: Likewise. * gcc.target/powerpc/pr60203.c: Likewise. * gcc.target/powerpc/pr66144-2.c: Likewise. * gcc.target/powerpc/pr66144-3.c: Likewise. * gcc.target/powerpc/pr68163.c: Likewise. * gcc.target/powerpc/pr69548.c: Likewise. * gcc.target/powerpc/pr70669.c: Likewise. * gcc.target/powerpc/pr71977-1.c: Likewise. * gcc.target/powerpc/pr71977-2.c: Likewise. * gcc.target/powerpc/pr72717.c: Likewise. * gcc.target/powerpc/pr78056-3.c: Likewise. * gcc.target/powerpc/pr78056-4.c: Likewise. * gcc.target/powerpc/pr78102.c: Likewise. * gcc.target/powerpc/pr78543.c: Likewise. * gcc.target/powerpc/pr78604.c: Likewise. * gcc.target/powerpc/pr79251.p8.c: Likewise. * gcc.target/powerpc/pr79354.c: Likewise. * gcc.target/powerpc/pr79544.c: Likewise. * gcc.target/powerpc/pr79907.c: Likewise. * gcc.target/powerpc/pr79951.c: Likewise. * gcc.target/powerpc/pr80315-1.c: Likewise. * gcc.target/powerpc/pr80315-2.c: Likewise. * gcc.target/powerpc/pr80315-3.c: Likewise. * gcc.target/powerpc/pr80315-4.c: Likewise. * gcc.target/powerpc/pr80510-2.c: Likewise. * gcc.target/powerpc/pr80695-p8.c: Likewise. * gcc.target/powerpc/pr80718.c: Likewise. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr88558-p8.c: Likewise. * gcc.target/powerpc/pr88845.c: Likewise. * gcc.target/powerpc/pr91903.c: Likewise. * gcc.target/powerpc/pr92923-2.c: Likewise. * gcc.target/powerpc/pr96933-2.c: Likewise. * gcc.target/powerpc/pr97019.c: Likewise. * gcc.target/powerpc/pragma_power8.c: Likewise. * gcc.target/powerpc/signbit-1.c: Likewise. * gcc.target/powerpc/swaps-p8-1.c: Likewise. * gcc.target/powerpc/swaps-p8-12.c: Likewise. * gcc.target/powerpc/swaps-p8-14.c: Likewise. * gcc.target/powerpc/swaps-p8-15.c: Likewise. * gcc.target/powerpc/swaps-p8-16.c: Likewise. * gcc.target/powerpc/swaps-p8-17.c: Likewise. * gcc.target/powerpc/swaps-p8-18.c: Likewise. * gcc.target/powerpc/swaps-p8-19.c: Likewise. * gcc.target/powerpc/swaps-p8-2.c: Likewise. * gcc.target/powerpc/swaps-p8-22.c: Likewise. * gcc.target/powerpc/swaps-p8-23.c: Likewise. * gcc.target/powerpc/swaps-p8-24.c: Likewise. * gcc.target/powerpc/swaps-p8-25.c: Likewise. * gcc.target/powerpc/swaps-p8-26.c: Likewise. * gcc.target/powerpc/swaps-p8-27.c: Likewise. * gcc.target/powerpc/swaps-p8-3.c: Likewise. * gcc.target/powerpc/swaps-p8-30.c: Likewise. * gcc.target/powerpc/swaps-p8-33.c: Likewise. * gcc.target/powerpc/swaps-p8-36.c: Likewise. * gcc.target/powerpc/swaps-p8-39.c: Likewise. * gcc.target/powerpc/swaps-p8-4.c: Likewise. * gcc.target/powerpc/swaps-p8-42.c: Likewise. * gcc.target/powerpc/swaps-p8-45.c: Likewise. * gcc.target/powerpc/swaps-p8-46.c: Likewise. * gcc.target/powerpc/swaps-p8-5.c: Likewise. * gcc.target/powerpc/unpack-vectorize-3.c: Likewise. * gcc.target/powerpc/upper-regs-sf.c: Likewise. * gcc.target/powerpc/vec-cmp.c: Likewise. * gcc.target/powerpc/vec-extract-1.c: Likewise. * gcc.target/powerpc/vec-extract-3.c: Likewise. * gcc.target/powerpc/vec-extract-5.c: Likewise. * gcc.target/powerpc/vec-extract-6.c: Likewise. * gcc.target/powerpc/vec-extract-7.c: Likewise. * gcc.target/powerpc/vec-extract-8.c: Likewise. * gcc.target/powerpc/vec-extract-9.c: Likewise. * gcc.target/powerpc/vec-init-10.c: Likewise. * gcc.target/powerpc/vec-init-6.c: Likewise. * gcc.target/powerpc/vec-init-7.c: Likewise. * gcc.target/powerpc/vsx-extract-3.c: Likewise. * gcc.target/powerpc/vsx-extract-4.c: Likewise. * gcc.target/powerpc/vsx-extract-5.c: Likewise. * gcc.target/powerpc/vsx-simode.c: Likewise. * gcc.target/powerpc/vsx-simode2.c: Likewise. * gcc.target/powerpc/vsx-simode3.c: Likewise. * gcc.target/powerpc/builtins-4-int128-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/builtins-mergew-mergow.c: Likewise. * gcc.target/powerpc/direct-move-float3.c: Likewise. * gcc.target/powerpc/divkc3-2.c: Likewise. * gcc.target/powerpc/divkc3-3.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-add-4.c: Likewise. * gcc.target/powerpc/fold-vec-add-7.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.h: Likewise. * gcc.target/powerpc/fold-vec-cmp-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.h: Likewise. * gcc.target/powerpc/fold-vec-cntlz-char.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-int.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-short.c: Likewise. * gcc.target/powerpc/fold-vec-ld-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-float.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-short.c: Likewise. * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-short.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int.c: Likewise. * gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.h: Likewise. * gcc.target/powerpc/fold-vec-pack-double.c: Likewise. * gcc.target/powerpc/fold-vec-pack-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-st-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-sub-int128.c: Likewise. * gcc.target/powerpc/fold-vec-sub-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-float.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-int.c: Likewise. * gcc.target/powerpc/mmx-packs.c: Likewise. * gcc.target/powerpc/mmx-packssdw-1.c: Likewise. * gcc.target/powerpc/mmx-packsswb-1.c: Likewise. * gcc.target/powerpc/mmx-packuswb-1.c: Likewise. * gcc.target/powerpc/mmx-paddb-1.c: Likewise. * gcc.target/powerpc/mmx-paddd-1.c: Likewise. * gcc.target/powerpc/mmx-paddsb-1.c: Likewise. * gcc.target/powerpc/mmx-paddsw-1.c: Likewise. * gcc.target/powerpc/mmx-paddusb-1.c: Likewise. * gcc.target/powerpc/mmx-paddusw-1.c: Likewise. * gcc.target/powerpc/mmx-paddw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/mmx-pmaddwd-1.c: Likewise. * gcc.target/powerpc/mmx-pmulhw-1.c: Likewise. * gcc.target/powerpc/mmx-pmullw-1.c: Likewise. * gcc.target/powerpc/mmx-pslld-1.c: Likewise. * gcc.target/powerpc/mmx-psllw-1.c: Likewise. * gcc.target/powerpc/mmx-psrad-1.c: Likewise. * gcc.target/powerpc/mmx-psraw-1.c: Likewise. * gcc.target/powerpc/mmx-psrld-1.c: Likewise. * gcc.target/powerpc/mmx-psrlw-1.c: Likewise. * gcc.target/powerpc/mmx-psubb-2.c: Likewise. * gcc.target/powerpc/mmx-psubd-2.c: Likewise. * gcc.target/powerpc/mmx-psubsb-1.c: Likewise. * gcc.target/powerpc/mmx-psubsw-1.c: Likewise. * gcc.target/powerpc/mmx-psubusb-1.c: Likewise. * gcc.target/powerpc/mmx-psubusw-1.c: Likewise. * gcc.target/powerpc/mmx-psubw-2.c: Likewise. * gcc.target/powerpc/mmx-punpckhbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhdq-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhwd-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckldq-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklwd-1.c: Likewise. * gcc.target/powerpc/mulkc3-2.c: Likewise. * gcc.target/powerpc/mulkc3-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-8.c: Likewise. * gcc.target/powerpc/pr37191.c: Likewise. * gcc.target/powerpc/pr83862.c: Likewise. * gcc.target/powerpc/pr84154-1.c: Likewise. * gcc.target/powerpc/pr84220-sld2.c: Likewise. * gcc.target/powerpc/pr85456.c: Likewise. * gcc.target/powerpc/pr86731-longlong.c: Likewise. * gcc.target/powerpc/sse-addps-1.c: Likewise. * gcc.target/powerpc/sse-addss-1.c: Likewise. * gcc.target/powerpc/sse-andnps-1.c: Likewise. * gcc.target/powerpc/sse-andps-1.c: Likewise. * gcc.target/powerpc/sse-cmpss-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32x2ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi16-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi8-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-2.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-2.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-2.c: Likewise. * gcc.target/powerpc/sse-divps-1.c: Likewise. * gcc.target/powerpc/sse-divss-1.c: Likewise. * gcc.target/powerpc/sse-maxps-1.c: Likewise. * gcc.target/powerpc/sse-maxps-2.c: Likewise. * gcc.target/powerpc/sse-maxss-1.c: Likewise. * gcc.target/powerpc/sse-minps-1.c: Likewise. * gcc.target/powerpc/sse-minps-2.c: Likewise. * gcc.target/powerpc/sse-minss-1.c: Likewise. * gcc.target/powerpc/sse-movaps-1.c: Likewise. * gcc.target/powerpc/sse-movaps-2.c: Likewise. * gcc.target/powerpc/sse-movhlps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-2.c: Likewise. * gcc.target/powerpc/sse-movlhps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-2.c: Likewise. * gcc.target/powerpc/sse-movmskb-1.c: Likewise. * gcc.target/powerpc/sse-movmskps-1.c: Likewise. * gcc.target/powerpc/sse-movss-1.c: Likewise. * gcc.target/powerpc/sse-movss-2.c: Likewise. * gcc.target/powerpc/sse-movss-3.c: Likewise. * gcc.target/powerpc/sse-mulps-1.c: Likewise. * gcc.target/powerpc/sse-mulss-1.c: Likewise. * gcc.target/powerpc/sse-orps-1.c: Likewise. * gcc.target/powerpc/sse-pavgw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse-pminsw-1.c: Likewise. * gcc.target/powerpc/sse-pminub-1.c: Likewise. * gcc.target/powerpc/sse-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse-psadbw-1.c: Likewise. * gcc.target/powerpc/sse-rcpps-1.c: Likewise. * gcc.target/powerpc/sse-rsqrtps-1.c: Likewise. * gcc.target/powerpc/sse-shufps-1.c: Likewise. * gcc.target/powerpc/sse-sqrtps-1.c: Likewise. * gcc.target/powerpc/sse-subps-1.c: Likewise. * gcc.target/powerpc/sse-subss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-2.c: Likewise. * gcc.target/powerpc/sse-ucomiss-3.c: Likewise. * gcc.target/powerpc/sse-ucomiss-4.c: Likewise. * gcc.target/powerpc/sse-ucomiss-5.c: Likewise. * gcc.target/powerpc/sse-ucomiss-6.c: Likewise. * gcc.target/powerpc/sse-unpckhps-1.c: Likewise. * gcc.target/powerpc/sse-unpcklps-1.c: Likewise. * gcc.target/powerpc/sse-xorps-1.c: Likewise. * gcc.target/powerpc/sse2-addpd-1.c: Likewise. * gcc.target/powerpc/sse2-addsd-1.c: Likewise. * gcc.target/powerpc/sse2-andnpd-1.c: Likewise. * gcc.target/powerpc/sse2-andpd-1.c: Likewise. * gcc.target/powerpc/sse2-cmppd-1.c: Likewise. * gcc.target/powerpc/sse2-cmpsd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-2.c: Likewise. * gcc.target/powerpc/sse2-comisd-3.c: Likewise. * gcc.target/powerpc/sse2-comisd-4.c: Likewise. * gcc.target/powerpc/sse2-comisd-5.c: Likewise. * gcc.target/powerpc/sse2-comisd-6.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2ss-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-2.c: Likewise. * gcc.target/powerpc/sse2-cvtss2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvttpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-divpd-1.c: Likewise. * gcc.target/powerpc/sse2-divsd-1.c: Likewise. * gcc.target/powerpc/sse2-maxpd-1.c: Likewise. * gcc.target/powerpc/sse2-maxsd-1.c: Likewise. * gcc.target/powerpc/sse2-minpd-1.c: Likewise. * gcc.target/powerpc/sse2-minsd-1.c: Likewise. * gcc.target/powerpc/sse2-mmx.c: Likewise. * gcc.target/powerpc/sse2-movhpd-1.c: Likewise. * gcc.target/powerpc/sse2-movhpd-2.c: Likewise. * gcc.target/powerpc/sse2-movlpd-1.c: Likewise. * gcc.target/powerpc/sse2-movlpd-2.c: Likewise. * gcc.target/powerpc/sse2-movmskpd-1.c: Likewise. * gcc.target/powerpc/sse2-movq-1.c: Likewise. * gcc.target/powerpc/sse2-movq-2.c: Likewise. * gcc.target/powerpc/sse2-movq-3.c: Likewise. * gcc.target/powerpc/sse2-movsd-1.c: Likewise. * gcc.target/powerpc/sse2-movsd-2.c: Likewise. * gcc.target/powerpc/sse2-movsd-3.c: Likewise. * gcc.target/powerpc/sse2-mulpd-1.c: Likewise. * gcc.target/powerpc/sse2-mulsd-1.c: Likewise. * gcc.target/powerpc/sse2-orpd-1.c: Likewise. * gcc.target/powerpc/sse2-packssdw-1.c: Likewise. * gcc.target/powerpc/sse2-packsswb-1.c: Likewise. * gcc.target/powerpc/sse2-packuswb-1.c: Likewise. * gcc.target/powerpc/sse2-paddb-1.c: Likewise. * gcc.target/powerpc/sse2-paddd-1.c: Likewise. * gcc.target/powerpc/sse2-paddq-1.c: Likewise. * gcc.target/powerpc/sse2-paddsb-1.c: Likewise. * gcc.target/powerpc/sse2-paddsw-1.c: Likewise. * gcc.target/powerpc/sse2-paddusb-1.c: Likewise. * gcc.target/powerpc/sse2-paddusw-1.c: Likewise. * gcc.target/powerpc/sse2-paddw-1.c: Likewise. * gcc.target/powerpc/sse2-pand-1.c: Likewise. * gcc.target/powerpc/sse2-pandn-1.c: Likewise. * gcc.target/powerpc/sse2-pavgb-1.c: Likewise. * gcc.target/powerpc/sse2-pavgw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/sse2-pextrw.c: Likewise. * gcc.target/powerpc/sse2-pinsrw.c: Likewise. * gcc.target/powerpc/sse2-pmaddwd-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse2-pminsw-1.c: Likewise. * gcc.target/powerpc/sse2-pminub-1.c: Likewise. * gcc.target/powerpc/sse2-pmovmskb-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhw-1.c: Likewise. * gcc.target/powerpc/sse2-pmullw-1.c: Likewise. * gcc.target/powerpc/sse2-pmuludq-1.c: Likewise. * gcc.target/powerpc/sse2-por-1.c: Likewise. * gcc.target/powerpc/sse2-psadbw-1.c: Likewise. * gcc.target/powerpc/sse2-pshufd-1.c: Likewise. * gcc.target/powerpc/sse2-pshufhw-1.c: Likewise. * gcc.target/powerpc/sse2-pshuflw-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-2.c: Likewise. * gcc.target/powerpc/sse2-pslldq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-2.c: Likewise. * gcc.target/powerpc/sse2-psllw-1.c: Likewise. * gcc.target/powerpc/sse2-psllw-2.c: Likewise. * gcc.target/powerpc/sse2-psrad-1.c: Likewise. * gcc.target/powerpc/sse2-psrad-2.c: Likewise. * gcc.target/powerpc/sse2-psraw-1.c: Likewise. * gcc.target/powerpc/sse2-psraw-2.c: Likewise. * gcc.target/powerpc/sse2-psrld-1.c: Likewise. * gcc.target/powerpc/sse2-psrld-2.c: Likewise. * gcc.target/powerpc/sse2-psrldq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-2.c: Likewise. * gcc.target/powerpc/sse2-psrlw-1.c: Likewise. * gcc.target/powerpc/sse2-psrlw-2.c: Likewise. * gcc.target/powerpc/sse2-psubb-1.c: Likewise. * gcc.target/powerpc/sse2-psubd-1.c: Likewise. * gcc.target/powerpc/sse2-psubq-1.c: Likewise. * gcc.target/powerpc/sse2-psubsb-1.c: Likewise. * gcc.target/powerpc/sse2-psubsw-1.c: Likewise. * gcc.target/powerpc/sse2-psubusb-1.c: Likewise. * gcc.target/powerpc/sse2-psubusw-1.c: Likewise. * gcc.target/powerpc/sse2-psubw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhwd-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckldq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklwd-1.c: Likewise. * gcc.target/powerpc/sse2-pxor-1.c: Likewise. * gcc.target/powerpc/sse2-shufpd-1.c: Likewise. * gcc.target/powerpc/sse2-sqrtpd-1.c: Likewise. * gcc.target/powerpc/sse2-subpd-1.c: Likewise. * gcc.target/powerpc/sse2-subsd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-2.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-3.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-4.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-5.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-6.c: Likewise. * gcc.target/powerpc/sse2-unpckhpd-1.c: Likewise. * gcc.target/powerpc/sse2-unpcklpd-1.c: Likewise. * gcc.target/powerpc/sse2-xorpd-1.c: Likewise. * gcc.target/powerpc/sse3-addsubpd.c: Likewise. * gcc.target/powerpc/sse3-addsubps.c: Likewise. * gcc.target/powerpc/sse3-haddpd.c: Likewise. * gcc.target/powerpc/sse3-haddps.c: Likewise. * gcc.target/powerpc/sse3-hsubpd.c: Likewise. * gcc.target/powerpc/sse3-hsubps.c: Likewise. * gcc.target/powerpc/sse3-lddqu.c: Likewise. * gcc.target/powerpc/sse3-movddup.c: Likewise. * gcc.target/powerpc/sse3-movshdup.c: Likewise. * gcc.target/powerpc/sse3-movsldup.c: Likewise. * gcc.target/powerpc/sse4_1-blendpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendps-2.c: Likewise. * gcc.target/powerpc/sse4_1-blendps.c: Likewise. * gcc.target/powerpc/sse4_1-blendvpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendvps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilpd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilsd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilss.c: Likewise. * gcc.target/powerpc/sse4_1-floorpd.c: Likewise. * gcc.target/powerpc/sse4_1-floorps.c: Likewise. * gcc.target/powerpc/sse4_1-floorsd.c: Likewise. * gcc.target/powerpc/sse4_1-floorss.c: Likewise. * gcc.target/powerpc/sse4_1-pblendvb.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw-2.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw.c: Likewise. * gcc.target/powerpc/sse4_1-pcmpeqq.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrb.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrd.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxbq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxdq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxwq.c: Likewise. * gcc.target/powerpc/sse4_1-pmuldq.c: Likewise. * gcc.target/powerpc/sse4_1-ptest-1.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-2.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-3.c: Likewise. * gcc.target/powerpc/sse4_2-pcmpgtq.c: Likewise. * gcc.target/powerpc/ssse3-pabsb.c: Likewise. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/powerpc/ssse3-pabsw.c: Likewise. * gcc.target/powerpc/ssse3-palignr.c: Likewise. * gcc.target/powerpc/ssse3-phaddd.c: Likewise. * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. * gcc.target/powerpc/ssse3-phaddw.c: Likewise. * gcc.target/powerpc/ssse3-phsubd.c: Likewise. * gcc.target/powerpc/ssse3-phsubsw.c: Likewise. * gcc.target/powerpc/ssse3-phsubw.c: Likewise. * gcc.target/powerpc/ssse3-pmaddubsw.c: Likewise. * gcc.target/powerpc/ssse3-pmulhrsw.c: Likewise. * gcc.target/powerpc/ssse3-pshufb.c: Likewise. * gcc.target/powerpc/ssse3-psignb.c: Likewise. * gcc.target/powerpc/ssse3-psignd.c: Likewise. * gcc.target/powerpc/ssse3-psignw.c: Likewise. * gcc.target/powerpc/vec-cmp-sel.c: Likewise. * gcc.target/powerpc/vec-sld-modulo.c: Likewise. * gcc.target/powerpc/vec-srad-modulo.c: Likewise. * gcc.target/powerpc/vec-srd-modulo.c: Likewise. * gcc.target/powerpc/amo1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mpower9-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power9 if !has_arch_pwr9. * gcc.target/powerpc/amo2.c: Likewise. * gcc.target/powerpc/dform-1.c: Likewise. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/float128-5.c: Likewise. * gcc.target/powerpc/float128-complex-2.c: Likewise. * gcc.target/powerpc/float128-fma1.c: Likewise. * gcc.target/powerpc/float128-hw.c: Likewise. * gcc.target/powerpc/float128-hw10.c: Likewise. * gcc.target/powerpc/float128-hw11.c: Likewise. * gcc.target/powerpc/float128-hw2.c: Likewise. * gcc.target/powerpc/float128-hw3.c: Likewise. * gcc.target/powerpc/float128-hw4.c: Likewise. * gcc.target/powerpc/float128-hw5.c: Likewise. * gcc.target/powerpc/float128-hw6.c: Likewise. * gcc.target/powerpc/float128-hw7.c: Likewise. * gcc.target/powerpc/float128-hw8.c: Likewise. * gcc.target/powerpc/float128-hw9.c: Likewise. * gcc.target/powerpc/float128-minmax.c: Likewise. * gcc.target/powerpc/float128-odd.c: Likewise. * gcc.target/powerpc/float128-sqrt1.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p9.c: Likewise. * gcc.target/powerpc/gnuattr2.c: Likewise. * gcc.target/powerpc/pr71656-1.c: Likewise. * gcc.target/powerpc/pr71656-2.c: Likewise. * gcc.target/powerpc/pr81959.c: Likewise. * gcc.target/powerpc/pr82748-1.c: Likewise. * gcc.target/powerpc/pr82748-2.c: Likewise. * gcc.target/powerpc/pr111449-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/pr98914.c: Likewise. * gcc.target/powerpc/versioned-copy-loop.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/clone2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/p9-options-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr84226.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.dg/pr69667.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mpower9-vector with -mvsx. * gcc.dg/vect/pr109011-1.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector with -mdejagnu-cpu=power8 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, and replace -mpower9-vector with -mdejagnu-cpu=power9 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-4.c: Likewise. * gcc.dg/vect/pr109011-3.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector -mno-power9-vector with -mdejagnu-cpu=power8 -mvsx. * gcc.dg/vect/pr109011-5.c: Likewise. * gcc.target/powerpc/altivec-35.c: Remove -mno-power8-vector. * gcc.target/powerpc/vsx-vector-7.c: Replace -mno-power8-vector with -mdejagnu-cpu=power7. * gcc.dg/vect/O3-pr70130.c: Replace -mcpu=power7 with options -mdejagnu-cpu=power7 -mvsx and remove option -mno-power9-vector -mno-power8-vector. * gfortran.dg/vect/pr45714-b.f: Likewise. * gcc.dg/vect/pr48765.c: Remove dg-skip-if and replace -mcpu=power7 with option -mdejagnu-cpu=power6. * gcc.target/powerpc/pr78056-2.c: Likewise. * gcc.target/powerpc/altivec-2-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, remove -mpower8-vector and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/altivec-37.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mpower8-vector with -mvsx. * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-int.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p8.c: Likewise. * gcc.target/powerpc/pr104124.c: Likewise. * gcc.target/powerpc/vec-cmpne-long.c: Likewise. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/pr80098-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr80098-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mno-power8-vector with -mno-vsx. * gcc.target/powerpc/pragma_misc9.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok.
2024-02-22RISC-V: Upgrade RVV intrinsic version to 0.12Pan Li1-1/+1
Upgrade the version of RVV intrinsic from 0.11 to 0.12. PR target/114017 gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade the version to 0.12. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the version to 0.12. * gcc.target/riscv/rvv/base/pr114017-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-02-21RISC-V: Enable assert for insn_has_dfa_reservationEdwin Lu1-2/+0
Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-02-21RISC-V: Add vector related pipelinesEdwin Lu3-126/+145
Creates new generic vector pipeline file common to all cpu tunes. Moves all vector related pipelines from generic-ooo to generic-vector-ooo. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo): Move reservation (generic_ooo_vec_load): Ditto (generic_ooo_vec_store): Ditto (generic_ooo_vec_loadstore_seg): Ditto (generic_ooo_vec_alu): Ditto (generic_ooo_vec_fcmp): Ditto (generic_ooo_vec_imul): Ditto (generic_ooo_vec_fadd): Ditto (generic_ooo_vec_fmul): Ditto (generic_ooo_crypto): Ditto (generic_ooo_perm): Ditto (generic_ooo_vec_reduction): Ditto (generic_ooo_vec_ordered_reduction): Ditto (generic_ooo_vec_idiv): Ditto (generic_ooo_vec_float_divsqrt): Ditto (generic_ooo_vec_mask): Ditto (generic_ooo_vec_vesetvl): Ditto (generic_ooo_vec_setrm): Ditto (generic_ooo_vec_readlen): Ditto * config/riscv/riscv.md: Include generic-vector-ooo * config/riscv/generic-vector-ooo.md: New file. To here Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
2024-02-21RISC-V: Add non-vector types to dfa pipelinesEdwin Lu8-69/+117
This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): Ditto * config/riscv/generic.md (generic_sfb_alu): Ditto (generic_fmul_half): Ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation (sifive_7_popcount): Ditto * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto * config/riscv/vector.md: Change rdfrm to fmove * config/riscv/zc.md: Change pushpop to load/store Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-02-21bpf: add inline memmove and memcpy expansionDavid Faust3-0/+153
BPF programs are not typically linked, which means we cannot fall back on library calls to implement __builtin_{memmove,memcpy} and should always expand them inline if possible. GCC already successfully expands these builtins inline in many cases, but failed to do so for a few for simple cases involving overlapping memmove in the kernel BPF selftests and was instead emitting a libcall. This patch implements a simple inline expansion of memcpy and memmove in the BPF backend in a verifier-friendly way, with the caveat that the size must be an integer constant, which is also required by clang. gcc/ * config/bpf/bpf-protos.h (bpf_expand_cpymem): New. * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New. * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands. gcc/testsuite/ * gcc.target/bpf/memcpy-1.c: New test. * gcc.target/bpf/memmove-1.c: New test. * gcc.target/bpf/memmove-2.c: New test.
2024-02-21ipa: Convert lattices from pure array to vector (PR 113476)Martin Jambor8-0/+16
In PR 113476 we have discovered that ipcp_param_lattices is no longer a POD and should be destructed. In a follow-up discussion it transpired that their initialization done by memsetting their backing memory to zero is also invalid because now any write there before construction can be considered dead. Plus that having them in an array is a little bit old-school and does not get the extra checking offered by vector along with automatic construction and destruction when necessary. So this patch converts the array to a vector. That however means that ipcp_param_lattices cannot be just a forward declared type but must be known to all code that deals with ipa_node_params and thus to all code that includes ipa-prop.h. Therefore I have moved ipcp_param_lattices and the type it depends on to a new header ipa-cp.h which now ipa-prop.h depends on. Because we have the (IMHO not a very wise) rule that headers don't include what they need themselves, I had to add inclusions of ipa-cp.h and sreal.h (on which it depends) to very many files, which made the patch rather ugly. gcc/lto/ChangeLog: 2024-02-16 Martin Jambor <mjambor@suse.cz> PR ipa/113476 * lto-common.cc: Include sreal.h and ipa-cp.h. * lto-partition.cc: Include ipa-cp.h, move inclusion of sreal higher. * lto.cc: Include sreal.h and ipa-cp.h. gcc/ChangeLog: 2024-02-16 Martin Jambor <mjambor@suse.cz> PR ipa/113476 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust initializers in the contructor. (ipa_node_params::~ipa_node_params): Release lattices as a vector. * ipa-cp.h: New file. * ipa-cp.cc: Include sreal.h and ipa-cp.h. (ipcp_value_source): Move to ipa-cp.h. (ipcp_value_base): Likewise. (ipcp_value): Likewise. (ipcp_lattice): Likewise. (ipcp_agg_lattice): Likewise. (ipcp_bits_lattice): Likewise. (ipcp_vr_lattice): Likewise. (ipcp_param_lattices): Likewise. (ipa_get_parm_lattices): Remove assert latticess is non-NULL. (ipa_value_from_jfunc): Adjust a check for empty lattices. (ipa_context_from_jfunc): Likewise. (ipa_agg_value_from_jfunc): Likewise. (merge_agg_lats_step): Do not memset new aggregate lattices to zero. (ipcp_propagate_stage): Allocate lattices in a vector as opposed to just in contiguous memory. (ipcp_store_vr_results): Adjust a check for empty lattices. * auto-profile.cc: Include sreal.h and ipa-cp.h. * cgraph.cc: Likewise. * cgraphclones.cc: Likewise. * cgraphunit.cc: Likewise. * config/aarch64/aarch64.cc: Likewise. * config/i386/i386-builtins.cc: Likewise. * config/i386/i386-expand.cc: Likewise. * config/i386/i386-features.cc: Likewise. * config/i386/i386-options.cc: Likewise. * config/i386/i386.cc: Likewise. * config/rs6000/rs6000.cc: Likewise. * config/s390/s390.cc: Likewise. * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the files to be included in gtype-desc.cc. * gimple-range-fold.cc: Include sreal.h and ipa-cp.h. * ipa-devirt.cc: Likewise. * ipa-fnsummary.cc: Likewise. * ipa-icf.cc: Likewise. * ipa-inline-analysis.cc: Likewise. * ipa-inline-transform.cc: Likewise. * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher. * ipa-modref.cc: Include sreal.h and ipa-cp.h. * ipa-param-manipulation.cc: Likewise. * ipa-predicate.cc: Likewise. * ipa-profile.cc: Likewise. * ipa-prop.cc: Likewise. (ipa_node_params_t::duplicate): Assert new lattices remain empty instead of setting them to NULL. * ipa-pure-const.cc: Include sreal.h and ipa-cp.h. * ipa-split.cc: Likewise. * ipa-sra.cc: Likewise. * ipa-strub.cc: Likewise. * ipa-utils.cc: Likewise. * ipa.cc: Likewise. * toplev.cc: Likewise. * tree-ssa-ccp.cc: Likewise. * tree-ssa-sccvn.cc: Likewise. * tree-vrp.cc: Likewise.
2024-02-21AArch64: remove ls64 from being mandatory on armv8.7-a..Tamar Christina1-1/+1
The Arm Architectural Reference Manual (Version J.a, section A2.9 on FEAT_LS64) shows that ls64 is an optional extensions and should not be enabled by default for Armv8.7-a. This drops it from the mandatory bits for the architecture and brings GCC inline with LLVM and the achitecture. Note that we will not be changing binutils to preserve compatibility with older released compilers. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from Armv8.7-a. gcc/testsuite/ChangeLog: * g++.target/aarch64/acle/ls64.C: Add +ls64. * g++.target/aarch64/acle/ls64_lto.C: Likewise. * gcc.target/aarch64/acle/ls64_lto.c: Likewise. * gcc.target/aarch64/acle/pr110100.c: Likewise. * gcc.target/aarch64/acle/pr110132.c: Likewise. * gcc.target/aarch64/options_set_28.c: Drop check for nols64. * gcc.target/aarch64/pragma_cpp_predefs_2.c: Correct header checks.
2024-02-21aarch64: More SME vs -mtrack-speculationRichard Sandiford1-1/+2
The sequence to commit a lazy save includes a branch based on whether TPIDR2_EL0 is zero. The code assumed that CBZ could be used for this, but that instruction is forbidden when -mtrack-speculation is being used. gcc/ * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): Use aarch64_gen_compare_zero_and_branch rather than emitting a CBZ directly. gcc/testsuite/ * gcc.target/aarch64/sme/locally_streaming_1_ts.c: New test. * gcc.target/aarch64/sme/sibcall_7_ts.c: Likewise.
2024-02-21aarch64: Remove duplicated callRichard Sandiford1-1/+0
I noticed while working on another patch that we had a duplicated call to aarch64_process_target_attr. gcc/ * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p): Remove duplicated call.
2024-02-21aarch64: Fix sibcalls involving shared-ZT0 functionsRichard Sandiford1-2/+4
In: void bar() __arm_inout("za"); void foo() __arm_inout("za", "zt0") { bar(); } foo cannot tail-call bar because foo needs to restore ZT0 after the call. I'd forgotten to update the ok_for_sibcall rules to handle this when adding SME2. Thanks to Sander de Smalen for the spot. gcc/ * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall): Check that each individual piece of state is shared in the same way, rather than using an aggregate check for PSTATE.ZA. gcc/testsuite/ * gcc.target/aarch64/sme/sibcall_9.c: New test.
2024-02-21aarch64: Ensure ZT0 is zeroed in a new-ZT0 functionRichard Sandiford1-1/+7
ACLE guarantees that a function like: __arm_new("zt0") foo() { ... } will start with ZT0 equal to zero. I'd forgotten to enforce that after commiting a lazy save. After such a save, we should zero ZA iff the function has ZA state and zero ZT0 iff the function has ZT0 state. gcc/ * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): In the code that commits a lazy save, only zero ZA if the function has ZA state. Similarly zero ZT0 if the function has ZT0 state. gcc/testsuite/ * gcc.target/aarch64/sme/zt0_state_5.c (test3): Expect ZT0 rather than ZA to be zeroed. (test5): Remove zeroing of ZA.
2024-02-21aarch64: Remove the aarch64_commit_lazy_save patternRichard Sandiford2-49/+9
The main purpose of the aarch64_commit_lazy_save pattern was to defer insertion of a half-diamond until splitting, since splitting knew how to create the associated basic blocks. However, the fix for PR113220 means that mode-switching also knows how to do that. This patch therefore removes the pattern and emits the subinstructions directly. On its own, this is actually a slight regression, since it means we keep an unnecessary zero { za }. But the cases where that happens are wrong for a different reason, and this patch is a prerequisite to fixing it. gcc/ * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove, directly inserting the associated sequence * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): ...here instead. gcc/testsuite/ * gcc.target/aarch64/sme/zt0_state_5.c (test3, test5): Expect zero { za }s.
2024-02-21aarch64: Stack-clash prologues and VG saves [PR113995]Richard Sandiford1-2/+7
This patch fixes an ICE for a combination of: - -fstack-clash-protection - a frame that has SVE save slots - a frame that has no GPR save slots - a frame that has a VG save slot The allocation code was folding the SVE save slot allocation into the initial frame allocation, so that we had one allocation of size <size of SVE registers> + 16. But the VG save code itself expected the allocations to remain separate, since it wants to store at a constant offset from SP or FP. The VG save isn't shrink-wrapped and so acts as a probe of the initial allocations. It should therefore be safe to keep separate allocations in this case. The scans in locally_streaming_1.c expect no stack clash protection, so the patch forces that and adds a separate compile-only test for when protection is enabled. gcc/ PR target/113995 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't fold the SVE allocation into the initial allocation if the initial allocation includes a VG save. gcc/testsuite/ PR target/113995 * gcc.target/aarch64/sme/locally_streaming_1.c: Require -fno-stack-clash-protection. * gcc.target/aarch64/sme/locally_streaming_1_scp.c: New test.
2024-02-21Allow mode-switching to introduce internal loops [PR113220]Richard Sandiford1-0/+2
In this PR, the SME mode-switching code needs to insert a stack-probe loop for an alloca. This patch allows the target to do that. There are two parts to it: allowing loops for insertions in blocks, and allowing them for insertions on edges. The former can be handled entirely within mode-switching itself, by recording which blocks have had new branches inserted. The latter requires an extension to commit_one_edge_insertion. I think the extension to commit_one_edge_insertion makes logical sense, since it already explicitly allows internal loops during RTL expansion. The single-block find_sub_basic_blocks is a relatively recent addition, so wouldn't have been available when the code was originally written. The patch also has a small and obvious fix to make the aarch64 emit hook cope with labels. I've added specific -fstack-clash-protection versions of all aarch64-sme.exp tests that previously failed because of this bug. I've also added -fno-stack-clash-protection to the original versions of these tests if they contain scans that assume no protection. gcc/ PR target/113220 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that contain jumps even if called after initial RTL expansion. * mode-switching.cc: Include cfgbuild.h. (optimize_mode_switching): Allow the sequence returned by the emit hook to contain internal jumps. Record which blocks contain such jumps and split the blocks at the end. * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for non-debug insns when scanning the sequence. gcc/testsuite/ PR target/113220 * gcc.target/aarch64/sme/call_sm_switch_5.c: Add -fno-stack-clash-protection. * gcc.target/aarch64/sme/call_sm_switch_5_scp.c: New test. * gcc.target/aarch64/sme/sibcall_6_scp.c: New test. * gcc.target/aarch64/sme/za_state_4.c: Add -fno-stack-clash-protection. * gcc.target/aarch64/sme/za_state_4_scp.c: New test. * gcc.target/aarch64/sme/za_state_5.c: Add -fno-stack-clash-protection. * gcc.target/aarch64/sme/za_state_5_scp.c: New test.
2024-02-21OpenMP/nvptx: support 'arch(nvptx64)' as context selectorTobias Burnus2-2/+3
The main 'arch' context selector for nvptx is, well, 'nvptx'; however, as 'nvptx64' is used as by LLVM, it makes sense to support it as well. Note that LLVM has: "The triple architecture can be one of ``nvptx`` (32-bit PTX) or ``nvptx64`` (64-bit PTX)." GCC effectively only supports the 64bit variant (at least for offloading). Thus, GCC's 'nvptx' is not quite the same as LLVM's. The device-compiler part (nvptx_omp_device_kind_arch_isa) uses TARGET_ABI64 such that nvptx64 is only defined with -m64. gcc/ChangeLog: * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch. * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise. libgomp/ChangeLog: * libgomp.texi (OpenMP Context Selectors): Add 'nvptx64' as additional 'arch' value for nvptx.
2024-02-20AVR: Use types of exact size and signedness in built-ins.Georg-Johann Lay2-32/+32
The AVR built-ins used types like "int" or "char" that don't have exact signedness or type size which depend on -mint8 and -f[no-][un-]signed-char etc. As the built-ins are modelling machine instructions of given type sizes and signedness, also use according types in their prototypes. gcc/ * config/avr/builtins.def: Use function prototypes of given size and signedness. * config/avr/avr.cc (avr_init_builtins): Adjust types required by builtins.def. * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2024-02-20bpf: Add documentation for the -mcpu optionWill Hawkins1-0/+2
Add documentation describing the meaning and values for the -mcpu command-line option. Tested for bpf-unknown-none on x86_64-linux-gnu host. gcc/ChangeLog: * config/bpf/bpf.opt: Add help information for -mcpu. Signed-off-by: Will Hawkins <hawkinsw@obs.cr>
2024-02-20aarch64: Fix streaming-compatible code with -mtrack-speculation [PR113805]Richard Sandiford6-21/+82
This patch makes -mtrack-speculation work on streaming-compatible functions. There were two related issues. The first is that the streaming-compatible code was using TB(N)Z unconditionally, whereas those instructions are not allowed with speculation tracking. That part can be fixed in a similar way to the recent eh_return fix (PR112987). The second issue was that the speculation-tracking pass runs before some of the conditional branches are inserted. It isn't safe to insert the branches any earlier, so the patch instead adds a second speculation-tracking pass that runs afterwards. The new pass is only used for streaming-compatible functions. The testcase is adapted from call_sm_switch_1.c. gcc/ PR target/113805 * config/aarch64/aarch64-passes.def (pass_late_track_speculation): New pass. * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation): Declare. * config/aarch64/aarch64.md (is_call): New attribute. (*and<mode>3nr_compare0): Rename to... (@aarch64_and<mode>3nr_compare0): ...this. * config/aarch64/aarch64-sme.md (aarch64_get_sme_state) (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes. * config/aarch64/aarch64-speculation.cc: Update file comment to describe the new late pass. (aarch64_do_track_speculation): Handle is_call insns like other calls. (pass_track_speculation): Add an is_late member variable. (pass_track_speculation::gate): Run the late pass for streaming- compatible functions and the early pass for other functions. (make_pass_track_speculation): Update accordingly. (make_pass_late_track_speculation): New function. * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New function. (aarch64_guard_switch_pstate_sm): Use it. gcc/testsuite/ PR target/113805 * gcc.target/aarch64/sme/call_sm_switch_11.c: New test.
2024-02-19aarch64: Register rng builtins with uint64_t pointers.Iain Sandoe1-1/+2
Currently, these are registered as unsigned_intDI_type_node which is not necessarily the same type definition as uint64_t. On platforms where these differ that causes fails in consuming the arm_acle.h header. gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins): Register these builtins with a pointer to uint64_t rather than unsigned DI mode.
2024-02-19GCN: Conditionalize 'define_expand "reduc_<fexpander>_scal_<mode>"' on ↵Thomas Schwinge2-1/+5
'!TARGET_RDNA2_PLUS' [PR113615] On top of commit c7ec7bd1c6590cf4eed267feab490288e0b8d691 "amdgcn: add -march=gfx1030 EXPERIMENTAL" conditionalizing 'define_expand "reduc_<reduc_op>_scal_<mode>"' on '!TARGET_RDNA2' (later: '!TARGET_RDNA2_PLUS'), we then did similar in commit 7cc2262ec9a410dc56d1c1c6b950c922e14f621d "gcn/gcn-valu.md: Disable fold_left_plus for TARGET_RDNA2_PLUS [PR113615]" to conditionalize 'define_expand "fold_left_plus_<mode>"' on '!TARGET_RDNA2_PLUS', but I found we also need to conditionalize the related 'define_expand "reduc_<fexpander>_scal_<mode>"' on '!TARGET_RDNA2_PLUS', to avoid ICEs like: [...]/gcc.dg/vect/pr108608.c: In function 'foo': [...]/gcc.dg/vect/pr108608.c:9:1: error: unrecognizable insn: (insn 34 33 35 2 (set (reg:V64DF 723) (unspec:V64DF [ (reg:V64DF 690 [ vect_m_11.20 ]) (const_int 1 [0x1]) ] UNSPEC_MOV_DPP_SHR)) -1 (nil)) during RTL pass: vregs Similar for 'gcc.dg/vect/vect-fmax-2.c', 'gcc.dg/vect/vect-fmin-2.c', and 'UNSPEC_SMAX_DPP_SHR' for 'gcc.dg/vect/vect-fmax-1.c', and 'UNSPEC_SMIN_DPP_SHR' for 'gcc.dg/vect/vect-fmin-1.c', when running 'vect.exp' for 'check-gcc-c'. PR target/113615 gcc/ * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"): Conditionalize on '!TARGET_RDNA2_PLUS'. * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn) (gcn_expand_reduc_scalar): 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2024-02-19GCN: Restore lost '__gfx90a__' target CPU definitionThomas Schwinge1-0/+6
Also, add some safeguards for the future. Fix-up for commit 52a2c659ae6c21f84b6acce0afcb9b93b9dc71a0 "GCN: Add pre-initial support for gfx1100". gcc/ * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost '__gfx90a__' target CPU definition. Add some safeguards for the future.
2024-02-19RISC-V: Suppress the vsetvl fusion for conflict successorsJuzhe-Zhong1-0/+25
Update in v2: Add dump information. This patch fixes the following ineffective vsetvl insertion: void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, size_t cond2) { for (size_t i = 0; i < n; i++) { if (i == cond) { vint8mf8_t v = *(vint8mf8_t*)(in + i + 100); *(vint8mf8_t*)(out + i + 100) = v; } else if (i == cond2) { vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200); *(vfloat32mf2_t*)(out + i + 200) = v; } else if (i == (cond2 - 1)) { vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300); *(vuint16mf2_t*)(out + i + 300) = v; } else { vint8mf4_t v = *(vint8mf4_t*)(in + i + 400); *(vint8mf4_t*)(out + i + 400) = v; } } } Before this patch: f: .LFB0: .cfi_startproc beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 vsetvli t3,zero,e8,mf8,ta,ma ---> ineffective uplift .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) vsetvli t3,zero,e8,mf8,ta,ma .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: vsetvli t1,zero,e8,mf4,ta,ma addi t5,a0,-400 addi t4,a1,-400 vle16.v v1,0(t5) vse16.v v1,0(t4) vsetvli t3,zero,e8,mf8,ta,ma j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 It's obvious that we are hoisting the e8mf8 vsetvl to the top. It's ineffective since e8mf8 comes from low probability block which is if (i == cond). For this case, we disable such fusion. After this patch: f: beq a2,zero,.L12 addi a7,a0,400 addi a6,a1,400 addi a0,a0,1600 addi a1,a1,1600 li a5,0 addi t6,a4,-1 .L7: beq a3,a5,.L15 beq a4,a5,.L16 beq t6,a5,.L17 vsetvli t1,zero,e8,mf4,ta,ma vle8.v v1,0(a0) vse8.v v1,0(a1) .L4: addi a5,a5,1 addi a7,a7,4 addi a6,a6,4 addi a0,a0,4 addi a1,a1,4 bne a2,a5,.L7 .L12: ret .L15: vsetvli t3,zero,e8,mf8,ta,ma vle8.v v1,0(a7) vse8.v v1,0(a6) j .L4 .L17: addi t5,a0,-400 addi t4,a1,-400 vsetvli t1,zero,e8,mf4,ta,ma vle16.v v1,0(t5) vse16.v v1,0(t4) j .L4 .L16: addi t5,a0,-800 addi t4,a1,-800 vsetvli t3,zero,e32,mf2,ta,ma vle32.v v1,0(t5) vse32.v v1,0(t4) j .L4 Tested on both RV32/RV64 no regression. Ok for trunk ? PR target/113696 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Suppress vsetvl fusion. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr113696.c: New test.
2024-02-18x86-64: Generate push2/pop2 only if the incoming stack is 16-byte alignedH.J. Lu1-6/+18
Since push2/pop2 requires 16-byte stack alignment, don't generate them if the incoming stack isn't 16-byte aligned. gcc/ PR target/113912 * config/i386/i386.cc (ix86_can_use_push2pop2): New. (ix86_pro_and_epilogue_can_use_push2pop2): Use it. (ix86_emit_save_regs): Don't generate push2 if ix86_can_use_push2pop2 return false. (ix86_expand_epilogue): Don't generate pop2 if ix86_can_use_push2pop2 return false. gcc/testsuite/ PR target/113912 * gcc.target/i386/apx-push2pop2-2.c: New test.
2024-02-18LoongArch: Remove redundant symbol type conversions in larchintrin.h.Lulu Cheng1-36/+33
gcc/ChangeLog: * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant symbol type conversions. (__cacop_d): Likewise. (__cpucfg): Likewise. (__asrtle_d): Likewise. (__asrtgt_d): Likewise. (__lddir_d): Likewise. (__ldpte_d): Likewise. (__crc_w_b_w): Likewise. (__crc_w_h_w): Likewise. (__crc_w_w_w): Likewise. (__crc_w_d_w): Likewise. (__crcc_w_b_w): Likewise. (__crcc_w_h_w): Likewise. (__crcc_w_w_w): Likewise. (__crcc_w_d_w): Likewise. (__csrrd_w): Likewise. (__csrwr_w): Likewise. (__csrxchg_w): Likewise. (__csrrd_d): Likewise. (__csrwr_d): Likewise. (__csrxchg_d): Likewise. (__iocsrrd_b): Likewise. (__iocsrrd_h): Likewise. (__iocsrrd_w): Likewise. (__iocsrrd_d): Likewise. (__iocsrwr_b): Likewise. (__iocsrwr_h): Likewise. (__iocsrwr_w): Likewise. (__iocsrwr_d): Likewise. (__frecipe_s): Likewise. (__frecipe_d): Likewise. (__frsqrte_s): Likewise. (__frsqrte_d): Likewise.
generated by cgit v1.1 at 2025-09-20 02:12:52 +0000