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2016-11-16[ARC] Fix LE tests for nps400 variant.Andrew Burgess1-0/+14
2016-11-16Fix pdp11 buildRichard Sandiford1-0/+1
2016-11-16Fix missing brackets in arc.cRichard Sandiford1-1/+1
2016-11-16[ARM] PR target/78364: Add proper restrictions to zero and sign_extract patte...Kyrylo Tkachov1-6/+10
2016-11-15Fix instances of gen_rtx_REG (VOIDmode, ...)Richard Sandiford8-8/+8
2016-11-15[ARC] New option handling, refurbish multilib support.Claudiu Zissulescu19-272/+1146
2016-11-15MIPS/GCC: Mark trailing labels with `.insn'Maciej W. Rozycki2-0/+62
2016-11-14rs6000.c (rs6000_expand_vector_set): Add support for using xxinsertw and vins...Michael Meissner2-8/+54
2016-11-14i386.md (*andndi3_doubleword): Merge operand constraints.Uros Bizjak1-6/+6
2016-11-14The second patch updates the Cortex-A57 scheduler now that we can differentia...Wilco Dijkstra1-2/+2
2016-11-14Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm".Wilco Dijkstra7-17/+19
2016-11-14The existing vector costs stop some beneficial vectorization.Wilco Dijkstra1-3/+3
2016-11-14re PR target/78093 ([avr] New variable attribute "absdata" and option "-mabsd...Georg-Johann Lay6-9/+25
2016-11-13re PR target/78336 (powerpc-darwin bootstrap broken (probably by 241930))David Edelsohn1-0/+2
2016-11-12rs6000: Don't forget to initialize the TOC (PR77957)Segher Boessenkool1-40/+41
2016-11-11i386.md (*<shift_insn><mode>3_doubleword): Mark operand 0 as earlyclobber.Uros Bizjak1-1/+1
2016-11-11re PR target/78243 (incorrect byte offset in vextractuh with -mcpu=power9)Michael Meissner2-5/+8
2016-11-11re PR target/78310 (ICE: insn does not satisfy its constraints: {*bmi2_rorxdi...Uros Bizjak1-4/+6
2016-11-10rs6000.c (rs6000_hard_regno_mode_ok): If ISA 3.0...Michael Meissner3-197/+313
2016-11-10[ARM] Remove duplicated enum type for CPU identifiersRichard Earnshaw7-135/+125
2016-11-10[ARM/AArch64] Add Falkor CPU support.Siddhesh Poyarekar7-5/+13
2016-11-09re PR target/78262 (wrong code with -fschedule-insns)Uros Bizjak1-1/+1
2016-11-09re PR target/78254 (FAIL: g++.dg/torture/pr77822.C -O3 -g (internal compil...Andreas Schwab1-10/+16
2016-11-08re PR target/70799 (STV pass does not convert DImode shifts)Uros Bizjak1-5/+26
2016-11-08[ARM][2/2] Remove old rtx costsKyrylo Tkachov3-1222/+8
2016-11-08[ARM][1/2] Use generic_extra_costs in all remaining tuning structsKyrylo Tkachov1-9/+9
2016-11-08[Patch AArch64] aarch64-c.o should depend on TARGET_HJames Greenhalgh1-1/+1
2016-11-07re PR target/78229 (ICE in redirect_eh_edge_1, at tree-eh.c:2305)Jakub Jelinek1-2/+2
2016-11-07rs6000: Do swdiv at expand timeSegher Boessenkool2-2/+18
2016-11-07Fix typo.David Edelsohn1-2/+2
2016-11-07configure.ac (.hidden): Change to conftest_s string.David Edelsohn4-45/+125
2016-11-07re PR target/78227 (ICE: unrecognizable insn: in extract_insn, at recog.c:231...Jakub Jelinek1-0/+1
2016-11-07re PR target/78229 (ICE in redirect_eh_edge_1, at tree-eh.c:2305)Richard Biener1-1/+1
2016-11-07[AArch64] Fix PR target/77822: Use tighter predicates for zero_extract patternsKyrylo Tkachov1-8/+18
2016-11-04rs6000.c (gimple-ssa.h): New #include.Bill Schmidt1-0/+43
2016-11-04Start adding target-specific selftestsDavid Malcolm1-0/+34
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme5-7/+12
2016-11-04Add support for ARM Cortex-M23 processorThomas Preud'homme6-9/+14
2016-11-04[ARC] Various small miscellaneous fixes.Claudiu Zissulescu6-61/+41
2016-11-04Fix wrong patch committedMichael Meissner1-1/+1
2016-11-03re PR target/78192 (extract from vector registers to int results in wrong dat...Michael Meissner1-4/+3
2016-11-03re PR bootstrap/77993 (bootstrap failure on PowerPC/Linux)Michael Meissner2-4/+5
2016-11-03[arm] Eliminate SUBTARGET_CPU_DEFAULTRichard Earnshaw7-44/+3
2016-11-03sparc.md (vec_interleave_lowv8qi): Delete.Eric Botcazou1-28/+0
2016-11-03rs6000.c (rs6000_xcoff_declare_object_name): Use symtab_node::get_create.Richard Biener1-2/+2
2016-11-03[ARC] Define SIZE_TYPE and PTRDIFF_TYPE correctly.Vineet Gupta1-2/+2
2016-11-03make targetm.gen_ccmp{first,next} take rtx_insn **Trevor Saunders1-5/+5
2016-11-02i386.c (ix86_init_libfuncs): New.Uros Bizjak1-7/+46
2016-11-02nvptx.c (PTX_GANG_DEFAULT): Set to zero.Cesar Philippidis1-1/+1
2016-11-02xtensa: fix ICE on pr59037.c testMax Filippov1-21/+23
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