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AgeCommit message (Expand)AuthorFilesLines
2023-11-28amdgcn: Disallow TImode vector permuteAndrew Stubbs1-1/+3
2023-11-28amdgcn: Fix vector TImode reload loopAndrew Stubbs1-4/+4
2023-11-28amdgcn: Add Accelerator VGPR registersAndrew Stubbs7-203/+543
2023-11-28amdgcn: simplify secondary reload patternsAndrew Stubbs2-90/+4
2023-11-10amdgcn: Fix vector min/max ICEAndrew Stubbs1-1/+9
2023-11-10amdgcn: silence warningsAndrew Stubbs2-3/+5
2023-11-10amdgcn: switch mov insns to compact syntaxAndrew Stubbs2-148/+120
2023-11-10amdgcn: silence warningAndrew Stubbs1-1/+1
2023-10-26Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus6-50/+50
2023-10-26LoongArch: Define macro CLEAR_INSN_CACHE.Lulu Cheng1-0/+5
2023-10-26LoongArch: Implement __builtin_thread_pointer for TLS.chenxiaolong1-0/+7
2023-10-23SH: Fix PR 111001Oleg Endo1-1/+8
2023-10-22rs6000: Make 32 bit stack_protect support prefixed insn [PR111367]Kewen Lin1-46/+27
2023-10-20SH: Fix PR 101177Oleg Endo1-1/+1
2023-10-17Disparage slightly for the alternative which move DFmode between SSE_REGS and...liuhongt1-2/+2
2023-10-16Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus1-38/+36
2023-10-15rs6000: Use default target option node for callee by default [PR111380]Kewen Lin1-35/+30
2023-10-15rs6000: Skip empty inline asm in rs6000_update_ipa_fn_target_info [PR111366]Kewen Lin1-3/+6
2023-10-06Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus3-6/+44
2023-10-02Disable generation of scalar modulo instructions.Pat Haugen3-6/+44
2023-09-29Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus5-28/+55
2023-09-29AArch64: List official cores before codenamesWilco Dijkstra2-4/+4
2023-09-29AArch64: Fix memmove operand corruption [PR111121]Wilco Dijkstra3-18/+29
2023-09-20aarch64: Fix loose ldpstp check [PR111411]Richard Sandiford1-5/+3
2023-09-20aarch64: Fix return register handling in untyped_callRichard Sandiford1-1/+19
2023-09-18Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus7-414/+337
2023-09-18RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]xuli2-153/+2
2023-09-12aarch64: Make stack smash canary protect saved registersRichard Sandiford1-6/+40
2023-09-12aarch64: Remove below_hard_fp_saved_regs_sizeRichard Sandiford2-31/+21
2023-09-12aarch64: Explicitly record probe registers in frame infoRichard Sandiford2-14/+62
2023-09-12aarch64: Simplify probe of final frame allocationRichard Sandiford1-8/+4
2023-09-12aarch64: Put LR save probe in first 16 bytesRichard Sandiford1-42/+30
2023-09-12aarch64: Tweak stack clash boundary conditionRichard Sandiford1-1/+3
2023-09-12aarch64: Minor initial adjustment tweakRichard Sandiford1-3/+2
2023-09-12aarch64: Simplify top of frame allocationRichard Sandiford1-15/+8
2023-09-12aarch64: Measure reg_offset from the bottom of the frameRichard Sandiford2-29/+27
2023-09-12aarch64: Tweak frame_size commentRichard Sandiford1-2/+2
2023-09-12aarch64: Rename hard_fp_offset to bytes_above_hard_fpRichard Sandiford2-16/+16
2023-09-12aarch64: Rename locals_offset to bytes_above_localsRichard Sandiford2-6/+6
2023-09-12aarch64: Only calculate chain_offset if there is a chainRichard Sandiford1-5/+5
2023-09-12aarch64: Tweak aarch64_save/restore_callee_savesRichard Sandiford2-32/+28
2023-09-12aarch64: Add bytes_below_hard_fp to frame infoRichard Sandiford2-3/+8
2023-09-12aarch64: Add bytes_below_saved_regs to frame infoRichard Sandiford2-35/+41
2023-09-12aarch64: Explicitly handle frames with no saved registersRichard Sandiford1-3/+5
2023-09-12aarch64: Avoid a use of callee_offsetRichard Sandiford1-3/+1
2023-09-12aarch64: Use local frame vars in shrink-wrapping codeRichard Sandiford1-59/+64
2023-09-12rs6000: call vector load/store with length only on 64-bit Power10Haochen Gui1-4/+10
2023-09-11i386: Handle CONST_WIDE_INT in output_pic_addr_const [PR111340]Uros Bizjak1-2/+2
2023-09-11Remove constraint modifier % for fcmaddcph/fmaddcph/fcmulcph since there're n...liuhongt1-4/+12
2023-09-08Merge branch 'releases/gcc-13' into devel/omp/gcc-13Tobias Burnus3-5/+17
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