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2024-07-28[RISC-V][target/116085] Fix rv64 minmax extension avoidance splitterJeff Law2-18/+29
2024-07-28aarch64: sve: Rename aarch64_bic to standard pattern, andnAndrew Pinski2-3/+3
2024-07-28aarch64: Use iorn and andn standard pattern names for scalar modesAndrew Pinski1-6/+6
2024-07-28aarch64: Rename bic/orn patterns to iorn/andn for vector modesAndrew Pinski1-10/+10
2024-07-28aarch64: Fix target/optimize option handling with transiting between O1 to O2Andrew Pinski1-1/+1
2024-07-28RISC-V: Work around bare apostrophe in error string.Robin Dapp1-1/+1
2024-07-28i386: Use BLKmode for {ld,st}tilecfgHaochen Jiang2-8/+6
2024-07-28rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df, __buil...Carl Love3-81/+10
2024-07-28rs6000, Remove __builtin_vec_set_v1ti, __builtin_vec_set_v2df, __builtin_vec_...Carl Love2-53/+0
2024-07-28rs6000, remove __builtin_vsx_xvcmp* built-insCarl Love1-9/+0
2024-07-28RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressingChristoph Müllner1-4/+2
2024-07-28rtl-ssa: Define INCLUDE_ARRAYRichard Sandiford4-0/+4
2024-07-28RISC-V: Error early with V and no M extension.Robin Dapp1-0/+5
2024-07-28RISC-V: Allow LICM hoist POLY_INT configuration code sequenceJuzhe-Zhong1-4/+5
2024-07-28SVE Intrinsics: Change return type of redirect_call to gcall.Jennifer Schmitz3-5/+5
2024-07-28i386: Adjust rtx cost for imulq and imulw [PR115749]Lingling Kong1-8/+8
2024-07-28aarch64: Extend aarch64_feature_flags to 128 bitsAndrew Carlotti4-13/+25
2024-07-28aarch64: Use constructor explicitly in get_flags_offAndrew Carlotti1-2/+3
2024-07-28aarch64: Add bool conversion to TARGET_* macrosAndrew Carlotti5-131/+79
2024-07-28aarch64: Add explicit bool cast to return valueAndrew Carlotti1-1/+1
2024-07-28aarch64: Decouple feature flag option storage typeAndrew Carlotti2-5/+10
2024-07-28aarch64: Define aarch64_get_{asm_|}isa_flagsAndrew Carlotti2-22/+25
2024-07-28aarch64: Introduce aarch64_isa_mode typeAndrew Carlotti4-77/+94
2024-07-28aarch64: Eliminate a temporary variable.Andrew Carlotti1-5/+4
2024-07-28aarch64: Move AARCH64_NUM_ISA_MODES definitionAndrew Carlotti2-5/+5
2024-07-28aarch64: Remove unused global aarch64_tune_flagsAndrew Carlotti1-4/+0
2024-07-28optabs/rs6000: Rename iorc and andc to iorn and andnAndrew Pinski3-25/+25
2024-07-28Revert "aarch64: Fuse CMP+CSEL and CMP+CSET for -mcpu=neoverse-v2"Kyrylo Tkachov3-25/+1
2024-07-28aarch64: Fuse CMP+CSEL and CMP+CSET for -mcpu=neoverse-v2Jennifer Schmitz3-1/+25
2024-07-28RISC-V: Disable Zba optimization pattern if XTheadMemIdx is enabledChristoph Müllner1-1/+1
2024-07-28x86: Don't enable APX_F in 32-bit modeLingling Kong2-2/+4
2024-07-28RISC-V: Fix snafu in SI mode splitters patchVineet Gupta1-1/+1
2024-07-28report message for operator %a on unaddressible operandJiufu Guo1-1/+6
2024-07-28Relax ix86_hardreg_mov_ok after split1.liuhongt1-3/+2
2024-07-28rs6000: Update option set in rs6000_inner_target_options [PR115713]Kewen Lin1-1/+2
2024-07-28rs6000: Consider explicitly set options in target option parsing [PR115713]Kewen Lin1-2/+5
2024-07-28rs6000: Escalate warning to error for VSX with explicit no-altivec etc.Kewen Lin1-18/+23
2024-07-28i386: Change prefetchi output templateHaochen Jiang1-1/+1
2024-07-28RISC-V: Implement the .SAT_TRUNC for scalarPan Li4-0/+61
2024-07-28Add -mcpu=power11 support.Michael Meissner16-87/+127
2024-07-28aarch64: Tighten aarch64_simd_mem_operand_p [PR115969]Richard Sandiford1-2/+3
2024-07-28AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR11...Tamar Christina1-0/+12
2024-07-21SH: Fix outage caused by recently added 2nd combine pass after reg allocOleg Endo1-1/+9
2024-07-20LoongArch: Organize the code related to split move and merge the same functions.Lulu Cheng3-169/+58
2024-07-19AVR: Support new built-in function __builtin_avr_mask1.Georg-Johann Lay3-0/+201
2024-07-19bpf: create modifier for mem operand for xchg and cmpxchgCupertino Miranda2-6/+18
2024-07-18rs6000: Fix .machine cpu selection w/ altivec [PR97367]René Rebe1-1/+4
2024-07-18Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOVliuhongt2-6/+32
2024-07-17alpha: Fix duplicate !tlsgd!62 assemble error [PR115526]Uros Bizjak1-3/+7
2024-07-17AVR: target/90616 - Improve adding constants that are 0 mod 256.Georg-Johann Lay4-0/+47
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