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AgeCommit message (Expand)AuthorFilesLines
2014-05-21config.gcc (*-*-dragonfly*): New target.John Marino4-0/+353
2014-05-21Make the Blackfin port build again.Bernd Schmidt1-5/+9
2014-05-21re PR target/54236 ([SH] Improve addc and subc insn utilization)Oleg Endo1-4/+19
2014-05-20msp430.md (split): Don't allow subregs when splitting SImode adds.DJ Delorie2-4/+8
2014-05-20tree.h (DECL_ONE_ONLY): Return true only for externally visible symbols.Jan Hubicka6-8/+8
2014-05-20msp430.c (TARGET_GIMPLIFY_VA_ARG_EXPR): Define.Nick Clifton1-1/+116
2014-05-20[ARM] Adjust arith_shiftsi for -mrestrict-it.Kyrylo Tkachov1-0/+1
2014-05-20msp430.md (zero_extendpsisi2): Use + constraint on operand 0 in order to prev...Nick Clifton1-1/+7
2014-05-19arm.c (thumb1_reorg): When scanning backwards skip anything that's not a prop...Richard Earnshaw1-1/+1
2014-05-19re PR target/61195 (single precision fmov does not need to switch mode)Christian Bruel1-3/+23
2014-05-19re PR bootstrap/61084 (wide-int merge broke Solaris/SPARC bootstrap)Richard Sandiford1-4/+4
2014-05-19reg-notes.def (CROSSING_JUMP): Likewise.Richard Sandiford3-9/+9
2014-05-17use templates instead of gengtype for typed allocation functionsTrevor Saunders33-47/+47
2014-05-17ChangeLog:Ajit Agarwal4-14/+63
2014-05-17rs6000.c (rs6000_real_tls_symbol_ref_p): New function.Richard Sandiford1-1/+11
2014-05-16re PR target/54089 ([SH] Refactor shift patterns)Oleg Endo2-19/+41
2014-05-16re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)Oleg Endo3-9/+20
2014-05-16sh.c (sh_option_override): Set branch cost to 2 for all target variants.Oleg Endo1-5/+6
2014-05-16arc.c (arc_init): Fix typo in error message.Benno Schulenberg2-2/+2
2014-05-16[AArch64 costs] Fixup to costing of FNMULJames Greenhalgh1-10/+4
2014-05-16[AArch64 costs 18/18] Dump a message if we are unable to cost an insn.James Greenhalgh1-1/+5
2014-05-16[AArch64 costs 17/18] Cost for SYMBOL_REF, HIGH and LO_SUMJames Greenhalgh1-6/+35
2014-05-16[AArch64 costs 16/18] Cost TRUNCATEJames Greenhalgh1-0/+33
2014-05-16[AArch64 costs 15/18] Cost more Floating point RTX.James Greenhalgh1-0/+83
2014-05-16[AArch64 costs 14/18] Cost comparisons, flag setting operators and IF_THEN_ELSEJames Greenhalgh1-11/+148
2014-05-16[AArch64 costs 13/18] Improve costs for div/modJames Greenhalgh1-8/+7
2014-05-16[AArch64 costs 12/18] Improve costs for sign/zero extractsJames Greenhalgh1-2/+61
2014-05-16[AArch64 costs 11/18] Improve costs for rotate and shift operations.James Greenhalgh1-9/+47
2014-05-16[AArch64 costs 10/18] Improve costs for sign/zero extend operationsJames Greenhalgh1-6/+47
2014-05-16[AArch64 costs 9/18] Better cost logical operationsJames Greenhalgh1-5/+60
2014-05-16[AArch64 costs 8/18] Cost memory accesses using address costs James Greenhalgh1-2/+30
2014-05-16[AArch64 costs 7/18] Improve SET cost.James Greenhalgh1-8/+35
2014-05-16[AArch64 costs 6/18] Set default costs and handle vector modes.James Greenhalgh1-0/+15
2014-05-16[AArch64 costs 5/18] Factor out common MULT casesJames Greenhalgh1-110/+254
2014-05-16[AArch64 costs 4/18] Better estimate cost of building a constantJames Greenhalgh1-12/+84
2014-05-16[AArch64 costs 3/18] Wrap aarch64_rtx_costs to dump verbose outputJames Greenhalgh1-0/+21
2014-05-16[AArch64 costs 2/18] Add cost tables for Cortex-A57James Greenhalgh1-2/+43
2014-05-16[AArch64 costs 1/18] Refactor aarch64_address_costs.James Greenhalgh2-31/+117
2014-05-15re PR target/61193 (ABI incompatibility between POWER and Z HTM builtins and ...Peter Bergner1-2/+7
2014-05-15[ARM][cleanup] Use enum name instead of integer value for PARAM_SCHED_PRESSUR...Kyrylo Tkachov1-1/+2
2014-05-14sparc-protos.h (sparc_absnegfloat_split_legitimate): Delete.Eric Botcazou3-147/+161
2014-05-14msp430.c (msp430_builtin): Add MSP430_BUILTIN_DELAY_CYCLES.DJ Delorie2-0/+216
2014-05-14nios2.md (nios2_cbranch): Fix paste-o in length attribute computation.Sandra Loosemore1-2/+2
2014-05-14re PR bootstrap/61084 (wide-int merge broke Solaris/SPARC bootstrap)Richard Sandiford1-4/+4
2014-05-14gcc/Ilya Tocar11-14/+357
2014-05-14avr.h (REG_CLASS_CONTENTS): Use unsigned suffix for shifted values to avoid b...Georg-Johann Lay1-7/+7
2014-05-14re PR rtl-optimization/60901 (ICE: SIGSEGV in add_to_deps_list with -fsel-sch...Andrey Belevantsev1-4/+8
2014-05-13[ARM] Remove builtins for vzup, vuzp, vtrn and cleanup.Kyrylo Tkachov3-143/+0
2014-05-13Implement HARD_REGNO_CALLER_SAVE_MODE for AArch64Ian Bolton3-0/+25
2014-05-13target.def (mode_switching): New hook vector.Christian Bruel9-92/+128
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