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2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-04-27VAX: Fix ill-formed `jbb<ccss>i<mode>' insn operandsMaciej W. Rozycki1-6/+4
The insn has extraneous operand #3 that is aliased in RTL to operand #0 with a constraint. The operands specify a single-bit field in memory that the machine instruction produced boths reads for the purpose of determining whether to branch or not and either clears or sets according to the machine operation selected with the `ccss' iterator. The caller of the insn is supposed to supply the same rtx for both operands. This odd arrangement happens to work with old reload, but breaks with libatomic if LRA is used instead: .../libatomic/flag.c: In function 'atomic_flag_test_and_set': .../libatomic/flag.c:36:1: error: unable to generate reloads for: 36 | } | ^ (jump_insn 7 6 19 2 (unspec_volatile [ (set (pc) (if_then_else (eq (zero_extract:SI (mem/v:QI (reg:SI 27) [-1 S1 A8]) (const_int 1 [0x1]) (const_int 0 [0])) (const_int 1 [0x1])) (label_ref:SI 25) (pc))) (set (zero_extract:SI (mem/v:QI (reg:SI 28) [-1 S1 A8]) (const_int 1 [0x1]) (const_int 0 [0])) (const_int 1 [0x1])) ] 100) ".../libatomic/flag.c":35:10 669 {jbbssiqi} (nil) -> 25) during RTL pass: reload .../libatomic/flag.c:36:1: internal compiler error: in curr_insn_transform, at lra-constraints.c:4098 0x1112c587 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) .../gcc/rtl-error.c:108 0x10ee6563 curr_insn_transform .../gcc/lra-constraints.c:4098 0x10eeaf87 lra_constraints(bool) .../gcc/lra-constraints.c:5133 0x10ec97e3 lra(_IO_FILE*) .../gcc/lra.c:2336 0x10e4633f do_reload .../gcc/ira.c:5827 0x10e46b27 execute .../gcc/ira.c:6013 Please submit a full bug report, with preprocessed source if appropriate. Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. Switch to using `match_dup' as expected then for a machine instruction that in its encoding only has one actual operand in for the single-bit field. gcc/ * config/vax/builtins.md (jbb<ccss>i<mode>): Remove operand #3. (sync_lock_test_and_set<mode>): Adjust accordingly. (sync_lock_release<mode>): Likewise.
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-05PR target/95294: VAX: Convert backend to MODE_CC representationMaciej W. Rozycki1-14/+95
In the VAX ISA INSV bit-field insert instruction is the only computational operation that keeps the condition codes, held in the PSL or Processor Status Longword register, intact. The instruction is flexible enough it could potentially be used for data moves post-reload, but then reportedly it is not the best choice performance-wise, and then we have no addition operation available that would keep the condition codes unchanged. Futhermore, as usually with a complex CISC ISA, for many operations we have several machine instructions or instruction sequences to choose from that set condition codes in a different manner. Use the approach then where the condition codes only get introduced by reload, by definining instruction splitters for RTL insns that change condition codes in some way, by default considering them clobbered. Then to prevent code generated from regressing too much provide insns that include a `compare' operation setting the condition codes in parallel to the main operation. The manner condition codes are set by each insn is supposed to be provided by the whatever the SELECT_CC_MODE macro expands to. Given that individual patterns provided for the same RTL basic operation may set the condion codes differently keeping the information away from the insn patterns themselves would cause a maintenance nightmare and would be bound to fail in a horrible way sooner or later. Therefore instead let the patterns themselves choose which condition modes they support, by having one or more subst iterators applied and then have individual comparison operators require the specific condition mode each according to the codes used by the operation. While subst iterators only support one alternative each, there is actually no problem with applying multiple ones to a single insn with the result as intended, and if the corresponding subst attribute supplies an empty NO-SUBST-VALUE, then no mess results even. Make use of this observation. Add appropriate subst iterators to all the computational patterns then, according to the condition codes they usably set, including DImode ones and a substitute DImode comparison instruction in the absence of a CMPQ machine instruction, however do not provide a `cbranchdi4' named pattern as without a further development it regresses code quality by resorting to the `__cmpdi2' libcall where a simpler operation would do, e.g. to check for negativity the TSTL machine instruction may be executed over the upper longword only. This is good material for further work. Do not apply subst iterators to the increment- or decrement-and-branch patterns at this time; these may yet have to be reviewed, in particular whether `*jsobneq_minus_one' is still relevant in the context of the recent integer constant cost review. Also add a couple of peepholes to help eliminating comparisons in some problematic cases, such as with the BIT instruction which is bitwise-AND for condition codes only that has no direct counterpart for the actual calculation, because the BIC instruction which does do bitwise-AND and produces a result implements the operation with a bitwise negation of its input `mask' operand. Or the FFS instruction which sets the Z condition code according to its `field' input operand rather than the result produced. Or the bit-field comparisons we don't have generic middle-end support for. Code size stats are as follows, obtained from 17640 and 9086 executables built in `check-c' and `check-c++' GCC testing respectively: check-c check-c++ samples average median samples average median --------------------------------------------------------------- regressions 1813 0.578% 0.198% 289 0.349% 0.175% unchanged 15160 0.000% 0.000% 8662 0.000% 0.000% progressions 667 -0.589% -0.194% 135 -0.944% -0.191% ---------------------------------------------------------------- total 17640 0.037% 0.000% 9086 -0.003% 0.000% Outliers: old new change %change filename ---------------------------------------------------- 2406 2950 +544 +22.610 20111208-1.exe 4314 5329 +1015 +23.528 pr39417.exe 2235 3055 +820 +36.689 990404-1.exe 2631 4213 +1582 +60.129 pr57521.exe 3063 5579 +2516 +82.142 20000422-1.exe and: old new change %change filename ---------------------------------------------------- 6317 4845 -1472 -23.302 vector-compare-1.exe 6313 4845 -1468 -23.254 vector-compare-1.exe 6474 5002 -1472 -22.737 vector-compare-1.exe 6470 5002 -1468 -22.689 vector-compare-1.exe We have some code quality regressions like: 10861: 9e ef d9 12 movab 11b40 <p>,r0 10865: 00 00 50 10868: 90 a0 03 a0 movb 0x3(r0),0x2(r0) 1086c: 02 1086d: d1 60 8f 61 cmpl (r0),$0x64646261 10871: 62 64 64 10874: 13 07 beql 1087d <main_test+0x21> to: 10861: 9e ef e1 12 movab 11b48 <p>,r0 10865: 00 00 50 10868: 90 a0 03 a0 movb 0x3(r0),0x2(r0) 1086c: 02 1086d: d1 ef d5 12 cmpl 11b48 <p>,$0x64646261 10871: 00 00 8f 61 10875: 62 64 64 10878: 13 07 beql 10881 <main_test+0x25> (from `memmove-2.x2') due to the constant propagation passes eagerly replacing pseudo registers with direct symbol references where possible, which does not happen with CC0 even though the passes do run regardless. There are further code quality regressions due to earlier compilation stages trying to push expression evaluation earlier where possible so as to make data dependencies further apart from each other. This works well for computations and architectures that do not involve condition codes set as a side effect of calculations. However for integer negation that makes assembly code produced like: movb *8(%ap),%r0 mnegb %r0,%r1 tstb %r0 jeql .L2 the RTL equibvalent of which the comparison elimination pass cannot really do anything about, because the comparison is made on the source rather than the target operand of the negation (we could add a peephole for this, but this seems futile an effort, as one'd have to iterate over all the possible such cases), even though this is really equivalent to: movb *8(%ap),%r0 mnegb %r0,%r1 jeql .L2 or, if R0 is dead at the conclusion of the branch, even: mnegb *8(%ap),%r1 jeql .L2 Since the compiler insists on doing the comparison on the source of the negation it obviously has to load it into a temporary so as to avoid accessing the original memory location twice, hence the sequence of three instructions rather than just a single one. A similar phenomenon can be observed with the XOR operation and in other cases. In some cases a comparison does get eliminated, however useless moves into registers done in preparation to it remain, such as with: movb *8(%ap),%r2 movb *12(%ap),%r1 subb3 %r1,%r2,%r0 jlssu .L2 where R1 and R2 are both dead at conclusion and therefore: subb3 *12(%ap),*8(%ap),%r0 jlssu .L2 would obviously do, but there was to be a comparison before the branch: cmpb %r2,%r1 All this looks like material for future improvement. Test cases for comparison elimination and the peepholes will be supplied separately. gcc/ PR target/95294 * config/vax/elf.h (REGISTER_NAMES): Append `%psl'. * config/vax/vax-modes.def (CCN, CCNZ, CCZ): New modes. * config/vax/vax-protos.h (vax_select_cc_mode): New prototype. (vax_maybe_split_dimode_move): Likewise. (vax_notice_update_cc): Remove prototype. * config/vax/vax.c (TARGET_FLAGS_REGNUM): New macro. (TARGET_CC_MODES_COMPATIBLE): Likewise. (TARGET_MD_ASM_ADJUST): Likewise. (vax_select_cc_mode): New function (vax_cc_modes_compatible): Likewise. (vax_md_asm_adjust): Likewise. (vax_notice_update_cc): Remove function. (vax_output_int_move): Factor out code checking if a DImode move may have to be split... (vax_maybe_split_dimode_move): ... into this new function. * config/vax/vax.h (FIRST_PSEUDO_REGISTER): Bump up. (FIXED_REGISTERS): Append an entry for PSL. (CALL_USED_REGISTERS): Likewise. (NOTICE_UPDATE_CC, OUTPUT_JUMP): Remove macros. (SELECT_CC_MODE): New macro. (REGISTER_NAMES): Append `psl'. * config/vax/predicates.md (const_zero_operand) (vax_cc_comparison_operator, vax_ccn_comparison_operator) (vax_ccnz_comparison_operator, vax_ccz_comparison_operator): New predicates. * config/vax/builtins.md: Rewrite for MODE_CC representation. * config/vax/vax.md: Likewise.
2020-12-05VAX: Actually produce QImode and HImode `ctz' operationsMaciej W. Rozycki1-0/+22
The middle end does not refer to `ctzqi2'/`ctzhi2' or `ffsqi2'/`ffshi2' patterns by name where `__builtin_ctz' or `__builtin_ffs' respectively is invoked for an argument of the QImode or HImode type, and instead it extends the data type before passing it to `ctzsi2' or `ffssi2'. Avoid the redundant operation and use a peephole2 to convert it to the right RTL expression that will collapse the two operations into a single machine instruction instead unless we need the extended intermediate result for another purpose. gcc/ * config/vax/builtins.md: Add a peephole2 for QImode and HImode `ctz' operations. (any_extend): New code iterator. gcc/testsuite/ * gcc.target/vax/ctzhi.c: New test. * gcc.target/vax/ctzqi.c: New test. * gcc.target/vax/ffshi.c: New test. * gcc.target/vax/ffsqi.c: New test.
2020-12-05VAX: Also provide QImode and HImode `ctz' and `ffs' operationsMaciej W. Rozycki1-8/+9
The FFS machine instruction provides for arbitrary input bit-field widths so take advantage of this and convert `ffssi2' and `ctzsi2' to templates for all the three of QI, HI, SI machine modes. Test cases will be added separately. gcc/ * config/vax/builtins.md (width): New mode attribute. (ffssi2): Rework expander into... (ffs<mode>2): ... this. (ctzsi2): Rework insn into... (ctz<mode>2): ... this.
2020-12-05VAX: Provide the `ctz' operationMaciej W. Rozycki1-3/+3
Our `ffssi2_internal' pattern and the machine FFS instruction, which technically is a bit-field operation, match the `ctz' operation exactly, with the result produced for the bit-field source operand of zero equal to its width as specified with another machine instruction operand, not directly expressed in RTL and currently hardcoded in the assembly code produced. In our terms this is the bit size of the machine mode used, and although it's SImode now let's be flexible for an upcoming change. The operation also sets the Z condition code according to the value of the source operand. gcc/ * config/vax/builtins.md (ffssi2_internal): Rename insn to... (ctzsi2): ... this. Update the RTL operation. (ffssi2): Update accordingly. * config/vax/vax.c (vax_notice_update_cc): Handle CTZ. * config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro. gcc/testsuite/ * gcc.target/vax/ctzsi.c: New test.
2020-12-05VAX: Correct `sync_lock_test_and_set' and `sync_lock_release' builtinsMaciej W. Rozycki1-19/+17
Remove an ICE like: during RTL pass: expand .../libatomic/tas_n.c: In function 'libat_test_and_set_1': .../libatomic/tas_n.c:39:1: internal compiler error: in patch_jump_insn, at cfgrtl.c:1298 39 | } | ^ 0x108a09ff patch_jump_insn .../gcc/cfgrtl.c:1298 0x108a0b07 redirect_branch_edge .../gcc/cfgrtl.c:1325 0x108a124b rtl_redirect_edge_and_branch .../gcc/cfgrtl.c:1458 0x1087f6d3 redirect_edge_and_branch(edge_def*, basic_block_def*) .../gcc/cfghooks.c:373 0x11d6264b try_forward_edges .../gcc/cfgcleanup.c:562 0x11d6b0eb try_optimize_cfg .../gcc/cfgcleanup.c:2960 0x11d6ba4f cleanup_cfg(int) .../gcc/cfgcleanup.c:3174 0x10870b3f execute .../gcc/cfgexpand.c:6763 triggered with an RTL pattern like: (jump_insn 8 7 20 2 (parallel [ (set (pc) (if_then_else (ne (zero_extract:SI (mem/v:QI (mem/f/c:SI (reg/f:SI 16 virtual-incoming-args) [1 mptr+0 S4 A32]) [-1 S1 A8]) (const_int 1 [0x1]) (const_int 0 [0])) (const_int 0 [0])) (label_ref 10) (pc))) (set (zero_extract:SI (mem/v:QI (mem/f/c:SI (reg/f:SI 16 virtual-incoming-args) [1 mptr+0 S4 A32]) [-1 S1 A8]) (const_int 1 [0x1]) (const_int 0 [0])) (const_int 1 [0x1])) ]) ".../libatomic/tas_n.c":38:12 -1 (nil) -> 10) caused by a volatile memory reference used that is not accepted by the `memory_operand' predicate of the `jbbssiqi' insn explicitly referred from the `sync_lock_test_and_setqi' expander. Also seen with: FAIL: gcc.dg/pr61756.c (internal compiler error) Define a new `any_memory_operand' predicate accepting both ordinary and volatile memory references and use it with the `jbb<ccss>i<mode>' insn, so as to address the ICE. Also remove useless operations from the `sync_lock_test_and_set<mode>' and `sync_lock_release<mode>' expanders as those always either complete or fail and therefore never fall through to using their template other than to match operands. Wrap `jbb<ccss>i<mode>' into `unspec_volatile' instead so that the jump does not get removed or reordered. Share one index to avoid a complication around the iterators since the index is nowhere referred to anyway and the pattern required pulled by its name. Test cases will be added separately. gcc/ * config/vax/predicates.md (volatile_mem_operand) (any_memory_operand): New predicates. * config/vax/builtins.md (VUNSPEC_UNLOCK): Remove constant. (sync_lock_test_and_set<mode>): Remove `set' and `unspec' operations, match operands only. Reformat. (sync_lock_release<mode>): Likewise. Remove cruft. (jbb<ccss>i<mode>): Wrap into `unspec_volatile', use `any_memory_operand' predicate.
2020-12-05VAX: Use an int iterator to produce individual interlocked branchesMaciej W. Rozycki1-22/+7
With mode-specific interlocked branch insns already folded into iterated templates now fold the two templates into one too, observing that the only difference between them is the value of the bit branched on, which is of course reflected both in the RTL expression and the instruction produced. Use an int iterator to iterate over the bit value, making use of the newly-added wide integer support, and substituting patterns as necessary to produce equivalent individual insns. No functional change. gcc/ * config/vax/builtins.md (bit): New int iterator. (ccss): New int attribute. (jbbssi<mode>, jbbcci<mode>): Fold insns into... (jbb<ccss>i<mode>): ... this.
2020-12-05VAX: Use a mode iterator to produce individual interlocked branchesMaciej W. Rozycki1-81/+15
Regardless of the machine mode all the interlocked branches of the same kind, one of the two provided by the ISA, use the same RTL patterns and machine instructions, except for the memory operand's constraint. Remove code duplication then and make use of a mode iterator combined with an attribute to expand the same insn patterns with the constraint suitably substituted from a single template. No functional change. gcc/ * config/vax/builtins.md (bb_mem): New mode attribute. (jbbssiqi, jbbssihi, jbbssisi): Fold insns into... (jbbssi<mode>): ... this. (jbbcciqi, jbbccihi, jbbccisi): Likewise... (jbbcci<mode>): ... this.
2020-12-05VAX: Correct fatal issues with the `ffs' builtinMaciej W. Rozycki1-3/+9
The `builtins.md' machine description fragment is not included anywhere and is therefore dead code, which has become bitrotten due to non-use. If actually enabled, it does not build due to the use of an unknown `t' constraint: .../gcc/config/vax/builtins.md:42:1: error: undefined machine-specific constraint at this point: "t" .../gcc/config/vax/builtins.md:42:1: note: in operand 1 which came from commit becb93d02cc1 ("builtins.md (ffssi2_internal): Correct constraint."), which was not applied as posted and reviewed; `T' was meant to be used instead. Once this has been fixed this code still fails building: .../gcc/config/vax/builtins.md: In function 'rtx_def* gen_ffssi2(rtx, rtx)': .../gcc/config/vax/builtins.md:35:19: error: 'gen_bne' was not declared in this scope; did you mean 'gen_use'? 35 | emit_jump_insn (gen_bne (label)); | ^~~~~~~ | gen_use make[2]: *** [Makefile:1122: insn-emit.o] Error 1 Finally the FFS machine instruction sets the Z condition code according to the comparison of the value held in the source operand against zero rather than the value held in the target operand. If the source operand is found hold zero, then the target operand is set to the width of the source operand, 32 for SImode (FFS supports arbitrary widths). Correct the build issues then and update RTL to match the operation of the machine instruction. A test case will be added separately. gcc/ * config/vax/builtins.md (ffssi2): Make preparation statements actually buildable. (ffssi2_internal): Fix input constraints; make the RTL pattern match reality for `cc0'.
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r279813
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r267494
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-06-29builtins.md (ffssi2_internal): Correct constraint.Maya Rashish1-1/+1
2017-06-29 Maya Rashish <coypu@sdf.org> * config/vax/builtins.md (ffssi2_internal): Correct constraint. From-SVN: r249812
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r243994
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r232055
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r219188
2014-01-02Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r206289
2013-01-10Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r195098
2009-04-01[multiple changes]Matt Thomas1-0/+192
2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/vax.c: Add #includes to silence warnings. Change #include order to silence two warnings. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/linux.h (TARGET_DEFAULT): Add the MASK_QMATH flag bit. (ASM_SPEC): Pass -k to the assembler for PIC code. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config.gcc: Add vax-*-linux* to the switch. * gcc/config/vax/linux.h: New file. (TARGET_VERSION, TARGET_OS_CPP_BUILTINS, TARGET_DEFAULT, CPP_SPEC, LINK_SPEC): Define. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/vax.c (vax_output_int_move, adjacent_operands_p): Use predicate macros instead of GET_CODE() == foo. * gcc/config/vax/vax.md (movsi_2, movstrictqi, and<mode>3, ashrsi3, ashlsi3, rotrsi3, <unnamed>): Likewise. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/builtins.md (jbbssiqi, jbbssihi, jbbssisi, jbbcciqi, jbbccihi, jbbccisi): Remova trailing whitespace. * gcc/config/vax/constraints.md: Likewise. * gcc/config/vax/elf.h: (ASM_PREFERRED_EH_DATA_FORMAT): Likewise. * gcc/config/vax/openbsd1.h (OBSD_OLD_GAS): Likewise. * gcc/config/vax/predicates.md: Likewise. * gcc/config/vax/vax.c (print_operand_address, vax_output_int_move, vax_expand_addsub_di_operands, adjacent_operands_p): Likewise. * gcc/config/vax/vax.h: Likewise. * gcc/config/vax/vax.md (nonlocal_goto): Likewise. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/vax.c (vax_float_literal, vax_output_int_move) (indirectable_address_p, adjacent_operands_p): Add spaces around braces. * gcc/config/vax/vax-protos.h (adjacent_operands_p): Likewise. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/vax.c (legitimate_constant_address_p, legitimate_constant_p, indirectable_address_p, nonindexed_address_p, index_term_p, reg_plus_index_p, legitimate_address_p, vax_mode_dependent_address_p): Update comments to match functions modified by the recent int->bool conversion. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/builtins.md: Update copyright message. * gcc/config/vax/constraints.md: Likewise. * gcc/config/vax/netbsd-elf.h: Likewise. * gcc/config/vax/predicates.md: Likewise. * gcc/config/vax/vax-protos.h: Likewise. * gcc/config/vax/vax.c: Likewise. * gcc/config/vax/vax.h: Likewise. * gcc/config/vax/vax.md: Likewise. * gcc/config/vax/vax.opt: Likewise. 2009-04-01 Jan-Benedict Glaw <jbglaw@jbglaw-dev.homezone.telefonica.de> * gcc/config/vax/builtins.md (ffssi2, ffssi2_internal, sync_lock_test_and_set<mode>, sync_lock_release<mode>): Fix indention. * gcc/config/vax/constraints.md (B, R): Likewise. * gcc/config/vax/predicates.md (external_memory_operand, nonimmediate_addsub_di_operand): Likewise. * gcc/config/vax/vax.c (vax_output_int_add): Likewise. * gcc/config/vax/vax.md (movsi, movsi_2, mov<mode>, call_value, untyped_call): Likewise. 2009-04-01 Matt Thomas <matt@3am-software.com> * config/vax/predicates.md: New file. (symbolic_operand, local_symbolic_operand, external_symbolic_operand, external_const_operand, nonsymbolic_operand, external_memory_operand, indirect_memory_operand, indexed_memory_operand, illegal_blk_memory_operand, illegal_addsub_di_memory_operand, nonimmediate_addsub_di_operand, general_addsub_di_operand): New predicate. * config/vax/constraints.md: New file. (Z0, U06, U08, U16, CN6, S08, S16, I, J, K, L, M, N, O, G, Q, B, R, T): New constraint. * config/vax/builtins.md: New file. (ffssi2, ffssi2_internal, sync_lock_test_and_set<mode>, jbbssiqi, jbbssihi, jbbssisi, sync_lock_release<mode>, jbbcciqi, jbbccihi, jbbccisi): Define. * config/vax/vax.opt (mqmath): Add option. * config/vax/vax.md (isfx): Extend with DI. (VAXintQH, VAXintQHSD): Define. (tst<mode>, cmp<mode>, *bit<mode>, movmemhi1, truncsiqi2, truncsihi2, mulsidi3, add<mode>3, sub<mode>, mul<mode>3, div<mode>3, and<mode>, and<mode>_const_int, ior<mode>3, xor<mode>3, neg<mode>2, one_cmpl<mode>2, ashlsi3, lshrsi3, rotlsi3): Update constraints. (movdi): Update constraints and use vax_output_int_move(). (movsi, movsi_2, pushlclsymreg, pushextsymreg, movlclsymreg, movextsymreg, adddi3, adcdi3, subdi3, sbcdi3, pushextsym, movextsym, pushlclsym, movlclsym, movaddr<mode>, pushaddr<mode>, nonlocal_goto): New. (mov<mode>): Extend accepted operand types. (subdi3_old): Rename from subdi3, change update constraints and use a new implementation. * gcc/config/vax/vax.h (PCC_BITFIELD_TYPE_MATTERS): Add space. (FRAME_POINTER_CFA_OFFSET, IRA_COVER_CLASSES, CLASS_MAX_NREGS, MOVE_RATIO, CLEAR_RATIO): Define. (REG_CLASS_FROM_LETTER, CONST_OK_FOR_LETTER_P, CONST_DOUBLE_OK_FOR_LETTER_P, EXTRA_CONSTRAINT): Delete. (PRINT_OPERAND): Redefine using a function instead of inlined code. * gcc/config/vax/vax.c (TARGET_BUILTIN_SETJMP_FRAME_VALUE): Define. (split_quadword_operands): Make static and really allow variable splitting. (print_operand_address): Update for PIC generation. (print_operand, vax_builtin_setjmp_frame_value, vax_output_int_subtract, indexable_address_p, fixup_mathdi_operand, vax_expand_addsub_di_operands, adjacent_operands_p): New. (vax_float_literal, legitimate_constant_p, indirectable_constant_address_p, index_term_p, reg_plus_index_p): Return bool instead of int. (vax_rtx_costs): Fix cost for CONST_INT, indent and use HOST_WIDE_INT where needed. (vax_output_int_move, vax_output_int_add): Extend to allow PIC generation. (vax_output_conditional_branch): Indent. (legitimate_constant_address_p, indirectable_constant_address_p, indirectable_address_p, nonindexed_address_p, legitimate_address_p, vax_mode_dependent_address_p): Return bool instead of int, update for PIC generation. * config/vax/vax-protos.h (legitimate_constant_address_p, legitimate_constant_p, legitimate_address_p, vax_mode_dependent_address_p): Change declaration to bool. (legitimate_pic_operand_p, adjacent_operands_p, print_operand, vax_expand_addsub_di_operands, vax_output_int_subtract, vax_output_movmemsi): Declare. (split_quadword_operands, vax_float_literal): Delete declaration. * config/vax/netbsd-elf.h (CC1_SPEC, CC1PLUS_SPEC) Define. * config/vax/elf.h (NO_EXTERNAL_INDIRECT_ADDRESS, VAX_CC1_AND_CC1PLUS_SPEC, ASM_PREFERRED_EH_DATA_FORMAT, ASM_OUTPUT_DWARF_PCREL): Define. (ASM_SPEC): Change definition to allow PIC generation. From-SVN: r145416
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