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2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-09-16sparc: Add scheduling information for LEON5Daniel Cederman1-0/+1
The LEON5 can often dual issue instructions from the same 64-bit aligned double word if there are no data dependencies. Add scheduling information to avoid scheduling unpairable instructions back-to-back. gcc/ChangeLog: * config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5 * config/sparc/sparc.c (struct processor_costs): Add LEON5 costs (leon5_adjust_cost): Increase cost of store with data dependency on ALU instruction and FPU anti-dependencies. (sparc_option_override): Add LEON5 costs (sparc_adjust_cost): Add LEON5 cost adjustments * config/sparc/sparc.h: Add LEON5 * config/sparc/sparc.md: Include LEON5 scheduling information * config/sparc/sparc.opt: Add LEON5 * doc/invoke.texi: Add LEON5 * config/sparc/leon5.md: New file.
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r279813
2019-02-26sparc-opts.h (enum processor_type): Rename to...Eric Botcazou1-5/+14
* config/sparc/sparc-opts.h (enum processor_type): Rename to... (enum sparc_processor_type): ...this. (enum sparc_code_model_type): New enumeration type. (enum sparc_memory_model_type): Tweak comments. * config/sparc/sparc.opt (mcpu): Adjust to above renaming. (mtune): Likewise. (mcmodel): Use sparc_code_model enumeration and variable. (sparc_code_model): New enumeration. (mdebug): Add Undocumented marker. * config/sparc/sparc.h (enum cmodel): Delete. (sparc_cmodel): Likewise. (TARGET_CM_MEDLOW): Adjust to above renaming. (TARGET_CM_MEDMID): Likewise. (TARGET_CM_MEDANY): Likewise. (TARGET_CM_EMBMEDANY): Likewise. * config/sparc/sparc.c (sparc_cmodel): Delete. (sparc_option_override): Remove string/value mapping support for the code model. Move code and memory model support to after the handling of target flags. Do private machine setup last. (sparc_emit_set_symbolic_const64): Use sparc_code_model. (sparc_legitimize_reload_address): Likewise. (sparc_output_mi_thunk): Likewise. * config/sparc/sparc.md (cpu): Adjust comment to above renaming. From-SVN: r269232
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r267494
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-07-07Support for the SPARC M8 cpu.Jose E. Marchesi1-0/+1
This patch serie adds support for the SPARC M8 processor to GCC. The SPARC M8 processor implements the Oracle SPARC Architecture 2017. - bmask* instructions are put in their own instruction type. It makes little sense to have them in the same category than array instructions. - Similarly, VIS compare instructions are put in their own instruction type. This is to better accommodate subtypes, which are not quite the same than the subtypes of `visl' instructions. - The introduction of a new `subtype' insn attribute in sparc.md avoids the need for adjusting the instruction scheduler DFAs for previous cpu models every time a new cpu is introduced. - The full set of SPARC instructions used in sparc.md, and their position in the type/subtype hierarchy, is documented in a comment. This eases the modification of the DFA schedulers, and the addition of new cpus. - The M7 DFA scheduler is reworked: + To use the new type/subtype hierarchy. + The v3pipe insn attribute is no longer needed. + More accurate latencies for instructions. + The C4 core pipeline is documented in a comment in niagara7.md. - Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN denomination for M8 and later processors.) - Support for a new VIS level, VIS4B, covering the new VIS instructions introduced in OSA2017 and implemented in the M8. Also built-ins. - A M8 DFA scheduler: + Also based on the new type/subtype hierarchy. + The functional units in the C5 core are explicitly documented in a comment in m8.md. gcc/ChangeLog: * config/sparc/m8.md: New file. * config/sparc/sparc.md: Include m8.md. * config/sparc/sparc.opt: New option -mvis4b. * config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B. (sparc_option_override): Handle VIS4B. (enum sparc_builtins): Define SPARC_BUILTIN_DICTUNPACK{8,16,32}, SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL, SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL, SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and SPARC_BUILTIN_FPCMPUR{8,16,32}SHL. (check_constant_argument): New function. (sparc_vis_init_builtins): Define builtins __builtin_vis_dictunpack{8,16,32}, __builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl, __builtin_vis_fpcmpu{le,gt}{8,16,32}shl, __builtin_vis_fpcmpde{8,16,32}shl and __builtin_vis_fpcmpur{8,16,32}shl. (sparc_expand_builtin): Check that the constant operands to __builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed constant and in range. * config/sparc/sparc-c.c (sparc_target_macros): Handle TARGET_VIS4B. * config/sparc/sparc.h (SPARC_IMM2_P): Define. (SPARC_IMM5_P): Likewise. * config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b". (enabled): Handle vis4b. (UNSPEC_DICTUNPACK): New unspec. (UNSPEC_FPCMPSHL): Likewise. (UNSPEC_FPUCMPSHL): Likewise. (UNSPEC_FPCMPDESHL): Likewise. (UNSPEC_FPCMPURSHL): Likewise. (cpu_feature): New CPU feature `vis4b'. (dictunpack{8,16,32}): New insns. (FPCSMODE): New mode iterator. (fpcscond): New code iterator. (fpcsucond): Likewise. (fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns. (fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise. (fpcmpde{8,16,32}{si,di}shl): Likewise. (fpcmpur{8,16,32}{si,di}shl): Likewise. * config/sparc/constraints.md: Define constraints `q' for unsigned 2-bit integer constants and `t' for unsigned 5-bit integer constants. * config/sparc/predicates.md (imm5_operand_dictunpack8): New predicate. (imm5_operand_dictunpack16): Likewise. (imm5_operand_dictunpack32): Likewise. (imm2_operand): Likewise. * doc/invoke.texi (SPARC Options): Document -mvis4b. * doc/extend.texi (SPARC VIS Built-in Functions): Document the ditunpack* and fpcmp*shl builtins. * config.gcc: Handle m8 in --with-{cpu,tune} options. * config.in: Add HAVE_AS_SPARC6 define. * config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC M8. * config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for TARGET_CPU_m8. (ASM_CPU32_DEFAUILT_SPEC): Likewise. (CPP_CPU_SPEC): Handle m8. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_M8. * config/sparc/sparc.c (m8_costs): New struct. (sparc_option_override): Handle TARGET_CPU_m8. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. * config/sparc/sparc.h (TARGET_CPU_m8): Define. (CPP_CPU64_DEFAULT_SPEC): Define for M8. (ASM_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle M8. (ASM_CPU_SPEC): Likewise. (AS_M8_FLAG): Define. * config/sparc/sparc.md: Add m8 to the cpu attribute. * config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets. * configure.ac (HAVE_AS_SPARC6): Check for assembler support for M8 instructions. * configure: Regenerate. * doc/invoke.texi (SPARC Options): Document -mcpu=m8 and -mtune=m8. * config/sparc/niagara7.md: Rework the DFA scheduler to use insn subtypes. * config/sparc/sparc.md: Remove the `v3pipe' insn attribute. ("*movdi_insn_sp32"): Do not set v3pipe. ("*movsi_insn"): Likewise. ("*movdi_insn_sp64"): Likewise. ("*movsf_insn"): Likewise. ("*movdf_insn_sp32"): Likewise. ("*movdf_insn_sp64"): Likewise. ("*zero_extendsidi2_insn_sp64"): Likewise. ("*sign_extendsidi2_insn"): Likewise. ("*mov<VM32:mode>_insn"): Likewise. ("*mov<VM64:mode>_insn_sp64"): Likewise. ("*mov<VM64:mode>_insn_sp32"): Likewise. ("<plusminus_insn><VADDSUB:mode>3"): Likewise. ("<vlop:code><VL:mode>3"): Likewise. ("*not_<vlop:code><VL:mode>3"): Likewise. ("*nand<VL:mode>_vis"): Likewise. ("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise. ("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise. ("one_cmpl<VL:mode>2"): Likewise. ("faligndata<VM64:mode>_vis"): Likewise. ("alignaddrsi_vis"): Likewise. ("alignaddrdi_vis"): Likweise. ("alignaddrlsi_vis"): Likewise. ("alignaddrldi_vis"): Likewise. ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. ("bmaskdi_vis"): Likewise. ("bmasksi_vis"): Likewise. ("bshuffle<VM64:mode>_vis"): Likewise. ("cmask8<P:mode>_vis"): Likewise. ("cmask16<P:mode>_vis"): Likewise. ("cmask32<P:mode>_vis"): Likewise. ("pdistn<P:mode>_vis"): Likewise. ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. * config/sparc/sparc.md ("subtype"): New insn attribute. ("*wrgsr_sp64"): Set insn subtype. ("*rdgsr_sp64"): Likewise. ("alignaddrsi_vis"): Likewise. ("alignaddrdi_vis"): Likewise. ("alignaddrlsi_vis"): Likewise. ("alignaddrldi_vis"): Likewise. ("<plusminus_insn><VADDSUB:mode>3"): Likewise. ("fexpand_vis"): Likewise. ("fpmerge_vis"): Likewise. ("faligndata<VM64:mode>_vis"): Likewise. ("bshuffle<VM64:mode>_vis"): Likewise. ("cmask8<P:mode>_vis"): Likewise. ("cmask16<P:mode>_vis"): Likewise. ("cmask32<P:mode>_vis"): Likewise. ("fchksm16_vis"): Likewise. ("v<vis3_shift_patname><GCM:mode>3"): Likewise. ("fmean16_vis"): Likewise. ("fp<plusminus_insn>64_vis"): Likewise. ("<plusminus_insn>v8qi3"): Likewise. ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. ("<vis4_minmax_patname><VMMAX:mode>3"): Likewise. ("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise. ("<vis3_addsub_ss_patname>v8qi3"): Likewise. ("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise. ("*movqi_insn"): Likewise. ("*movhi_insn"): Likewise. ("*movsi_insn"): Likewise. ("movsi_pic_gotdata_op"): Likewise. ("*movdi_insn_sp32"): Likewise. ("*movdi_insn_sp64"): Likewise. ("movdi_pic_gotdata_op"): Likewise. ("*movsf_insn"): Likewise. ("*movdf_insn_sp32"): Likewise. ("*movdf_insn_sp64"): Likewise. ("*zero_extendhisi2_insn"): Likewise. ("*zero_extendqihi2_insn"): Likewise. ("*zero_extendqisi2_insn"): Likewise. ("*zero_extendqidi2_insn"): Likewise. ("*zero_extendhidi2_insn"): Likewise. ("*zero_extendsidi2_insn_sp64"): Likewise. ("ldfsr"): Likewise. ("prefetch_64"): Likewise. ("prefetch_32"): Likewise. ("tie_ld32"): Likewise. ("tie_ld64"): Likewise. ("*tldo_ldub_sp32"): Likewise. ("*tldo_ldub1_sp32"): Likewise. ("*tldo_ldub2_sp32"): Likewise. ("*tldo_ldub_sp64"): Likewise. ("*tldo_ldub1_sp64"): Likewise. ("*tldo_ldub2_sp64"): Likewise. ("*tldo_ldub3_sp64"): Likewise. ("*tldo_lduh_sp32"): Likewise. ("*tldo_lduh1_sp32"): Likewise. ("*tldo_lduh_sp64"): Likewise. ("*tldo_lduh1_sp64"): Likewise. ("*tldo_lduh2_sp64"): Likewise. ("*tldo_lduw_sp32"): Likewise. ("*tldo_lduw_sp64"): Likewise. ("*tldo_lduw1_sp64"): Likewise. ("*tldo_ldx_sp64"): Likewise. ("*mov<VM32:mode>_insn"): Likewise. ("*mov<VM64:mode>_insn_sp64"): Likewise. ("*mov<VM64:mode>_insn_sp32"): Likewise. * config/sparc/sparc.md ("type"): New insn type viscmp. ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to viscmp. ("fpcmp<gcond:code>8<P:mode>_vis"): Likewise. ("fucmp<gcond:code>8<P:mode>_vis"): Likewise. ("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. * config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle viscmp. ("n7_vis_logical_11cycle"): Likewise. * config/sparc/niagara4.md ("n4_vis_logical"): Likewise. * config/sparc/niagara2.md ("niag3_vis": Likewise. * config/sparc/niagara.md ("niag_vis"): Likewise. * config/sparc/ultra3.md ("us3_fga"): Likewise. * config/sparc/ultra1_2.md ("us1_fga_double"): Likewise. * config/sparc/sparc.md: New instruction type `bmask'. (bmaskdi_vis): Use the `bmask' type. (bmasksi_vis): Likewise. * config/sparc/ultra3.md (us3_array): Likewise. * config/sparc/niagara7.md (n7_array): Likewise. * config/sparc/niagara4.md (n4_array): Likewise. * config/sparc/niagara2.md (niag2_vis): Likewise. (niag3_vis): Likewise. * config/sparc/niagara.md (niag_vis): Likewise. gcc/testsuite/ChangeLog: * gcc.target/sparc/dictunpack.c: New file. * gcc.target/sparc/fpcmpdeshl.c: Likewise. * gcc.target/sparc/fpcmpshl.c: Likewise. * gcc.target/sparc/fpcmpurshl.c: Likewise. * gcc.target/sparc/fpcmpushl.c: Likewise. From-SVN: r250049
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r243994
2016-06-06sparc: support for the SPARC M7 and VIS 4.0Jose E. Marchesi1-0/+1
gcc/ChangeLog: 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> * config/sparc/sparc.md (cpu): Add niagara7 cpu type. Include the M7 SPARC DFA scheduler. New attribute v3pipe. Annotate insns with v3pipe where appropriate. Define cpu_feature vis4. Add lzd instruction type and set it on clzdi_sp64 and clzsi_sp64. Add (V8QI "8") to vbits. Add insns {add,sub}v8qi3 Add insns ss{add,sub}v8qi3 Add insns us{add,sub}{v8qi,v4hi}3 Add insns {min,max}{v8qi,v4hi,v2si}3 Add insns {minu,maxu}{v8qi,v4hi,v2si}3 Add insns fpcmp{le,gt,ule,ug,ule,ugt}{8,16,32}_vis. * config/sparc/niagara4.md: Add a comment explaining the discrepancy between the documented latenty numbers and the implemented ones. * config/sparc/niagara7.md: New file. * configure.ac (HAVE_AS_SPARC5_VIS4): Define if the assembler supports SPARC5 and VIS 4.0 instructions. * configure: Regenerate. * config.in: Likewise. * config.gcc: niagara7 is a supported cpu in sparc*-*-* targets. * config/sparc/sol2.h (ASM_CPU32_DEFAUILT_SPEC): Set for TARGET_CPU_niagara7. (ASM_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle niagara7. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc-opts.h (processor_type): Add PROCESSOR_NIAGARA7. (mvis4): New option. * config/sparc/sparc.h (TARGET_CPU_niagara7): Define. (AS_NIAGARA7_FLAG): Define. (ASM_CPU64_DEFAULT_SPEC): Set for niagara7. (CPP_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle niagara7. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (niagara7_costs): Define. (sparc_option_override): Handle niagara7 and adjust cache-related parameters with better values for niagara cpus. Also support VIS4. (sparc32_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. (dump_target_flag_bits): Support VIS4. (sparc_vis_init_builtins): Likewise. (sparc_builtins): Likewise. * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ for VIS4 4.0. * config/sparc/driver-sparc.c (cpu_names): Add SPARC-M7 and UltraSparc M7. * config/sparc/sparc.opt (sparc_processor_type): New value niagara7. * config/sparc/visintrin.h (__attribute__): Prototypes for the VIS4 builtins. * doc/invoke.texi (SPARC Options): Document -mcpu=niagara7 and -mvis4. * doc/extend.texi (SPARC VIS Built-in Functions): Document the VIS4 builtins. gcc/testsuite/ChangeLog: 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> * gcc.target/sparc/vis4misc.c: New file. * gcc.target/sparc/fpcmp.c: Likewise. * gcc.target/sparc/fpcmpu.c: Likewise. From-SVN: r237132
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r232055
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r219188
2014-10-24config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor.Daniel Hellstrom1-0/+1
2014-10-24 Daniel Hellstrom <daniel@gaisler.com> * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor. * doc/invoke.texi (SPARC options): Add mcpu=leon3v7 comment. * config/sparc/leon.md (leon3_load, leon_store, leon_fp_*): Handle leon3v7 as leon3. * config/sparc/sparc-opts.h (enum processor_type): Add LEON3V7. * config/sparc/sparc.c (sparc_option_override): Add leon3v7 support. * config/sparc/sparc.h (TARGET_CPU_leon3v7): New define. * config/sparc/sparc.md (cpu): Add leon3v7. * config/sparc/sparc.opt (enum processor_type): Add leon3v7. From-SVN: r216666
2014-01-02Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r206289
2013-07-22config.gcc (sparc*-*-*): Accept leon3 processor.Eric Botcazou1-0/+1
* config.gcc (sparc*-*-*): Accept leon3 processor. (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support. * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry. * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3. * config/sparc/sparc.opt (enum processor_type): Add leon3. (mfix-ut699): Adjust comment. * config/sparc/sparc.h (TARGET_CPU_leon3): New define. (CPP_CPU32_DEFAULT_SPEC): Add leon3 support. (CPP_CPU_SPEC): Likewise. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (leon3_cost): New constant. (sparc_option_override): Add leon3 support. (mem_ref): New function. (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled. (sparc_do_work_around_errata): Look into the instruction in the delay slot and adjust accordingly. Add fix for the data cache nullify issues of the UT699. Change insertion position for the NOP. * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete. (leon3_load): New reservation. (leon_store): Bump latency to 2. (grfpu): New automaton. (grfpu_alu): New unit. (grfpu_ds): Likewise. (leon_fp_alu): Adjust. (leon_fp_mult): Delete. (leon_fp_div): Split into leon_fp_divs and leon_fp_divd. (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd. * config/sparc/sparc.md (cpu): Add leon3. * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699. (swapsi): Likewise. (atomic_test_and_set): Likewise. (ldstub): Likewise. From-SVN: r201147
2013-01-10Update copyright years in gcc/Richard Sandiford1-2/+1
From-SVN: r195098
2011-11-30sparc: Add -mmemory-model command-line option.Richard Henderson1-0/+10
* config/sparc/sparc-opts.h (enum sparc_memory_model_type): New. * config/sparc/sparc.opt (mmemory-model=): New option. * doc/invoke.texi (Sparc Options): Document it. * config/sparc/sparc.c (sparc_option_override): Provide default for sparc_memory_model. (sparc_emit_membar_for_model): Omit barrier combinations that are implied by the memory model. From-SVN: r181853
2011-09-05sparc-opts.h (PROCESSOR_NIAGARA3, [...]): New.David S. Miller1-0/+2
* config/sparc/sparc-opts.h (PROCESSOR_NIAGARA3, PROCESSOR_NIAGARA4): New. * config/sparc/sparc.opt: Handle new processor types. * config/sparc/sparc.md: Add to "cpu" attribute. * config/sparc/sparc.h (TARGET_CPU_niagara3, TARGET_CPU_niagara4): New, treat as niagara2. * config/sparc/linux64.h: Handle niagara3 and niagara4 like niagara2. * config/sparc/sol2.h: Likewise. * config/sparc/niagara2.md: Schedule niagara3 like niagara2. * config/sparc/sparc.c (sparc_option_override): Add niagara3 and niagara4 handling. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. * config/sparc/driver-sparc.c (cpu_names): Use niagara3 and niagara4 as appropriate. * doc/invoke.texi: Document new processor types. From-SVN: r178554
2011-08-08driver-sparc.c: New file.Rainer Orth1-1/+2
gcc: * config/sparc/driver-sparc.c: New file. * config/sparc/x-sparc: New file. * config.host: Use driver-sparc.o, sparc/x-sparc on sparc*-*-solaris2*. * config/sparc/sparc.opt (native): New value for enum processor_type. * config/sparc/sparc-opts.h (PROCESSOR_NATIVE): Declare. * config/sparc/sparc.c (sparc_option_override): Abort if PROCESSOR_NATIVE gets here. * config/sparc/sol2.h [__sparc__] (host_detect_local_cpu): Declare. (EXTRA_SPEC_FUNCTIONS, MCPU_MTUNE_NATIVE_SPECS, DRIVER_SELF_SPECS): Define. * doc/invoke.texi (SPARC Options, -mcpu): Document native. (SPARC Options, -mtune): Likewise. * configure.ac (EXTRA_GCC_LIBS): Check for libkstat. Substitute result. * configure: Regenerate. * Makefile.in (EXTRA_GCC_LIBS): Set. (xgcc$(exeext)): Add $(EXTRA_GCC_LIBS). (cpp$(exeext)): Likewise. gcc/cp: * Make-lang.in (g++$(exeext)): Add $(EXTRA_GCC_LIBS). gcc/fortran: * Make-lang.in (gfortran$(exeext)): Add $(EXTRA_GCC_LIBS). gcc/go: * Make-lang.in (gccgo$(exeext)): Add $(EXTRA_GCC_LIBS). gcc/java: * Make-lang.in ($(XGCJ)$(exeext)): Add $(EXTRA_GCC_LIBS). From-SVN: r177559
2011-03-28sparc-opts.h: New.Joseph Myers1-0/+47
* config/sparc/sparc-opts.h: New. * config/sparc/sparc.c (sparc_handle_option, sparc_select, sparc_cpu, fpu_option_set, TARGET_HANDLE_OPTION): Remove. (sparc_option_override): Store processor_type enumeration rather than string in cpu_default. Remove name and enumeration from cpu_table. Directly default -mcpu then default -mtune from -mcpu without using sparc_select. Use target_flags_explicit instead of fpu_option_set. * config/sparc/sparc.h (enum processor_type): Move to sparc-opts.h. (sparc_cpu, struct sparc_cpu_select, sparc_select): Remove. * config/sparc/sparc.opt (config/sparc/sparc-opts.h): New HeaderInclude entry. (mcpu=, mtune=): Use Var and Enum. (sparc_processor_type): New Enum and EnumValue entries. From-SVN: r171601
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