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AgeCommit message (Expand)AuthorFilesLines
2023-06-23Fix power10 fusion bug with prefixed loads, PR target/105325Michael Meissner1-2/+2
2023-04-11rs6000: correct vector sign extend builtins on Big EndianHaochen Gui1-3/+3
2023-03-23Don't force target of modulo into a distinct register.Pat Haugen1-6/+6
2023-02-20powerpc: Another umaddditi4 fix [PR108862]Jakub Jelinek1-2/+2
2023-02-15powerpc: Fix up expansion for WIDEN_MULT_PLUS_EXPR [PR108787]Jakub Jelinek1-9/+24
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-20rs6000: Optimize cmp on rotated 16bits constantJiufu Guo1-1/+65
2022-12-13rs6000: enable cbranchcc4Haochen Gui1-0/+10
2022-12-08rs6000: Update sign extension computation with sext_hwiJiufu Guo1-5/+5
2022-10-25rs6000: Add CCANY; replace <un>signed by <mode:CCANY>Segher Boessenkool1-16/+15
2022-09-08rs6000: allow constant splitter run in split1 passJiufu Guo1-2/+2
2022-09-07rs6000: remove unused splitter on const_scalar_int_operandJiufu Guo1-12/+0
2022-09-07rs6000: fix misleading new patterns of splittersJiufu Guo1-9/+3
2022-08-18rs6000: Add expand pattern for multiply-add (PR103109)Haochen Gui1-1/+47
2022-06-27rs6000: Simplify *rotl<mode>3_insert_4 by removing DImodeKewen Lin1-17/+8
2022-06-22PR target/105991: Recognize PLUS and XOR forms of rldimi in rs6000.md.Roger Sayle1-1/+20
2022-06-09rs6000: Delete FP_ISA3Segher Boessenkool1-17/+14
2022-06-09This patch replaces shift and ior insns with one rotate and mask insn for the...Haochen Gui1-6/+6
2022-05-18This patch adds a combine pattern for "CA minus one". The SImode "CA minus on...Haochen Gui1-0/+13
2022-05-11rs6000: Remove <Fv>Segher Boessenkool1-52/+46
2022-05-11rs6000: Remove <Ff>Segher Boessenkool1-60/+57
2022-04-22rs6000: Fix pack for soft-float (PR105334)Segher Boessenkool1-2/+43
2022-04-21rs6000: Disparage lfiwzx and similarSegher Boessenkool1-11/+11
2022-04-11rs6000: Fix unpack for no-direct-move (PR103623)Segher Boessenkool1-4/+4
2022-01-24rtl: builtins: (not just) rs6000: Add builtins for fegetround, feclearexcept ...Raoni Fassina Firmino1-0/+111
2022-01-21Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136Michael Meissner1-8/+16
2022-01-17Change references of .c files to .cc filesMartin Liska1-1/+1
2022-01-11rs6000: powerpc suboptimal boolean test of contiguous bits [PR102239]Xionghu Luo1-0/+38
2022-01-07rs6000: Define a pattern for mffscrni. If the RN is a constant, it can call ...Haochen Gui1-5/+19
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-17rs6000: Redo darn (PR103624)Segher Boessenkool1-19/+28
2021-12-15Generate XXSPLTIDP for scalars on power10.Michael Meissner1-18/+79
2021-12-15Generate XXSPLTIW on power10.Michael Meissner1-0/+5
2021-09-06rs6000: Expand fmod and remainder when built with fast-math [PR97142]Xionghu Luo1-0/+36
2021-07-23Fix execution failure of parity_1.f90 on P10 [PR100952]Haochen Gui1-1/+4
2021-07-07Generate 128-bit int divide/modulus on power10.Michael Meissner1-0/+34
2021-07-01Add IEEE 128-bit fp conditional move on PowerPC.Michael Meissner1-0/+106
2021-06-17Add IEEE 128-bit min/max support on PowerPC.Michael Meissner1-0/+11
2021-06-11rs6000: Support more short/char to float conversionKewen Lin1-0/+21
2021-06-09Conversions between 128-bit integer and floating point values.Carl Love1-0/+36
2021-05-21Add insn types for fusion pairsAaron Sawdey1-1/+19
2021-05-15rs6000: Emit ROP-mitigation instructions in prologue and epilogueBill Schmidt1-0/+31
2021-03-31Update prefixed attribute for Power10.Pat Haugen1-6/+13
2021-03-21rs6000: Fix some unexpected empty split conditionsKewen Lin1-14/+14
2021-03-03Update size attribute for Power10.Pat Haugen1-1/+2
2021-03-02aix: Fix TLS thread pointer function names.David Edelsohn1-2/+2
2021-02-25Optimize pcrel access of globalsAaron Sawdey1-1/+7
2021-02-22rs6000: Use rldimi for vec init instead of shift + iorKewen Lin1-1/+19
2021-01-27Combine patterns for p10 load-cmpi fusionAaron Sawdey1-0/+1
2021-01-15rs6000, vector integer multiply/divide/modulo instructionsCarl Love1-2/+3
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