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path: root/gcc/config/rs6000/altivec.md
AgeCommit message (Expand)AuthorFilesLines
2024-07-02rs6000: Fix wrong RTL patterns for vector merge high/low short on LEKewen Lin1-23/+53
2024-07-02rs6000: Fix wrong RTL patterns for vector merge high/low char on LEKewen Lin1-14/+52
2024-06-27rs6000: Fix wrong RTL patterns for vector merge high/low word on LEKewen Lin1-24/+56
2023-05-09rs6000: Fix predicate for const vector in sldoi_to_mov [PR109069]Kewen Lin1-3/+11
2023-04-04rs6000: Fix vector parity support [PR108699]Kewen Lin1-3/+5
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-11-02rs6000: Byte reverse V8HI on Power8 by vector rotation.Xionghu Luo1-1/+1
2022-07-21[PATCH, rs6000] Cleanup some vstrir define_expand naming inconsistenciesWill Schmidt1-13/+13
2022-01-16rs6000: Use known constant for GET_MODE_NUNITS and similarKewen Lin1-25/+0
2022-01-12rs6000: Add split pattern to replaceXionghu Luo1-0/+11
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-20rs6000: Replace UNSPECS with ss_plus/us_plus and ss_minus/us_minusXionghu Luo1-19/+10
2021-11-23rs6000: Optimize code generation of vec_reve [PR100868]Haochen Gui1-2/+44
2021-10-27rs6000: Fold xxsel to vsel since they have same semanticsXionghu Luo1-24/+36
2021-10-27rs6000: Fix wrong code generation for vec_sel [PR94613]Xionghu Luo1-16/+46
2021-10-19rs6000: Remove unspecs for vec_mrghl[bhw]Xionghu Luo1-145/+58
2021-08-24rs6000: Add vec_unpacku_{hi,lo}_v4siKewen Lin1-129/+29
2021-08-20Move xx* builtins to vsx.md.Michael Meissner1-197/+0
2021-08-13Fix xxeval predicates (PR 99921).Michael Meissner1-3/+3
2021-07-20rs6000: Fix up easy_vector_constant_msb handling [PR101384]Jakub Jelinek1-4/+15
2021-07-12Change rs6000_const_f32_to_i32 return type.Michael Meissner1-1/+1
2021-06-09RS6000 Add 128-bit Binary Integer sign extend operationsCarl Love1-0/+24
2021-06-09rs6000, Add test 128-bit shifts for just the int128 type.Carl Love1-8/+8
2021-06-09RS6000 add 128-bit Integer Operations part 1Carl Love1-0/+241
2021-06-09rs6000, Fix arguments in altivec_vrlwmi and altivec_rlwdi builtinsCarl Love1-3/+3
2021-03-31Update prefixed attribute for Power10.Pat Haugen1-8/+16
2021-03-30rs6000: Enable 32bit variable vec_insert [PR99718]luoxhu@cn.ibm.com1-4/+4
2021-01-15rs6000, vector integer multiply/divide/modulo instructionsCarl Love1-2/+0
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-11-02Add bcd builtings listed in appendix B of the ABICarl Love1-17/+87
2020-08-04rs6000 Add vector blend, permute builtin supportCarl Love1-0/+71
2020-08-04rs6000, Add vector splat builtin supportCarl Love1-0/+106
2020-08-04rs6000, Add vector shift double builtin supportCarl Love1-0/+18
2020-08-04rs6000, Update support for vec_extractCarl Love1-64/+0
2020-07-08[PATCH, rs6000]Add support to enable vmsumudm behind vec_msum builtin.Will Schmidt1-0/+11
2020-06-24[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtinWill Schmidt1-0/+34
2020-06-22rs6000: Rename future to power10Segher Boessenkool1-21/+21
2020-05-29rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg)Segher Boessenkool1-52/+52
2020-05-13rs6000: Add vec_extracth and vec_extractlKelvin Nilsen1-0/+62
2020-05-11rs6000: Vector string isolate instructionsKelvin Nilsen1-0/+105
2020-05-11rs6000: Add xxeval and vec_ternarylogicKelvin Nilsen1-0/+11
2020-05-11rs6000: Add vclrlb and vclrrbKelvin Nilsen1-0/+29
2020-05-11rs6000: Add vcfuged instructionKelvin Nilsen1-0/+10
2020-05-11rs6000: Add vgnbKelvin Nilsen1-0/+10
2020-05-11rs6000: Add vector pdep/pextKelvin Nilsen1-0/+20
2020-05-11rs6000: Add vector count under maskKelvin Nilsen1-0/+21
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-10-24rs6000: Implement [u]avg<mode>3_ceilSegher Boessenkool1-2/+2
2019-09-23Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823)Richard Sandiford1-7/+2
2019-08-22rs6000: Move various non-vector things out of altivec.mdSegher Boessenkool1-223/+0
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