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The patch optimizes code generation for comparisons of the form
X & C1 == C2 by converting them to (X | ~C1) == (C2 | ~C1).
C1 is a constant that requires li and addi to be loaded,
while ~C1 requires a single lui instruction.
As the values of C1 and C2 are not visible within
the equality expression, a plus pattern is matched instead.
PR target/114087
gcc/ChangeLog:
* config/riscv/riscv.md (*lui_constraint<ANYI:mode>_and_to_or): New pattern
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr114087-1.c: New test.
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This adds the Tenstorrent Ascalon 8 wide architecture (tt-ascalon-d8)
to the list of known cores.
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add tt-ascalon-d8.
* config/riscv/riscv.cc (tt_ascalon_d8_tune_info): New.
* doc/invoke.texi (RISC-V): Add tt-ascalon-d8 to -mcpu.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-tt-ascalon-d8.c: New test.
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Although this constraint is not currently used for any instructions, it is very
useful for custom instructions. Additionally, some new standard extensions
(not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this
constraint. Therefore, I believe there is sufficient justification to add it
now.
gcc/ChangeLog:
* config/riscv/constraints.md (R): New constraint.
* doc/md.texi: Document new constraint `R`.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/constraint-R.c: New.
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register name
The modifier `N`, to print the raw encoding of a register. This is used
when using `.insn <length>, <encoding>`, where the user wants to pass
a value to the instruction in a known register, but where the
instruction doesn't follow the existing instruction formats, so the
assembly parser is not expecting a register name, just a raw integer.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Add N.
* doc/extend.texi: Document for N,
gcc/testsuite/ChangeLog:
* gcc.target/riscv/modifier-N-fpr.c: New.
* gcc.target/riscv/modifier-N-vr.c: New.
* gcc.target/riscv/modifier-N.c: New.
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Here is a purposal that using N for printing register encoding number,
so let rename the existing internal operand modifier `N` to `n`.
gcc/ChangeLog:
* config/riscv/corev.md (*cv_branch<mode>): Update modifier.
(*branch<mode>): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Update modifier.
* config/riscv/riscv.md (*branch<mode>): Update modifier.
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gcc/ChangeLog:
* config/riscv/constraints.md (cr): New.
(cf): New.
* config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and
RVC_FP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* doc/md.texi: Document cr and cf constraint.
* config/riscv/riscv.cc (riscv_regno_to_class): Update
FP_REGS to RVC_FP_REGS since it smaller set.
(riscv_secondary_memory_needed): Handle RVC_FP_REGS.
(riscv_register_move_cost): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/constraint-cf-zfinx.c: New.
* gcc.target/riscv/constraint-cf.c: New.
* gcc.target/riscv/constraint-cr.c: New.
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Rename those constraint since we want define other constraint start with
`c`, those constraints are internal and undocumented, so it's fine to
rename.
gcc/ChangeLog:
* config/riscv/constraints.md (c01): Rename to...
(k01): ...this.
(c02): Rename to...
(k02): ...this.
(c03): Rename to...
(k03): ...this.
(c04): Rename to...
(k04): ...this.
(c08): Rename to...
(k08): ...this.
* config/riscv/corev.md (riscv_cv_simd_add_h_si): Update
constraints.
(riscv_cv_simd_sub_h_si): Ditto.
(riscv_cv_simd_cplxmul_i_si): Ditto.
(riscv_cv_simd_subrotmj_si): Ditto.
* config/riscv/riscv-v.cc (splat_to_scalar_move_p): Update
constraints.
* config/riscv/vector-iterators.md (stride_load_constraint):
Update constraints.
(stride_store_constraint): Ditto.
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PR112694 shows that we try to create sub-vectors of single-element
vectors because can_duplicate_and_interleave_p returns true.
The problem resurfaced in PR116611.
This patch makes can_duplicate_and_interleave_p return false
if count / nvectors > 0 and removes the corresponding check in the riscv
backend.
This partially gets rid of the FAIL in slp-19a.c. At least when built
with cost model we don't have LOAD_LANES anymore. Without cost model,
as in the test suite, we choose a different path and still end up with
LOAD_LANES.
Bootstrapped and regtested on x86 and power10, regtested on
rv64gcv_zvfh_zvbb. Still waiting for the aarch64 results.
Regards
Robin
gcc/ChangeLog:
PR target/112694
PR target/116611.
* config/riscv/riscv-v.cc (expand_vec_perm_const): Remove early
return.
* tree-vect-slp.cc (can_duplicate_and_interleave_p): Return
false when we cannot create sub-elements.
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This patch makes vcompress use the tail-undisturbed policy by default
and also uses the proper VL.
PR target/117383
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum insn_type): Use TU policy.
* config/riscv/riscv-v.cc (shuffle_compress_patterns): Set VL.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c:
Expect tu.
* gcc.target/riscv/rvv/autovec/pr117383.c: New test.
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For a generic vec_construct from scalar elements we need to load each
scalar element and move it over to a vector register.
Right now we only use a cost of 1 per element.
This patch uses register-move cost as well as scalar_to_vec and
multiplies it with the number of elements in the vector instead.
PR target/118019
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_builtin_vectorization_cost):
Increase vec_construct cost.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr118019.c: New test.
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This patch adds a second variant to implement the extract/slide1up
pattern. In order to do a permutation like
<3, 4, 5, 6> from vectors <0, 1, 2, 3> and <4, 5, 6, 7>
we currently extract <3> from the first vector and re-insert it into the
second vector. Unless register-file crossing latency is essentially
zero it should be preferable to first slide the second vector up by
one, then slide down the first vector by (nunits - 1).
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_register_move_cost):
Export.
* config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns):
Rename...
(shuffle_off_by_one_patterns): ... to this and add slideup/slidedown
variant.
(expand_vec_perm_const_1): Call renamed function.
* config/riscv/riscv.cc (riscv_secondary_memory_needed): Remove
static.
(riscv_register_move_cost): Add VR<->GR/FR handling.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112599-2.c: Adjust test
expectation.
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This adds handling for even/odd patterns.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_even_odd_patterns): New
function.
(expand_vec_perm_const_1): Use new function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd-run.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd.c: New test.
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This patch adds efficient handling of interleaving patterns like
[0 4 1 5] to vec_perm_const. It is implemented by a slideup and a
gather.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_interleave_patterns): New
function.
(expand_vec_perm_const_1): Use new function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave.c: New test.
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This patch adds a shuffle_slide_patterns to expand_vec_perm_const.
It recognizes permutations like
{0, 1, 4, 5}
or
{2, 3, 6, 7}
which can be constructed by a slideup or slidedown of one of the vectors
into the other one.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_slide_patterns): New.
(expand_vec_perm_const_1): Call new function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide-run.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide.c: New test.
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In PR117353 and PR117878 we expand a const vector during reload. For
this we use an unpredicated left shift. Normally an insn like this is
split but as we introduce it late and cannot create pseudos anymore
it remains unpredicated and is not recognized by the vsetvl pass (where
we expect all insns to be in predicated RVV format).
This patch directly emits a predicated shift instead. We could
distinguish between !lra_in_progress and lra_in_progress and emit
an unpredicated shift in the former case but we're not very likely
to optimize it anyway so it doesn't seem worth it.
PR target/117353
PR target/117878
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use predicated
instead of simple shift.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr117353.c: New test.
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The vector strided load doesn't include the (mem:BLK (scratch)) to
alias all other memories. It will make the alias analysis only
consider the base address of strided load and promopt the store
before the strided load. For example as below
#define STEP 10
char d[225];
int e[STEP];
int main() {
// store 0, 10, 20, 30, 40, 50, 60, 70, 80, 90
for (long h = 0; h < STEP; ++h)
d[h * STEP] = 9;
// load 30, 40, 50, 60, 70, 80, 90
// store 3, 4, 5, 6, 7, 8, 9
for (int h = 3; h < STEP; h += 1)
e[h] = d[h * STEP];
if (e[5] != 9) {
__builtin_abort ();
}
return 0;
}
The asm dump will be:
main:
lui a5,%hi(.LANCHOR0)
addi a5,a5,%lo(.LANCHOR0)
li a4,9
sb a4,30(a5)
addi a3,a5,30
vsetivli zero,7,e32,m1,ta,ma
li a2,10
vlse8.v v2,0(a3),a2 // depends on 30(a5), 40(a5), ... 90(a5) but
// only 30(a5) has been promoted before vlse.
// It is store after load mistake.
addi a3,a5,252
sb a4,0(a5)
sb a4,10(a5)
sb a4,20(a5)
sb a4,40(a5)
vzext.vf4 v1,v2
sb a4,50(a5)
sb a4,60(a5)
vse32.v v1,0(a3)
li a0,0
sb a4,70(a5)
sb a4,80(a5)
sb a4,90(a5)
lw a5,260(a5)
beq a5,a4,.L4
li a0,123
After this patch:
main:
vsetivli zero,4,e32,m1,ta,ma
vmv.v.i v1,9
lui a5,%hi(.LANCHOR0)
addi a5,a5,%lo(.LANCHOR0)
addi a4,a5,244
vse32.v v1,0(a4)
li a4,9
sb a4,0(a5)
sb a4,10(a5)
sb a4,20(a5)
sb a4,30(a5)
sb a4,40(a5)
sb a4,50(a5)
sb a4,60(a5)
sb a4,70(a5)
sb a4,80(a5)
sb a4,90(a5)
vsetivli zero,3,e32,m1,ta,ma
addi a4,a5,70
li a3,10
vlse8.v v2,0(a4),a3
addi a5,a5,260
li a0,0
vzext.vf4 v1,v2
vse32.v v1,0(a5)
ret
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
PR target/117990
gcc/ChangeLog:
* config/riscv/vector.md: Add the (mem:BLK (scratch)) to the
vector strided load.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr117990-run-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
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This commit newly introduces the ability to use overloaded builtins in
C++ SFINAE context.
The goal behind this is in order to ensure there is a single mechanism
that libstdc++ can use to determine whether a given type can be used in
the atomic fetch_add (and similar) builtins. I am working on another
patch that hopes to use this mechanism to identify whether fetch_add
(and similar) work on floating point types.
Current state of the world:
GCC currently exposes resolved versions of these builtins to the
user, so for GCC it's currently possible to use tests similar to the
below to check for atomic loads on a 2 byte sized object.
#if __has_builtin(__atomic_load_2)
Clang does not expose resolved versions of the atomic builtins.
clang currently allows SFINAE on builtins, so that C++ code can
check whether a builtin is available on a given type.
GCC does not (and that is what this patch aims to change).
C libraries like libatomic can check whether a given atomic builtin
can work on a given type by using autoconf to check for a
miscompilation when attempting such a use.
My goal:
I would like to enable floating point fetch_add (and similar) in
GCC, in order to use those overloads in libstdc++ implementation of
atomic<float>::fetch_add.
This should allow compilers targeting GPU's which have floating
point fetch_add instructions to emit optimal code.
In order to do that I need some consistent mechanism that libstdc++
can use to identify whether the fetch_add builtins have floating
point overloads (and for which types these exist).
I would hence like to enable SFINAE on builtins, so that libstdc++
can use that mechanism for the floating point fetch_add builtins.
Implementation follows the existing mechanism for handling SFINAE
contexts in c-common.cc. A boolean is passed into the c-common.cc
function indicating whether these functions should emit errors or not.
This boolean comes from `complain & tf_error` in the C++ frontend.
(Similar to other functions like valid_array_size_p and
c_build_vec_perm_expr).
This is done both for resolve_overloaded_builtin and
check_builtin_function_arguments, both of which can be used in SFINAE
contexts.
I attempted to trigger something using the `reject_gcc_builtin`
function in an SFINAE context. Given the context where this
function is called from the C++ frontend it looks like it may be
possible, but I did not manage to trigger this in template context
by attempting to do something similar to the testcases added around
those calls.
- I would appreciate any feedback on whether this is something that
can happen in a template context, and if so some help writing a
relevant testcase for it.
Both of these functions have target hooks for target specific builtins
that I have updated to take the extra boolean flag. I have not adjusted
the functions implementing those target hooks (except to update the
declarations) so target specific builtins will still error in SFINAE
contexts.
- I could imagine not updating the target hook definition since nothing
would use that change. However I figure that allowing targets to
decide this behaviour would be the right thing to do eventually, and
since this is the target-independent part of the change to do that
this patch should make that change.
Could adjust if others disagree.
Other relevant points that I'd appreciate reviewers check:
- I did not pass this new flag through
atomic_bitint_fetch_using_cas_loop since the _BitInt type is not
available in the C++ frontend and I didn't want if conditions that can
not be executed in the source.
- I only test non-compile-time-constant types with SVE types, since I do
not know of a way to get a VLA into a SFINAE context.
- While writing tests I noticed a few differences with clang in this
area. I don't think they are problematic but am mentioning them for
completeness and to allow others to judge if these are a problem).
- atomic_fetch_add on a boolean is allowed by clang.
- When __atomic_load is passed an invalid memory model (i.e. too
large), we give an SFINAE failure while clang does not.
Bootstrap and regression tested on AArch64 and x86_64.
Built first stage on targets whose target hook declaration needed
updated (though did not regtest etc). Targets triplets I built in order
to check the backend specific changes I made:
- arm-none-linux-gnueabihf
- avr-linux-gnu
- riscv-linux-gnu
- powerpc-linux-gnu
- s390x-linux-gnu
Ok for commit to trunk?
gcc/c-family/ChangeLog:
* c-common.cc (builtin_function_validate_nargs,
check_builtin_function_arguments,
speculation_safe_value_resolve_call,
speculation_safe_value_resolve_params, sync_resolve_size,
sync_resolve_params, get_atomic_generic_size,
resolve_overloaded_atomic_exchange,
resolve_overloaded_atomic_compare_exchange,
resolve_overloaded_atomic_load, resolve_overloaded_atomic_store,
resolve_overloaded_builtin): Add `complain` boolean parameter
and determine whether to emit errors based on its value.
* c-common.h (check_builtin_function_arguments,
resolve_overloaded_builtin): Mention `complain` boolean
parameter in declarations. Give it a default of `true`.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc
(aarch64_resolve_overloaded_builtin,aarch64_check_builtin_call):
Add new unused boolean parameter to match target hook
definition.
* config/arm/arm-builtins.cc (arm_check_builtin_call): Likewise.
* config/arm/arm-c.cc (arm_resolve_overloaded_builtin):
Likewise.
* config/arm/arm-protos.h (arm_check_builtin_call): Likewise.
* config/avr/avr-c.cc (avr_resolve_overloaded_builtin):
Likewise.
* config/riscv/riscv-c.cc (riscv_check_builtin_call,
riscv_resolve_overloaded_builtin): Likewise.
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
Likewise.
* config/rs6000/rs6000-protos.h (altivec_resolve_overloaded_builtin):
Likewise.
* config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
Likewise.
* doc/tm.texi: Regenerate.
* target.def (TARGET_RESOLVE_OVERLOADED_BUILTIN,
TARGET_CHECK_BUILTIN_CALL): Update prototype to include a
boolean parameter that indicates whether errors should be
emitted. Update documentation to mention this fact.
gcc/cp/ChangeLog:
* call.cc (build_cxx_call): Pass `complain` parameter to
check_builtin_function_arguments. Take its value from the
`tsubst_flags_t` type `complain & tf_error`.
* semantics.cc (finish_call_expr): Pass `complain` parameter to
resolve_overloaded_builtin. Take its value from the
`tsubst_flags_t` type `complain & tf_error`.
gcc/testsuite/ChangeLog:
* g++.dg/template/builtin-atomic-overloads.def: New test.
* g++.dg/template/builtin-atomic-overloads1.C: New test.
* g++.dg/template/builtin-atomic-overloads2.C: New test.
* g++.dg/template/builtin-atomic-overloads3.C: New test.
* g++.dg/template/builtin-atomic-overloads4.C: New test.
* g++.dg/template/builtin-atomic-overloads5.C: New test.
* g++.dg/template/builtin-atomic-overloads6.C: New test.
* g++.dg/template/builtin-atomic-overloads7.C: New test.
* g++.dg/template/builtin-atomic-overloads8.C: New test.
* g++.dg/template/builtin-sfinae-check-function-arguments.C: New test.
* g++.dg/template/builtin-speculation-overloads.def: New test.
* g++.dg/template/builtin-speculation-overloads1.C: New test.
* g++.dg/template/builtin-speculation-overloads2.C: New test.
* g++.dg/template/builtin-speculation-overloads3.C: New test.
* g++.dg/template/builtin-speculation-overloads4.C: New test.
* g++.dg/template/builtin-speculation-overloads5.C: New test.
* g++.dg/template/builtin-validate-nargs.C: New test.
Signed-off-by: Matthew Malcomson <mmalcomson@nvidia.com>
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This reverts commit 9bf4cad4e4e1ec92c320a619c9bad35535596ced.
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This is v2 of the patch; v1 was here:
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/655541.html
Changed in v2:
* added a new TARGET_DOCUMENTATION_NAME hook for figuring out which
documentation URL to use when there are multiple per-target docs,
such as for __attribute__((interrupt)); implemented this for all
targets that have target-specific attributes
* moved attribute_urlifier and its support code to a new
gcc-attribute-urlifier.cc since it needs to use targetm for the
above; gcc-urlifier.o is used by the driver.
* fixed extend.texi so that some attributes that failed to appear in
attr-urls.def now do so (affected nvptx "kernel" and "shared" attrs)
* regenerated attr-urls.def for the above fix, and bringing in
attributes added since v1 of the patch
In r14-5118-gc5db4d8ba5f3de I added a mechanism to automatically add
documentation URLs to quoted strings in diagnostics.
In r14-6920-g9e49746da303b8 I added a mechanism to generate URLs for
mentions of command-line options in quoted strings in diagnostics.
This patch does a similar thing for attributes. It adds a new Python 3
script to scrape the generated HTML looking for documentation of
attributes, and uses this to (re)generate a new gcc/attr-urls.def file.
Running "make regenerate-attr-urls" after rebuilding the HTML docs will
regenerate gcc/attr-urls.def in the source directory.
The patch uses this to optionally add doc URLs for attributes in any
diagnostic emitted during the lifetime of a auto_urlify_attributes
instance, and adds such instances everywhere that a diagnostic refers
to a diagnostic within quotes (based on grepping the source tree
for references to attributes in strings and in code).
For example, given:
$ ./xgcc -B. -S ../../src/gcc/testsuite/gcc.dg/attr-access-2.c
../../src/gcc/testsuite/gcc.dg/attr-access-2.c:14:16: warning:
attribute ‘access(read_write, 2, 3)’ positional argument 2 conflicts
with previous designation by argument 1 [-Wattributes]
with this patch the quoted text `access(read_write, 2, 3)'
automatically gains the URL for our docs for "access":
https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-access-function-attribute
in a sufficiently modern terminal.
Like r14-6920-g9e49746da303b8 this avoids the Makefile target
depending on the generated HTML, since a missing URL is a minor
problem, whereas requiring all users to build HTML docs seems more
involved. Doing so also avoids Python 3 as a build requirement for
everyone, but instead just for developers addding attributes.
Like the options, we could add a CI test for this.
The patch gathers both general and target-specific attributes.
For example, the function attribute "interrupt" has 19 URLs within our
docs: one common, and 18 target-specific ones.
The patch adds a new target hook used when selecting the most
appropriate one.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
gcc/ChangeLog:
* Makefile.in (OBJS): Add -attribute-urlifier.o.
(ATTR_URLS_HTML_DEPS): New.
(regenerate-attr-urls): New.
(regenerate-attr-urls-unit-test): New.
* attr-urls.def: New file.
* attribs.cc: Include "gcc-urlifier.h".
(decl_attributes): Use auto_urlify_attributes.
* config/aarch64/aarch64.cc (TARGET_DOCUMENTATION_NAME): New.
* config/arc/arc.cc (TARGET_DOCUMENTATION_NAME): New.
* config/arm/arm.cc (TARGET_DOCUMENTATION_NAME): New.
* config/bfin/bfin.cc (TARGET_DOCUMENTATION_NAME): New.
* config/bpf/bpf.cc (TARGET_DOCUMENTATION_NAME): New.
* config/epiphany/epiphany.cc (TARGET_DOCUMENTATION_NAME): New.
* config/gcn/gcn.cc (TARGET_DOCUMENTATION_NAME): New.
* config/h8300/h8300.cc (TARGET_DOCUMENTATION_NAME): New.
* config/i386/i386.cc (TARGET_DOCUMENTATION_NAME): New.
* config/ia64/ia64.cc (TARGET_DOCUMENTATION_NAME): New.
* config/m32c/m32c.cc (TARGET_DOCUMENTATION_NAME): New.
* config/m32r/m32r.cc (TARGET_DOCUMENTATION_NAME): New.
* config/m68k/m68k.cc (TARGET_DOCUMENTATION_NAME): New.
* config/mcore/mcore.cc (TARGET_DOCUMENTATION_NAME): New.
* config/microblaze/microblaze.cc (TARGET_DOCUMENTATION_NAME):
New.
* config/mips/mips.cc (TARGET_DOCUMENTATION_NAME): New.
* config/msp430/msp430.cc (TARGET_DOCUMENTATION_NAME): New.
* config/nds32/nds32.cc (TARGET_DOCUMENTATION_NAME): New.
* config/nvptx/nvptx.cc (TARGET_DOCUMENTATION_NAME): New.
* config/riscv/riscv.cc (TARGET_DOCUMENTATION_NAME): New.
* config/rl78/rl78.cc (TARGET_DOCUMENTATION_NAME): New.
* config/rs6000/rs6000.cc (TARGET_DOCUMENTATION_NAME): New.
* config/rx/rx.cc (TARGET_DOCUMENTATION_NAME): New.
* config/s390/s390.cc (TARGET_DOCUMENTATION_NAME): New.
* config/sh/sh.cc (TARGET_DOCUMENTATION_NAME): New.
* config/stormy16/stormy16.cc (TARGET_DOCUMENTATION_NAME): New.
* config/v850/v850.cc (TARGET_DOCUMENTATION_NAME): New.
* config/visium/visium.cc (TARGET_DOCUMENTATION_NAME): New.
gcc/analyzer/ChangeLog:
* region-model.cc: Include "gcc-urlifier.h".
(reason_attr_access::emit): Use auto_urlify_attributes.
* sm-taint.cc: Include "gcc-urlifier.h".
(tainted_access_attrib_size::emit): Use auto_urlify_attributes.
gcc/c-family/ChangeLog:
* c-attribs.cc: Include "gcc-urlifier.h".
(positional_argument): Use auto_urlify_attributes.
* c-common.cc: Include "gcc-urlifier.h".
(parse_optimize_options): Use auto_urlify_attributes with
OPT_Wattributes.
(attribute_fallthrough_p): Use auto_urlify_attributes.
* c-warn.cc: Include "gcc-urlifier.h".
(diagnose_mismatched_attributes): Use auto_urlify_attributes.
gcc/c/ChangeLog:
* c-decl.cc: Include "gcc-urlifier.h".
(start_decl): Use auto_urlify_attributes with OPT_Wattributes.
(start_function): Likewise.
* c-parser.cc: Include "gcc-urlifier.h".
(c_parser_statement_after_labels): Use auto_urlify_attributes with
OPT_Wattributes.
* c-typeck.cc: Include "gcc-urlifier.h".
(maybe_warn_nodiscard): Use auto_urlify_attributes with
OPT_Wunused_result.
gcc/cp/ChangeLog:
* cp-gimplify.cc: Include "gcc-urlifier.h".
(process_stmt_hotness_attribute): Use auto_urlify_attributes with
OPT_Wattributes.
* cvt.cc: Include "gcc-urlifier.h".
(maybe_warn_nodiscard): Use auto_urlify_attributes with
OPT_Wunused_result.
* decl.cc: Include "gcc-urlifier.h".
(start_decl): Use auto_urlify_attributes.
(start_preparsed_function): Likewise.
gcc/ChangeLog:
* diagnostic.cc (diagnostic_context::override_urlifier): New.
* diagnostic.h (diagnostic_context::override_urlifier): New decl.
* doc/extend.texi (Nvidia PTX Function Attributes): Update
@cindex to specify that "kernel" is a function attribute and
"shared" is a variable attribute, so that these entries are
recognized by the regex in regenerate-attr-urls.py.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_DOCUMENTATION_NAME): New.
* gcc-attribute-urlifier.cc: New file.
* gcc-urlifier.cc: Include diagnostic.h.
(gcc_urlifier::make_doc): Convert to...
(make_doc_url): ...this.
(auto_override_urlifier::auto_override_urlifier): New.
(auto_override_urlifier::~auto_override_urlifier): New.
(selftest::gcc_urlifier_cc_tests): Split out body into...
(selftest::test_gcc_urlifier): ...this.
* gcc-urlifier.h: Include "pretty-print-urlifier.h" and "label-text.h".
(make_doc_url): New decl.
(class auto_override_urlifier): New.
(class attribute_urlifier): New.
(class auto_urlify_attributes): New.
* gimple-ssa-warn-access.cc: Include "gcc-urlifier.h".
(pass_waccess::execute): Use auto_urlify_attributes.
* gimplify.cc: Include "gcc-urlifier.h".
(expand_FALLTHROUGH): Use auto_urlify_attributes.
* internal-fn.cc: Define INCLUDE_MEMORY and include
"gcc-urlifier.h.
(expand_FALLTHROUGH): Use auto_urlify_attributes.
* ipa-pure-const.cc: Include "gcc-urlifier.h.
(suggest_attribute): Use auto_urlify_attributes.
* ipa-strub.cc: Include "gcc-urlifier.h.
(can_strub_p): Use auto_urlify_attributes.
* regenerate-attr-urls.py: New file.
* selftest-run-tests.cc (selftest::run_tests): Call
gcc_attribute_urlifier_cc_tests.
* selftest.h (selftest::gcc_attribute_urlifier_cc_tests): New
decl.
* target.def (documentation_name): New DEFHOOKPOD.
* tree-cfg.cc: Include "gcc-urlifier.h.
(do_warn_unused_result): Use auto_urlify_attributes.
* tree-ssa-uninit.cc: Include "gcc-urlifier.h.
(maybe_warn_read_write_only): Use auto_urlify_attributes.
(maybe_warn_pass_by_reference): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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Sometimes we want to use default cmodel other than medlow. Add a GCC
configure option for that.
gcc/ChangeLog:
* config.gcc (riscv*-*-*): Add support for --with-cmodel configure option.
(all_defaults): Add cmodel.
* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Remove.
* doc/install.texi: Document --with-cmodel configure option.
* doc/invoke.texi (-mcmodel): Mention --with-cmodel configure option.
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
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function_shape::get_name is the funciton for building intrinsic function name,
the result should not be changed by others once it built.
So add const to the return type to make sure no one change that by
accident.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc
(vsetvl_def::get_name): Adjust return type.
(loadstore_def::get_name): Ditto.
(indexed_loadstore_def::get_name): Ditto.
(th_loadstore_width_def::get_name): Ditto.
(th_indexed_loadstore_width_def::get_name): Ditto.
(alu_def::get_name): Ditto.
(alu_frm_def::get_name): Ditto.
(widen_alu_frm_def::get_name): Ditto.
(narrow_alu_frm_def::get_name): Ditto.
(reduc_alu_frm_def::get_name): Ditto.
(widen_alu_def::get_name): Ditto.
(no_mask_policy_def::get_name): Ditto.
(return_mask_def::get_name): Ditto.
(narrow_alu_def::get_name): Ditto.
(move_def::get_name): Ditto.
(mask_alu_def::get_name): Ditto.
(reduc_alu_def::get_name): Ditto.
(th_extract_def::get_name): Ditto.
(scalar_move_def::get_name): Ditto.
(vundefined_def::get_name): Ditto.
(misc_def::get_name): Ditto.
(vset_def::get_name): Ditto.
(vcreate_def: Ditto.::get_name): Ditto.
(read_vl_def::get_name): Ditto.
(fault_load_def::get_name): Ditto.
(vlenb_def::get_name): Ditto.
(seg_loadstore_def::get_name): Ditto.
(seg_indexed_loadstore_def::get_name): Ditto.
(seg_fault_load_def::get_name): Ditto.
(crypto_vv_def::get_name): Ditto.
(crypto_vi_def::get_name): Ditto.
(crypto_vv_no_op_type_def::get_name): Ditto.
(sf_vqmacc_def::get_name): Ditto.
(sf_vqmacc_def::get_name): Ditto.
(sf_vfnrclip_def::get_name): Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_builder::add_unique_function): Adjust the type for the
function name holder.
(function_builder::add_overloaded_function): Ditto.
* config/riscv/riscv-vector-builtins.h (function_shape::get_name): Add
const to the return type.
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sched1 computes ECC (Excess Change Cost) for each insn, which represents
the register pressure attributed to the insn.
Currently the pressure sensitive scheduling algorithm deliberately ignores
negative ECC values (pressure reduction), making them 0 (neutral), leading
to more spills. This happens due to the assumption that the compiler has
a reasonably accurate processor pipeline scheduling model and thus tries
to aggresively fill pipeline bubbles with spill slots.
This however might not be true, as the model might not be available for
certains uarches or even applicable especially for modern out-of-order cores.
The existing heuristic induces spill frenzy on RISC-V, noticably so on
SPEC2017 507.Cactu. If insn scheduling is disabled completely, the
total dynamic icounts for this workload are reduced in half from
~2.5 trillion insns to ~1.3 (w/ -fno-schedule-insns).
This patch adds --param=cycle-accurate-model={0,1} to gate the spill
behavior.
- The default (1) preserves existing spill behavior.
- targets/uarches sensitive to spilling can override the param to (0)
to get the reverse effect. RISC-V backend does so too.
The actual perf numbers are very promising.
(1) On RISC-V BPI-F3 in-order CPU, -Ofast -march=rv64gcv_zba_zbb_zbs:
Before:
------
Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par':
4,917,712.97 msec task-clock:u # 1.000 CPUs utilized
5,314 context-switches:u # 1.081 /sec
3 cpu-migrations:u # 0.001 /sec
204,784 page-faults:u # 41.642 /sec
7,868,291,222,513 cycles:u # 1.600 GHz
2,615,069,866,153 instructions:u # 0.33 insn per cycle
10,799,381,890 branches:u # 2.196 M/sec
15,714,572 branch-misses:u # 0.15% of all branches
After:
-----
Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par':
4,552,979.58 msec task-clock:u # 0.998 CPUs utilized
205,020 context-switches:u # 45.030 /sec
2 cpu-migrations:u # 0.000 /sec
204,221 page-faults:u # 44.854 /sec
7,285,176,204,764 cycles:u (7.4% faster) # 1.600 GHz
2,145,284,345,397 instructions:u (17.96% fewer) # 0.29 insn per cycle
10,799,382,011 branches:u # 2.372 M/sec
16,235,628 branch-misses:u # 0.15% of all branches
(2) Wilco reported 20% perf gains on aarch64 Neoverse V2 runs.
gcc/ChangeLog:
PR target/11472
* params.opt (--param=cycle-accurate-model=): New opt.
* doc/invoke.texi (cycle-accurate-model): Document.
* haifa-sched.cc (model_excess_group_cost): Return negative
delta if param_cycle_accurate_model is 0.
(model_excess_cost): Ceil negative baseECC to 0 only if
param_cycle_accurate_model is 1.
Dump the actual ECC value.
* config/riscv/riscv.cc (riscv_option_override): Set param
to 0.
gcc/testsuite/ChangeLog:
PR target/114729
* gcc.target/riscv/riscv.exp: Enable new tests to build.
* gcc.target/riscv/sched1-spills/spill1.cpp: Add new test.
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
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According to the the initial analysis of PR117878, the ice comes from
the out-of-range operand access for recog_data.operand[]. Thus, add
one assert here to expose this explicitly.
PR target/117878
gcc/ChangeLog:
* config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
out of range access.
(nonvlmax_avl_type_p): Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
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|
This commit adds intrinsics support for XXsfvfnrclipxfqf. We also redefine
the enum type frm_op_type in riscv-vector-builtins-bases.h file, because it
be used in sifive-vector-builtins-bases.cc file.
Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn>
gcc/ChangeLog:
* config/riscv/generic-vector-ooo.md: New reservation.
* config/riscv/genrvv-type-indexer.cc (main): New type.
* config/riscv/riscv-vector-builtins-bases.cc (enum frm_op_type): Delete it.
* config/riscv/riscv-vector-builtins-bases.h (enum frm_op_type): Redefine in h file.
* config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vfnrclip_def): New function.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE_INDEX): New builtins def.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX): New base def.
(signed_eew8_index): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext): New extension.
(required_ext_to_isa_name): Ditto.
(required_extensions_specified): Ditto.
(struct function_group_info): Ditto.
* config/riscv/riscv.md: New attr.
* config/riscv/sifive-vector-builtins-bases.cc (class sf_vfnrclip_x_f_qf): New function.
(class sf_vfnrclip_xu_f_qf): Ditto.
(BASE): New base_name.
* config/riscv/sifive-vector-builtins-bases.h: New function_base.
* config/riscv/sifive-vector-builtins-functions.def
(REQUIRED_EXTENSIONS): New intrinsics def.
(sf_vfnrclip_x_f_qf): Ditto.
(sf_vfnrclip_xu_f_qf): Ditto.
* config/riscv/sifive-vector.md (@pred_sf_vfnrclip<v_su><mode>_x_f_qf): New RTL mode.
* config/riscv/vector-iterators.md: New iterator.
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* config/riscv/riscv.cc (fli_value_hf, fli_value_sf)
(fli_value_df): Use integer constants. Constify.
(riscv_float_const_rtx_index_for_fli): Add const.
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A few targets have been using "unsigned int" function arguments that need to
receive a "location_t". Change to "location_t" to prepare for the
possibility that location_t can be configured to be a different type.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_resolve_overloaded_builtin):
Change "unsigned int" argument to "location_t".
* config/avr/avr-c.cc (avr_resolve_overloaded_builtin): Likewise.
* config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Likewise.
* target.def: Likewise.
* doc/tm.texi: Regenerate.
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If the target is ZBC or ZBKC, it uses clmul instruction for the CRC
calculation. Otherwise, if the target is ZBKB, generates table-based
CRC, but for reversing inputs and the output uses bswap and brev8
instructions. Add new tests to check CRC generation for ZBC, ZBKC and
ZBKB targets.
gcc/
* expr.cc (gf2n_poly_long_div_quotient): New function.
* expr.h (gf2n_poly_long_div_quotient): New function declaration.
* hwint.cc (reflect_hwi): New function.
* hwint.h (reflect_hwi): New function declaration.
* config/riscv/bitmanip.md (crc_rev<ANYI1:mode><ANYI:mode>4): New
expander for reversed CRC.
(crc<SUBX1:mode><SUBX:mode>4): New expander for bit-forward CRC.
* config/riscv/iterators.md (SUBX1, ANYI1): New iterators.
* config/riscv/riscv-protos.h (generate_reflecting_code_using_brev):
New function declaration.
(expand_crc_using_clmul): Likewise.
(expand_reversed_crc_using_clmul): Likewise.
* config/riscv/riscv.cc (generate_reflecting_code_using_brev): New
function.
(expand_crc_using_clmul): Likewise.
(expand_reversed_crc_using_clmul): Likewise.
* config/riscv/riscv.md (UNSPEC_CRC, UNSPEC_CRC_REV): New unspecs.
* doc/sourcebuild.texi: Document new target selectors.
gcc/testsuite
* lib/target-supports.exp (check_effective_target_riscv_zbc): New
target supports predicate.
(check_effective_target_riscv_zbkb): Likewise.
(check_effective_target_riscv_zbkc): Likewise.
(check_effective_target_zbc_ok): Likewise.
(check_effective_target_zbkb_ok): Likewise.
(check_effective_target_zbkc_ok): Likewise.
(riscv_get_arch): Add zbkb and zbkc support.
* gcc.target/riscv/crc-builtin-zbc32.c: New file.
* gcc.target/riscv/crc-builtin-zbc64.c: Likewise.
Co-author: Jeff Law <jlaw@ventanamicro.com>
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This commit adds intrinsics support for Xsfvqmaccqoq/dod.
Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn>
gcc/ChangeLog:
* config.gcc: Add new SiFive *.o files.
* config/riscv/generic-vector-ooo.md: New reservation.
* config/riscv/genrvv-type-indexer.cc (main): New type.
* config/riscv/riscv-vector-builtins-shapes.cc (struct sf_vqmacc_def): New function.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QMACC_OPS): New macros type.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_QMACC_OPS): New builtins def.
(DEF_RVV_TYPE_INDEX): Ditto.
(DEF_RVV_FUNCTION): Ditto.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX): New types def.
(4x8x4): New op type.
(2x8x2): Ditto.
(quad_emul_vector): New base type.
(quad_emul_signed_vector): Ditto.
(quad_emul_unsigned_vector): Ditto.
(quad_fixed_vector): Ditto.
(quad_fixed_signed_vector): Ditto.
(quad_fixed_unsigned_vector): Ditto.
(quad_lmul1_vector): Ditto.
(quad_lmul1_signed_vector): Ditto.
(quad_lmul1_unsigned_vector): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext): New extensions.
(required_ext_to_isa_name): Ditto.
(required_extensions_specified): Ditto.
(struct function_group_info): Ditto.
* config/riscv/riscv.md: New attr.
* config/riscv/t-riscv: Add include for SiFive files.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md: New include for SiFive file.
* config/riscv/sifive-vector-builtins-bases.cc: New file.
* config/riscv/sifive-vector-builtins-bases.h: New file.
* config/riscv/sifive-vector-builtins-functions.def: New file.
* config/riscv/sifive-vector.md: New file.
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The r15-4833-ge9ab41b79933 patch had among tons of config/i386
specific changes also important change to the generic code, allowing
also 2 as valid value of the second argument of __builtin_prefetch:
- /* Argument 1 must be either zero or one. */
- if (INTVAL (op1) != 0 && INTVAL (op1) != 1)
+ /* Argument 1 must be 0, 1 or 2. */
+ if (INTVAL (op1) < 0 || INTVAL (op1) > 2)
But the patch failed to document that change in __builtin_prefetch
documentation, and more importantly didn't adjust any of the other
backends to deal with it (my understanding is the expected behavior
is that 2 will be silently handled as 0 unless backends have some
more specific way). Some of the backends would ICE on it, in some
cases gcc_assert failures/gcc_unreachable, in other cases crash later
(e.g. accessing arrays with that value as index and due to accessing
garbage after the array crashing at final.cc time), others treated 2
silently as 0, others treated 2 silently as 1.
And even in the i386 backend there were bugs which caused ICEs.
The patch added some if (write == 0) and write 2 handling into
a (badly indented, maybe that is the reason, if (write == 1) body),
rather than into the else side, so it would be always false.
The new *prefetch_rst2 define_insn only accepts parameters 2 1
(i.e. read-shared with moderate degree of locality), so in order
not to ICE the patch uses it only for __builtin_prefetch (ptr, 2, 1);
or __builtin_ia32_prefetch (ptr, 2, 1, 0); and not for other values
of the parameter. If that isn't what we want and we want it to be used
also for all or some of __builtin_prefetch (ptr, 2, {0,2,3}); and
corresponding __builtin_ia32_prefetch, maybe the define_insn could match
other values.
And there was another problem that -mno-mmx -mno-sse -mmovrs compilation
would ICE on most of the prefetches, so I had to add the FAIL; cases.
2024-11-29 Jakub Jelinek <jakub@redhat.com>
PR target/117608
* doc/extend.texi (__builtin_prefetch): Document that second
argument may be also 2 and its meaning.
* config/i386/i386.md (prefetch): Remove unreachable code.
Clear write set operands[1] to const0_rtx if !TARGET_MOVRS or
of locality is not 1. Formatting fixes.
* config/i386/i386-expand.cc (ix86_expand_builtin): Use IN_RANGE.
Call gen_prefetch even for TARGET_MOVRS.
* config/alpha/alpha.md (prefetch): Treat read_or_write 2 like 0.
* config/mips/mips.md (prefetch): Likewise.
* config/arc/arc.md (prefetch_1, prefetch_2, prefetch_3): Likewise.
* config/riscv/riscv.md (prefetch): Likewise.
* config/loongarch/loongarch.md (prefetch): Likewise.
* config/sparc/sparc.md (prefetch): Likewise. Use IN_RANGE.
* config/ia64/ia64.md (prefetch): Likewise.
* config/pa/pa.md (prefetch): Likewise.
* config/aarch64/aarch64.md (prefetch): Likewise.
* config/rs6000/rs6000.md (prefetch): Likewise.
* gcc.dg/builtin-prefetch-1.c (good): Add tests with second argument
2.
* gcc.target/i386/pr117608-1.c: New test.
* gcc.target/i386/pr117608-2.c: New test.
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No functional change intended.
gcc/analyzer/ChangeLog:
PR c/104896
* sm-malloc.cc: Replace "%<%s%>" with "%qs" in message wording.
gcc/c-family/ChangeLog:
PR c/104896
* c-lex.cc (c_common_lex_availability_macro): Replace "%<%s%>"
with "%qs" in message wording.
* c-opts.cc (c_common_handle_option): Likewise.
* c-warn.cc (warn_parm_array_mismatch): Likewise.
gcc/ChangeLog:
PR c/104896
* common/config/ia64/ia64-common.cc (ia64_handle_option): Replace
"%<%s%>" with "%qs" in message wording.
* common/config/rs6000/rs6000-common.cc (rs6000_handle_option):
Likewise.
* config/aarch64/aarch64.cc (aarch64_validate_sls_mitigation):
Likewise.
(aarch64_override_options): Likewise.
(aarch64_process_target_attr): Likewise.
* config/arm/aarch-common.cc (aarch_validate_mbranch_protection):
Likewise.
* config/pru/pru.cc (pru_insert_attributes): Likewise.
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch): Likewise.
* omp-general.cc (oacc_verify_routine_clauses): Likewise.
* tree-ssa-uninit.cc (maybe_warn_read_write_only): Likewise.
(maybe_warn_pass_by_reference): Likewise.
gcc/cp/ChangeLog:
PR c/104896
* cvt.cc (maybe_warn_nodiscard): Replace "%<%s%>" with "%qs" in
message wording.
gcc/fortran/ChangeLog:
PR c/104896
* resolve.cc (resolve_operator): Replace "%<%s%>" with "%qs" in
message wording.
gcc/go/ChangeLog:
PR c/104896
* gofrontend/embed.cc (Gogo::initializer_for_embeds): Replace
"%<%s%>" with "%qs" in message wording.
* gofrontend/expressions.cc
(Selector_expression::lower_method_expression): Likewise.
* gofrontend/gogo.cc (Gogo::set_package_name): Likewise.
(Named_object::export_named_object): Likewise.
* gofrontend/parse.cc (Parse::struct_type): Likewise.
(Parse::parameter_list): Likewise.
gcc/rust/ChangeLog:
PR c/104896
* backend/rust-compile-expr.cc
(CompileExpr::compile_integer_literal): Replace "%<%s%>" with
"%qs" in message wording.
(CompileExpr::compile_float_literal): Likewise.
* backend/rust-compile-intrinsic.cc (Intrinsics::compile):
Likewise.
* backend/rust-tree.cc (maybe_warn_nodiscard): Likewise.
* checks/lints/rust-lint-scan-deadcode.h: Likewise.
* lex/rust-lex.cc (Lexer::parse_partial_unicode_escape): Likewise.
(Lexer::parse_raw_byte_string): Likewise.
* lex/rust-token.cc (Token::get_str): Likewise.
* metadata/rust-export-metadata.cc
(PublicInterface::write_to_path): Likewise.
* parse/rust-parse.cc
(peculiar_fragment_match_compatible_fragment): Likewise.
(peculiar_fragment_match_compatible): Likewise.
* resolve/rust-ast-resolve-path.cc (ResolvePath::resolve_path):
Likewise.
* resolve/rust-ast-resolve-toplevel.h: Likewise.
* resolve/rust-ast-resolve-type.cc (ResolveRelativeTypePath::go):
Likewise.
* rust-session-manager.cc (validate_crate_name): Likewise.
(Session::load_extern_crate): Likewise.
* typecheck/rust-hir-type-check-expr.cc (TypeCheckExpr::visit):
Likewise.
(TypeCheckExpr::resolve_fn_trait_call): Likewise.
* typecheck/rust-hir-type-check-implitem.cc
(TypeCheckImplItemWithTrait::visit): Likewise.
* typecheck/rust-hir-type-check-item.cc
(TypeCheckItem::validate_trait_impl_block): Likewise.
* typecheck/rust-hir-type-check-struct.cc
(TypeCheckStructExpr::visit): Likewise.
* typecheck/rust-tyty-call.cc (TypeCheckCallExpr::visit):
Likewise.
* typecheck/rust-tyty.cc (BaseType::bounds_compatible): Likewise.
* typecheck/rust-unify.cc (UnifyRules::emit_abi_mismatch):
Likewise.
* util/rust-attributes.cc (AttributeChecker::visit): Likewise.
libcpp/ChangeLog:
PR c/104896
* pch.cc (cpp_valid_state): Replace "%<%s%>" with "%qs" in message
wording.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
In the following situation (found in the
rvv/autovec/vls-vlmax/shuffle-slide.c test which is not yet pushed)
vsetivli zero,4,e8,mf4,ta,ma
vle8.v v2,0(a1) # (1)
vle8.v v1,0(a2) # (2)
vsetivli zero,2,e8,mf4,tu,ma
vslidedown.vi v1,v2,2
vsetivli zero,4,e8,mf4,ta,ma
vse8.v v1,0(a2)
we wrongly "propagate" VL=2 from vslidedown into the load.
Although we check whether the "target" instruction has a merge operand
the check only handles cases where the merge operand itself is
loaded, like (2) in the snippet above. For (1) we load the non-merged
operand, assume propagation is valid and continue despite (2).
This patch just re-uses avl_can_be_propagated_p in order to disable
slides altogether in such situations.
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (pass_avlprop::get_vlmax_ta_preferred_avl):
Check whether the use insn is valid for propagation.
|
|
The index markers changed slightly when nios2 were removed.
This just regenerates the files.
gcc/ChangeLog:
* config/g.opt.urls: Regenerate.
* config/i386/i386.opt.urls: Regenerate.
* config/i386/nto.opt.urls: Regenerate.
* config/nvptx/nvptx.opt.urls: Regenerate.
* config/riscv/riscv.opt.urls: Regenerate.
* config/s390/s390.opt.urls: Regenerate.
* config/sol2.opt.urls: Regenerate.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
As discussed in PR117544 the VTYPE register is not preserved across
function calls. Even though vmv1r-like instructions operate
independently of the actual vtype they still require a valid vtype. As
we cannot guarantee that the vtype is valid we must make sure to emit a
vsetvl between a function call and a vmv1r.v.
This patch makes the necessary changes by splitting the full-reg-move
insns into patterns that use the vtype register and adding vmov to the
types of instructions requiring a vset.
PR target/117544
gcc/ChangeLog:
* config/riscv/vector.md (*mov<mode>_whole): Split.
(*mov<mode>_fract): Ditto.
(*mov<mode>): Ditto.
(*mov<mode>_vls): Ditto.
(*mov<mode>_reg_whole_vtype): New pattern with vtype use.
(*mov<mode>_fract_vtype): Ditto.
(*mov<mode>_vtype): Ditto.
(*mov<mode>_vls_vtype): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-call-args-4.c: Expect vsetvl.
* gcc.target/riscv/rvv/base/pr117544.c: New test.
|
|
Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 at
the same time without building multiple libasan versions!
[1] https://github.com/llvm/llvm-project/commit/da0c8b275564f814a53a5c19497669ae2d99538d
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_asan_shadow_offset): Use dynamic
offset for RV64.
(riscv_asan_dynamic_shadow_offset_p): New.
(TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P): New.
gcc/testsuite/ChangeLog:
* g++.dg/asan/asan_test.cc: Update the testcase for dynamic
offset.
|
|
This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile time.
[1] https://github.com/riscv/riscv-svvptc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
* config/riscv/riscv.opt: New mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-44.c: New test.
|
|
Just regenerated them after the addition of msplit-bit-shift avr option.
Pushed as obvious.
gcc/ChangeLog:
* config/avr/avr.opt.urls: Regenerate.
* config/g.opt.urls: Regenerate.
* config/i386/nto.opt.urls: Regenerate.
* config/riscv/riscv.opt.urls: Regenerate.
* config/rx/rx.opt.urls: Regenerate.
* config/sol2.opt.urls: Regenerate.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
Since diagnostic.h is included in over half of the sources, requiring to `#define INCLUDE_MEMORY`
does not make sense. Instead lets unconditionally include memory in system.h.
The majority of this patch is just removing `#define INCLUDE_MEMORY` from the sources which currently
have it.
This should also fix the mingw build issue but I have not tried it.
Bootstrapped and tested on x86_64-linux-gnu.
PR bootstrap/117737
gcc/ada/ChangeLog:
* gcc-interface/misc.cc (INCLUDE_MEMORY): Remove.
* gcc-interface/trans.cc (INCLUDE_MEMORY): Remove.
* gcc-interface/utils.cc (INCLUDE_MEMORY): Remove.
gcc/analyzer/ChangeLog:
* access-diagram.cc (INCLUDE_MEMORY): Remove.
* analysis-plan.cc (INCLUDE_MEMORY): Remove.
* analyzer-language.cc (INCLUDE_MEMORY): Remove.
* analyzer-logging.cc (INCLUDE_MEMORY): Remove.
* analyzer-pass.cc (INCLUDE_MEMORY): Remove.
* analyzer-selftests.cc (INCLUDE_MEMORY): Remove.
* analyzer.cc (INCLUDE_MEMORY): Remove.
* bar-chart.cc (INCLUDE_MEMORY): Remove.
* bounds-checking.cc (INCLUDE_MEMORY): Remove.
* call-details.cc (INCLUDE_MEMORY): Remove.
* call-info.cc (INCLUDE_MEMORY): Remove.
* call-string.cc (INCLUDE_MEMORY): Remove.
* call-summary.cc (INCLUDE_MEMORY): Remove.
* checker-event.cc (INCLUDE_MEMORY): Remove.
* checker-path.cc (INCLUDE_MEMORY): Remove.
* complexity.cc (INCLUDE_MEMORY): Remove.
* constraint-manager.cc (INCLUDE_MEMORY): Remove.
* diagnostic-manager.cc (INCLUDE_MEMORY): Remove.
* engine.cc (INCLUDE_MEMORY): Remove.
* feasible-graph.cc (INCLUDE_MEMORY): Remove.
* infinite-loop.cc (INCLUDE_MEMORY): Remove.
* infinite-recursion.cc (INCLUDE_MEMORY): Remove.
* kf-analyzer.cc (INCLUDE_MEMORY): Remove.
* kf-lang-cp.cc (INCLUDE_MEMORY): Remove.
* kf.cc (INCLUDE_MEMORY): Remove.
* known-function-manager.cc (INCLUDE_MEMORY): Remove.
* pending-diagnostic.cc (INCLUDE_MEMORY): Remove.
* program-point.cc (INCLUDE_MEMORY): Remove.
* program-state.cc (INCLUDE_MEMORY): Remove.
* ranges.cc (INCLUDE_MEMORY): Remove.
* record-layout.cc (INCLUDE_MEMORY): Remove.
* region-model-asm.cc (INCLUDE_MEMORY): Remove.
* region-model-manager.cc (INCLUDE_MEMORY): Remove.
* region-model-reachability.cc (INCLUDE_MEMORY): Remove.
* region-model.cc (INCLUDE_MEMORY): Remove.
* region.cc (INCLUDE_MEMORY): Remove.
* sm-fd.cc (INCLUDE_MEMORY): Remove.
* sm-file.cc (INCLUDE_MEMORY): Remove.
* sm-malloc.cc (INCLUDE_MEMORY): Remove.
* sm-pattern-test.cc (INCLUDE_MEMORY): Remove.
* sm-sensitive.cc (INCLUDE_MEMORY): Remove.
* sm-signal.cc (INCLUDE_MEMORY): Remove.
* sm-taint.cc (INCLUDE_MEMORY): Remove.
* sm.cc (INCLUDE_MEMORY): Remove.
* state-purge.cc (INCLUDE_MEMORY): Remove.
* store.cc (INCLUDE_MEMORY): Remove.
* supergraph.cc (INCLUDE_MEMORY): Remove.
* svalue.cc (INCLUDE_MEMORY): Remove.
* symbol.cc (INCLUDE_MEMORY): Remove.
* trimmed-graph.cc (INCLUDE_MEMORY): Remove.
* varargs.cc (INCLUDE_MEMORY): Remove.
gcc/ChangeLog:
* asan.cc (INCLUDE_MEMORY): Remove.
* attribs.cc (INCLUDE_MEMORY): Remove.
* auto-profile.cc (INCLUDE_MEMORY): Remove.
* calls.cc (INCLUDE_MEMORY): Remove.
* cfganal.cc (INCLUDE_MEMORY): Remove.
* cfgexpand.cc (INCLUDE_MEMORY): Remove.
* cfghooks.cc (INCLUDE_MEMORY): Remove.
* cfgloop.cc (INCLUDE_MEMORY): Remove.
* cgraph.cc (INCLUDE_MEMORY): Remove.
* cgraphclones.cc (INCLUDE_MEMORY): Remove.
* cgraphunit.cc (INCLUDE_MEMORY): Remove.
* collect-utils.cc (INCLUDE_MEMORY): Remove.
* collect2.cc (INCLUDE_MEMORY): Remove.
* common/config/aarch64/aarch64-common.cc (INCLUDE_MEMORY): Remove.
* common/config/arm/arm-common.cc (INCLUDE_MEMORY): Remove.
* common/config/avr/avr-common.cc (INCLUDE_MEMORY): Remove.
* config/aarch64/aarch64-cc-fusion.cc (INCLUDE_MEMORY): Remove.
* config/aarch64/aarch64-early-ra.cc (INCLUDE_MEMORY): Remove.
* config/aarch64/aarch64-sve-builtins.cc (INCLUDE_MEMORY): Remove.
* config/aarch64/aarch64.cc (INCLUDE_MEMORY): Remove.
* config/arc/arc.cc (INCLUDE_MEMORY): Remove.
* config/arm/aarch-common.cc (INCLUDE_MEMORY) Remove.:
* config/arm/arm-mve-builtins.cc (INCLUDE_MEMORY): Remove.
* config/arm/arm.cc (INCLUDE_MEMORY): Remove.
* config/avr/avr-devices.cc (INCLUDE_MEMORY): Remove.
* config/avr/driver-avr.cc (INCLUDE_MEMORY): Remove.
* config/bpf/bpf.cc (INCLUDE_MEMORY): Remove.
* config/bpf/btfext-out.cc (INCLUDE_MEMORY): Remove.
* config/bpf/core-builtins.cc (INCLUDE_MEMORY): Remove.
* config/darwin.cc (INCLUDE_MEMORY): Remove.
* config/gcn/mkoffload.cc (INCLUDE_MEMORY): Remove.
* config/i386/driver-i386.cc (INCLUDE_MEMORY): Remove.
* config/i386/i386-builtins.cc (INCLUDE_MEMORY): Remove.
* config/i386/i386-expand.cc (INCLUDE_MEMORY): Remove.
* config/i386/i386-features.cc (INCLUDE_MEMORY): Remove.
* config/i386/i386-options.cc (INCLUDE_MEMORY): Remove.
* config/i386/i386.cc (INCLUDE_MEMORY): Remove.
* config/loongarch/loongarch-builtins.cc (INCLUDE_MEMORY): Remove.
* config/loongarch/loongarch.cc (INCLUDE_MEMORY): Remove.
* config/mingw/winnt-cxx.cc (INCLUDE_MEMORY): Remove.
* config/mingw/winnt.cc (INCLUDE_MEMORY): Remove.
* config/mips/mips.cc (INCLUDE_MEMORY): Remove.
* config/msp430/driver-msp430.cc (INCLUDE_MEMORY): Remove.
* config/nvptx/mkoffload.cc (INCLUDE_MEMORY): Remove.
* config/nvptx/nvptx.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv-avlprop.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv-target-attr.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv-vector-builtins.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv-vector-costs.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv-vsetvl.cc (INCLUDE_MEMORY): Remove.
* config/riscv/riscv.cc (INCLUDE_MEMORY): Remove.
* config/rs6000/driver-rs6000.cc (INCLUDE_MEMORY): Remove.
* config/rs6000/host-darwin.cc (INCLUDE_MEMORY): Remove.
* config/rs6000/rs6000-c.cc (INCLUDE_MEMORY): Remove.
* config/rs6000/rs6000.cc (INCLUDE_MEMORY): Remove.
* config/s390/s390-c.cc (INCLUDE_MEMORY): Remove.
* config/s390/s390.cc (INCLUDE_MEMORY): Remove.
* config/sol2-cxx.cc (INCLUDE_MEMORY): Remove.
* config/vms/vms-c.cc (INCLUDE_MEMORY): Remove.
* config/xtensa/xtensa-dynconfig.cc (INCLUDE_MEMORY): Remove.
* coroutine-passes.cc (INCLUDE_MEMORY): Remove.
* coverage.cc (INCLUDE_MEMORY): Remove.
* data-streamer-in.cc (INCLUDE_MEMORY): Remove.
* data-streamer-out.cc (INCLUDE_MEMORY): Remove.
* data-streamer.cc (INCLUDE_MEMORY): Remove.
* diagnostic-format-json.cc (INCLUDE_MEMORY): Remove.
* diagnostic-format-sarif.cc (INCLUDE_MEMORY): Remove.
* diagnostic-format-text.cc (INCLUDE_MEMORY): Remove.
* diagnostic-global-context.cc (INCLUDE_MEMORY): Remove.
* diagnostic-macro-unwinding.cc (INCLUDE_MEMORY): Remove.
* diagnostic-path.cc (INCLUDE_MEMORY): Remove.
* diagnostic-show-locus.cc (INCLUDE_MEMORY): Remove.
* diagnostic-spec.cc (INCLUDE_MEMORY): Remove.
* diagnostic.cc (INCLUDE_MEMORY): Remove.
* diagnostic.h: Remove check for INCLUDE_MEMORY.
* digraph.cc (INCLUDE_MEMORY): Remove.
* dumpfile.cc (INCLUDE_MEMORY): Remove.
* dwarf2out.cc (INCLUDE_MEMORY): Remove.
* edit-context.cc (INCLUDE_MEMORY): Remove.
* except.cc (INCLUDE_MEMORY): Remove.
* expr.cc (INCLUDE_MEMORY): Remove.
* file-prefix-map.cc (INCLUDE_MEMORY): Remove.
* final.cc (INCLUDE_MEMORY): Remove.
* fwprop.cc (INCLUDE_MEMORY): Remove.
* gcc-plugin.h (INCLUDE_MEMORY): Remove.
* gcc-rich-location.cc (INCLUDE_MEMORY): Remove.
* gcc-urlifier.cc (INCLUDE_MEMORY): Remove.
* gcc.cc (INCLUDE_MEMORY): Remove.
* gcov-dump.cc (INCLUDE_MEMORY): Remove.
* gcov-tool.cc (INCLUDE_MEMORY): Remove.
* gcov.cc (INCLUDE_MEMORY): Remove.
* gengtype.cc (open_base_files): Don't print `#define INCLUDE_MEMORY`.
* genmatch.cc (INCLUDE_MEMORY): Remove.
* gimple-fold.cc (INCLUDE_MEMORY): Remove.
* gimple-harden-conditionals.cc (INCLUDE_MEMORY): Remove.
* gimple-harden-control-flow.cc (INCLUDE_MEMORY): Remove.
* gimple-if-to-switch.cc (INCLUDE_MEMORY): Remove.
* gimple-loop-interchange.cc (INCLUDE_MEMORY): Remove.
* gimple-loop-jam.cc (INCLUDE_MEMORY): Remove.
* gimple-loop-versioning.cc (INCLUDE_MEMORY): Remove.
* gimple-lower-bitint.cc (INCLUDE_MEMORY): Remove.
* gimple-predicate-analysis.cc (INCLUDE_MEMORY): Remove.
* gimple-pretty-print.cc (INCLUDE_MEMORY): Remove.
* gimple-range-cache.cc (INCLUDE_MEMORY): Remove.
* gimple-range-edge.cc (INCLUDE_MEMORY): Remove.
* gimple-range-fold.cc (INCLUDE_MEMORY): Remove.
* gimple-range-gori.cc (INCLUDE_MEMORY): Remove.
* gimple-range-infer.cc (INCLUDE_MEMORY): Remove.
* gimple-range-op.cc (INCLUDE_MEMORY): Remove.
* gimple-range-path.cc (INCLUDE_MEMORY): Remove.
* gimple-range-phi.cc (INCLUDE_MEMORY): Remove.
* gimple-range-trace.cc (INCLUDE_MEMORY): Remove.
* gimple-range.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-backprop.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-sprintf.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-store-merging.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-strength-reduction.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-warn-access.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-warn-alloca.cc (INCLUDE_MEMORY): Remove.
* gimple-ssa-warn-restrict.cc (INCLUDE_MEMORY): Remove.
* gimple-streamer-in.cc (INCLUDE_MEMORY): Remove.
* gimple-streamer-out.cc (INCLUDE_MEMORY): Remove.
* gimple.cc (INCLUDE_MEMORY): Remove.
* gimplify.cc (INCLUDE_MEMORY): Remove.
* graph.cc (INCLUDE_MEMORY): Remove.
* graphite-dependences.cc (INCLUDE_MEMORY): Remove.
* graphite-isl-ast-to-gimple.cc (INCLUDE_MEMORY): Remove.
* graphite-optimize-isl.cc (INCLUDE_MEMORY): Remove.
* graphite-poly.cc (INCLUDE_MEMORY): Remove.
* graphite-scop-detection.cc (INCLUDE_MEMORY): Remove.
* graphite-sese-to-poly.cc (INCLUDE_MEMORY): Remove.
* graphite.cc (INCLUDE_MEMORY): Remove.
* graphviz.cc (INCLUDE_MEMORY): Remove.
* input.cc (INCLUDE_MEMORY): Remove.
* ipa-cp.cc (INCLUDE_MEMORY): Remove.
* ipa-devirt.cc (INCLUDE_MEMORY): Remove.
* ipa-fnsummary.cc (INCLUDE_MEMORY): Remove.
* ipa-free-lang-data.cc (INCLUDE_MEMORY): Remove.
* ipa-icf-gimple.cc (INCLUDE_MEMORY): Remove.
* ipa-icf.cc (INCLUDE_MEMORY): Remove.
* ipa-inline-analysis.cc (INCLUDE_MEMORY): Remove.
* ipa-inline.cc (INCLUDE_MEMORY): Remove.
* ipa-modref-tree.cc (INCLUDE_MEMORY): Remove.
* ipa-modref.cc (INCLUDE_MEMORY): Remove.
* ipa-param-manipulation.cc (INCLUDE_MEMORY): Remove.
* ipa-polymorphic-call.cc (INCLUDE_MEMORY): Remove.
* ipa-predicate.cc (INCLUDE_MEMORY): Remove.
* ipa-profile.cc (INCLUDE_MEMORY): Remove.
* ipa-prop.cc (INCLUDE_MEMORY): Remove.
* ipa-pure-const.cc (INCLUDE_MEMORY): Remove.
* ipa-reference.cc (INCLUDE_MEMORY): Remove.
* ipa-split.cc (INCLUDE_MEMORY): Remove.
* ipa-sra.cc (INCLUDE_MEMORY): Remove.
* ipa-strub.cc (INCLUDE_MEMORY): Remove.
* ipa-utils.cc (INCLUDE_MEMORY): Remove.
* json-parsing.cc (INCLUDE_MEMORY): Remove.
* json.cc (INCLUDE_MEMORY): Remove.
* json.h: Don't check INCLUDE_MEMORY.
* langhooks.cc (INCLUDE_MEMORY): Remove.
* late-combine.cc (INCLUDE_MEMORY): Remove.
* lazy-diagnostic-path.cc (INCLUDE_MEMORY): Remove.
* libdiagnostics.cc (INCLUDE_MEMORY): Remove.
* libsarifreplay.cc (INCLUDE_MEMORY): Remove.
* lto-cgraph.cc (INCLUDE_MEMORY): Remove.
* lto-compress.cc (INCLUDE_MEMORY): Remove.
* lto-opts.cc (INCLUDE_MEMORY): Remove.
* lto-section-in.cc (INCLUDE_MEMORY): Remove.
* lto-section-out.cc (INCLUDE_MEMORY): Remove.
* lto-streamer-in.cc (INCLUDE_MEMORY): Remove.
* lto-streamer-out.cc (INCLUDE_MEMORY): Remove.
* lto-streamer.cc (INCLUDE_MEMORY): Remove.
* lto-wrapper.cc (INCLUDE_MEMORY): Remove.
* make-unique.h (GCC_MAKE_UNIQUE): Remove.
* multiple_target.cc (INCLUDE_MEMORY): Remove.
* omp-expand.cc (INCLUDE_MEMORY): Remove.
* omp-general.cc (INCLUDE_MEMORY): Remove.
* omp-low.cc (INCLUDE_MEMORY): Remove.
* omp-oacc-neuter-broadcast.cc (INCLUDE_MEMORY): Remove.
* omp-offload.cc (INCLUDE_MEMORY): Remove.
* omp-simd-clone.cc (INCLUDE_MEMORY): Remove.
* opt-problem.cc (INCLUDE_MEMORY): Remove.
* optinfo-emit-json.cc (INCLUDE_MEMORY): Remove.
* optinfo.cc (INCLUDE_MEMORY): Remove.
* optinfo.h: Don't check INCLUDE_MEMORY.
* opts-common.cc (INCLUDE_MEMORY): Remove.
* opts-diagnostic.cc (INCLUDE_MEMORY): Remove.
* opts-global.cc (INCLUDE_MEMORY): Remove.
* opts.cc (INCLUDE_MEMORY): Remove.
* pair-fusion.cc (INCLUDE_MEMORY): Remove.
* passes.cc (INCLUDE_MEMORY): Remove.
* pointer-query.cc (INCLUDE_MEMORY): Remove.
* predict.cc (INCLUDE_MEMORY): Remove.
* pretty-print.cc (INCLUDE_MEMORY): Remove.
* pretty-print.h: Don't check INCLUDE_MEMORY.
* print-rtl.cc (INCLUDE_MEMORY): Remove.
* print-tree.cc (INCLUDE_MEMORY): Remove.
* profile-count.cc (INCLUDE_MEMORY): Remove.
* range-op-float.cc (INCLUDE_MEMORY): Remove.
* range-op-ptr.cc (INCLUDE_MEMORY): Remove.
* range-op.cc (INCLUDE_MEMORY): Remove.
* range.cc (INCLUDE_MEMORY): Remove.
* read-rtl-function.cc (INCLUDE_MEMORY): Remove.
* rtl-error.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/accesses.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/blocks.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/changes.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/functions.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/insns.cc (INCLUDE_MEMORY): Remove.
* rtl-ssa/movement.cc (INCLUDE_MEMORY): Remove.
* rtl-tests.cc (INCLUDE_MEMORY): Remove.
* sanopt.cc (INCLUDE_MEMORY): Remove.
* sched-rgn.cc (INCLUDE_MEMORY): Remove.
* selftest-diagnostic-path.cc (INCLUDE_MEMORY): Remove.
* selftest-diagnostic.cc (INCLUDE_MEMORY): Remove.
* selftest-json.cc (INCLUDE_MEMORY): Remove.
* sese.cc (INCLUDE_MEMORY): Remove.
* simple-diagnostic-path.cc (INCLUDE_MEMORY): Remove.
* splay-tree-utils.cc (INCLUDE_MEMORY): Remove.
* sreal.cc (INCLUDE_MEMORY): Remove.
* stmt.cc (INCLUDE_MEMORY): Remove.
* substring-locations.cc (INCLUDE_MEMORY): Remove.
* symtab-clones.cc (INCLUDE_MEMORY): Remove.
* symtab-thunks.cc (INCLUDE_MEMORY): Remove.
* symtab.cc (INCLUDE_MEMORY): Remove.
* system.h: Include memory unconditionally for C++.
Also remove support for INCLUDE_MEMORY.
* targhooks.cc (INCLUDE_MEMORY): Remove.
* text-art/box-drawing.cc (INCLUDE_MEMORY): Remove.
* text-art/canvas.cc (INCLUDE_MEMORY): Remove.
* text-art/ruler.cc (INCLUDE_MEMORY): Remove.
* text-art/selftests.cc (INCLUDE_MEMORY): Remove.
* text-art/style.cc (INCLUDE_MEMORY): Remove.
* text-art/styled-string.cc (INCLUDE_MEMORY): Remove.
* text-art/table.cc (INCLUDE_MEMORY): Remove.
* text-art/theme.cc (INCLUDE_MEMORY): Remove.
* text-art/tree-widget.cc (INCLUDE_MEMORY): Remove.
* text-art/widget.cc (INCLUDE_MEMORY): Remove.
* timevar.cc (INCLUDE_MEMORY): Remove.
* toplev.cc (INCLUDE_MEMORY): Remove.
* trans-mem.cc (INCLUDE_MEMORY): Remove.
* tree-affine.cc (INCLUDE_MEMORY): Remove.
* tree-assume.cc (INCLUDE_MEMORY): Remove.
* tree-call-cdce.cc (INCLUDE_MEMORY): Remove.
* tree-cfg.cc (INCLUDE_MEMORY): Remove.
* tree-chrec.cc (INCLUDE_MEMORY): Remove.
* tree-data-ref.cc (INCLUDE_MEMORY): Remove.
* tree-dfa.cc (INCLUDE_MEMORY): Remove.
* tree-diagnostic-client-data-hooks.cc (INCLUDE_MEMORY): Remove.
* tree-diagnostic.cc (INCLUDE_MEMORY): Remove.
* tree-dump.cc (INCLUDE_MEMORY): Remove.
* tree-if-conv.cc (INCLUDE_MEMORY): Remove.
* tree-inline.cc (INCLUDE_MEMORY): Remove.
* tree-into-ssa.cc (INCLUDE_MEMORY): Remove.
* tree-logical-location.cc (INCLUDE_MEMORY): Remove.
* tree-loop-distribution.cc (INCLUDE_MEMORY): Remove.
* tree-nested.cc (INCLUDE_MEMORY): Remove.
* tree-nrv.cc (INCLUDE_MEMORY): Remove.
* tree-object-size.cc (INCLUDE_MEMORY): Remove.
* tree-outof-ssa.cc (INCLUDE_MEMORY): Remove.
* tree-parloops.cc (INCLUDE_MEMORY): Remove.
* tree-predcom.cc (INCLUDE_MEMORY): Remove.
* tree-pretty-print.cc (INCLUDE_MEMORY): Remove.
* tree-profile.cc (INCLUDE_MEMORY): Remove.
* tree-scalar-evolution.cc (INCLUDE_MEMORY): Remove.
* tree-sra.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-address.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-alias.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-ccp.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-coalesce.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-copy.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-dce.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-dom.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-dse.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-forwprop.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-ifcombine.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-live.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-ch.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-im.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-ivcanon.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-ivopts.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-manip.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-niter.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-prefetch.cc (INCLUDE_MEMORY): Remove.
* tree-ssa-loop-split.cc (INCLUDE_MEMORY): Remove.
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gcc/rust/ChangeLog:
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Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
|
|
This is a small improvement to the constant synthesis code to capture a case
appended to PR 109279.
The case in question has the property that the high 32 bits have the value one
less than the low 32 bits and the highest bit in two low 32 bits is on. The
example used in BZ is 0xcccccccccccccccd which comes up computing N/10.
When we construct a constant with bit 31 on, it gets implicitly sign extended.
So something like 0xcccccccd when constructed would generate
0xffffffffcccccccd. The low bits are precisely what we want and the high bits
are a "-1". Both properties are useful.
We left shift that value by 32 positions into a temporary and add that
temporary to the original value. Concretely:
0xffffffffcccccccd
+ 0xcccccccd00000000
------------------
0xcccccccccccccccd
Tested in my tester on rv32 and rv64, waiting on the pre-commit tester to do its thing.
PR target/109279
gcc/
* config/riscv/riscv.cc (riscv_build_integer): Handle another 64-bit
synthesis where high half is one less than the low half and the 32-bit
sign bit is on.
gcc/testsuite/
* gcc.target/riscv/synthesis-16.c: New test.
|
|
As hinted out in the BZ, we were missing a left shift in the constant synthesis
in the case where the upper 32 bits can be synthesized using a shNadd of the
low 32 bits.
This adjusts the synthesis to add the missing left shift and adjusts the cost
to account for the additional instruction.
Regression tested on riscv64-elf in my tester. Waiting for the pre-commit
tester before moving forward.
PR target/117690
gcc/
* config/riscv/riscv.cc (riscv_build_integer): Add missing left
shift when using shNadd to derive upper 32 bits from lower 32 bits.
gcc/testsuite
* gcc.target/riscv/pr117690.c: New test.
* gcc.target/riscv/synthesis-13.c: Adjust expected output.
|
|
patterns
So much like my patch from last week, this removes alternatives that
create multiple instructions that we really should have never needed.
In this case it fixes one of two bugs in pr116590. In particular we
don't want vmvNr instructions for thead-vector. Those instructions were
emitted as part of those two instruction sequences.
I've tested this in my tester and assuming the pre-commit tester is
happy, I'll push it to the trunk.
PR target/116590
gcc
* config/riscv/vector.md (pred_mul_<optab>mode_undef): Drop
unnecessary alternatives.
(pred_<madd_msub><mode>): Likewise.
(pred_<macc_msac><mode>): Likewise.
(pred_<madd_msub><mode>_scalar): Likewise.
(pred_<macc_msac><mode>_scalar): Likewise.
(pred_mul_neg_<optab><mode>_undef): Likewise.
(pred_<nmsub_nmadd><mode>): Likewise.
(pred_<nmsac_nmacc><mode>): Likewise.
(pred_<nmsub_nmadd><mode>_scalar): Likewise.
(pred_<nmsac_nmacc><mode>_scalar): Likewise.
gcc/testsuite
* gcc.target/riscv/pr116590.c: New test.
|
|
condition error
This patch fix the wrong condition for RVVMF2BF. It should be
TARGET_VECTOR_ELEN_BF_16.
gcc/ChangeLog:
PR target/117669
* config/riscv/vector-iterators.md:
Signed-off-by: Feng Wang <wangfeng@eswincomputing.com>
|
|
This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and
xsfvfnrclipxfqf extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New.
* config/riscv/riscv.opt: New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-sf-3.c: New test.
* gcc.target/riscv/predef-sf-4.c: New test.
* gcc.target/riscv/predef-sf-5.c: New test.
|
|
Andreas reported GCC mis-compiled GAS for risc-v Thankfully he also reduced it
to a nice little testcase.
So the whole point of the pattern in question is to "reduce" the constants by
right shifting away common unnecessary bits in RTL expressions like this:
> [(set (pc)
> (if_then_else (any_eq
> (and:ANYI (match_operand:ANYI 1 "register_operand" "r")
> (match_operand 2 "shifted_const_arith_operand" "i"))
> (match_operand 3 "shifted_const_arith_operand" "i"))
> (label_ref (match_operand 0 "" ""))
> (pc)))
When applicable, the reduced constants in operands 2/3 fit into a simm12 and
thus do not need multi-instruction synthesis. Note that we have to also shift
operand 1.
That shift should have been an arithmetic shift, but was incorrectly coded as a
logical shift.
Fixed with the obvious change on the right shift opcode.
Expecting to push to the trunk once the pre-commit tester renders its verdict.
I've already tested in this my tester for rv32 and rv64.
PR target/117649
gcc/
* config/riscv/riscv.md (branch on masked/shifted operands): Use
arithmetic rather than logical shift for operand 1.
gcc/testsuite
* gcc.target/riscv/branch-1.c: Update expected output.
* gcc.target/riscv/pr117649.c: New test.
|
|
When configuring GCC for RV32EC with:
./configure \
--target=riscv32-none-elf \
--with-multilib-generator="rv32ec-ilp32e--" \
--with-abi=ilp32e \
--with-arch=rv32ec
Then the build fails because division is erroneously left enabled:
cc1: error: '-mdiv' requires '-march' to subsume the 'M' extension
-fself-test: 8412281 pass(es) in 0.647173 seconds
Fix by disabling MASK_DIV if multiplication is not available and -mdiv
option has not been explicitly passed.
Tested the above RV32EC-only toolchain using the GNU simulator:
=== gcc Summary ===
# of expected passes 211635
# of unexpected failures 3004
# of expected failures 1061
# of unresolved testcases 5651
# of unsupported tests 18958
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_override_options_internal):
Set division option's default to disabled if multiplication
is not available.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
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Instead of loading the permutation indices and using vmslt in order to
determine which elements belong to which source vector we can compute
the proper mask at compile time. That way we can emit vlm instead of
vle + vmslt.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_merge_patterns): Load VLS
indices directly.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/merge-1.c: Check for vlm and
no vmsleu etc.
* gcc.target/riscv/rvv/autovec/vls/merge-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-6.c: Ditto.
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And stage3 begins...
Zdenek's fuzzer caught this one. Essentially using simplify_gen_subreg
directly with an offset of 0 when we just needed a lowpart.
The offset of 0 works for little endian, but for big endian it's simply wrong.
simplify_gen_subreg will return NULL_RTX because the case isn't representable.
We then embed that NULL_RTX into an insn that's later scanned during
mark_jump_label.
Scanning the port I see a couple more instances of this incorrect idiom. One
is pretty obvious to fix. The others look a bit goofy and I'll probably need
to sync with Patrick on them.
Anyway tested on riscv64-elf and riscv32-elf with no regressions. Pushing to
the trunk.
PR target/117595
gcc/
* config/riscv/sync.md (atomic_compare_and_swap<mode>): Use gen_lowpart
rather than simplify_gen_subreg.
* config/riscv/riscv.cc (riscv_legitimize_move): Similarly.
gcc/testsuite/
* gcc.target/riscv/pr117595.c: New test.
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This patch adds VLS modes to the strided load expanders.
gcc/ChangeLog:
* config/riscv/autovec.md: Add VLS modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.
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This patch adds else operands to masked loads. Currently the default
else operand predicate just accepts "undefined" (i.e. SCRATCH) values.
PR middle-end/115336
PR middle-end/116059
gcc/ChangeLog:
* config/riscv/autovec.md: Add else operand.
* config/riscv/predicates.md (maskload_else_operand): New
predicate.
* config/riscv/riscv-v.cc (get_else_operand): Remove static.
(expand_load_store): Use get_else_operand and adjust index.
(expand_gather_scatter): Ditto.
(expand_lanes_load_store): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr115336.c: New test.
* gcc.target/riscv/rvv/autovec/pr116059.c: New test.
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Updated version of my prior patch to fix type attributes on the
pre-allocation vector move pattern. This version just adds a suitable
set of attributes to a second pattern that was obviously wrong.
Passed on my tester for rv64 and rv32 crosses. Bootstrapped and
regression tested on riscv64-linux-gnu as well.
--
So I was looking into a horrific schedule for SAD a week or so ago and
came across this gem.
Basically we were treating a vector load as a vector move from a
scheduling standpoint during sched1. Naturally we didn't expose much
ILP during sched1. That in turn caused the register allocator to pack
the pseudos onto the physical vector registers tightly. regrename
didn't do anything useful and the resulting code had too many false
dependencies for sched2 to do anything useful.
As a result we were taking many load->use stalls in x264's SAD routine.
I'm confident the types are fine, but I'm a lot less sure about the
other attributes (mode, avl_type_index, mode_idx). If someone could
take a look at that, it'd be greatly appreciated.
There's other cases that may need similar treatment. But I didn't want
to muck with them until I understood those other attributes and how they
need adjustments.
In particular mov<VLS_AVL_REG:mode><P:mode>_lra appears to have the same
problem.
--
gcc/
* config/riscv/vector.md (mov<mode> pattern/splitter): Fix type and
other attributes.
(mov<VLS_AVL_REG:mode><P:mode>_lra): Likewise.
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error: unrecognizable insn:
(insn 35 34 36 2 (set (subreg:RVVM1SF (reg/v:RVVM1x4SF 142 [ _r ]) 0)
(unspec:RVVM1SF [
(const_vector:RVVM1SF repeat [
(const_double:SF 0.0 [0x0.0p+0])
])
(reg:DI 0 zero)
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_TH_VWLDST)) -1
(nil))
during RTL pass: mode_sw
PR target/116591
gcc/ChangeLog:
* config/riscv/vector.md: Add restriction to call pred_th_whole_mov.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr116591.c: New test.
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