index
:
riscv-gnu-toolchain/gcc.git
devel/analyzer
devel/autopar_devel
devel/autopar_europar_2021
devel/bypass-asm
devel/c++-contracts
devel/c++-coroutines
devel/c++-modules
devel/c++-name-lookup
devel/coarray_native
devel/fortran_unsigned
devel/gccgo
devel/gfortran-caf
devel/gimple-linterchange
devel/gomp-5_0-branch
devel/icpp2021
devel/ira-select
devel/ix86/evex512
devel/jlaw/crc
devel/loop-unswitch-support-switches
devel/lto-offload
devel/m2link
devel/modula-2
devel/mold-lto-plugin
devel/mold-lto-plugin-v2
devel/nothrow-detection
devel/omp/gcc-10
devel/omp/gcc-11
devel/omp/gcc-12
devel/omp/gcc-13
devel/omp/gcc-14
devel/omp/gcc-9
devel/omp/ompd
devel/power-ieee128
devel/range-gen3
devel/ranger
devel/rust/master
devel/sh-lra
devel/sphinx
devel/ssa-range
devel/subreg-coalesce
devel/unified-autovect
master
releases/egcs-1.0
releases/egcs-1.1
releases/gcc-10
releases/gcc-11
releases/gcc-12
releases/gcc-13
releases/gcc-14
releases/gcc-2.95
releases/gcc-2.95.2.1-branch
releases/gcc-3.0
releases/gcc-3.1
releases/gcc-3.2
releases/gcc-3.3
releases/gcc-3.4
releases/gcc-4.0
releases/gcc-4.1
releases/gcc-4.2
releases/gcc-4.3
releases/gcc-4.4
releases/gcc-4.5
releases/gcc-4.6
releases/gcc-4.7
releases/gcc-4.8
releases/gcc-4.9
releases/gcc-5
releases/gcc-6
releases/gcc-7
releases/gcc-8
releases/gcc-9
releases/libgcj-2.95
trunk
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
gcc
/
config
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2018-02-13
RISC-V: define _REENTRANT with -pthread
Andreas Schwab
1
-0
/
+2
2018-01-26
RISC-V: Allow register pairs for 64-bit target.
Jim Wilson
1
-0
/
+4
2018-01-26
RISC-V: Add --specs=nosys.specs support.
Jim Wilson
1
-1
/
+1
2018-01-23
RISC-V: Add -mpreferred-stack-boundary option.
Andrew Waterman
3
-5
/
+33
2018-01-17
RISC-V: Mark fsX as call clobbered when soft-float.
Andrew Waterman
1
-0
/
+7
2018-01-15
RISC-V: Increase mult/div cost if not implemented in hardware.
Andrew Waterman
1
-1
/
+7
2018-01-10
RISC-V: Add naked function support.
Kito Cheng
3
-18
/
+144
2018-01-08
RISC-V: Fix -msave-restore bug with sibcalls.
Jim Wilson
1
-16
/
+2
2018-01-03
Update copyright years.
Jakub Jelinek
20
-20
/
+20
2018-01-02
RISC-V: Fix for icache flush issue on multicore processors.
Andrew Waterman
2
-0
/
+8
2017-12-16
poly_int: IN_TARGET_CODE
Richard Sandiford
3
-0
/
+6
2017-12-07
Add srodata section support to riscv port.
Andrew Waterman
1
-0
/
+22
2017-12-04
Fix typos in riscv register save/restore.
Jim Wilson
2
-4
/
+4
2017-11-29
Riscv patterns to optimize away some redundant zero/sign extends.
Jim Wilson
2
-2
/
+73
2017-11-12
[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)
Tom de Vries
1
-6
/
+9
2017-11-08
RISC-V: Fix build error
Kito Cheng
3
-4
/
+6
2017-11-07
RISC-V: Implement movmemsi
Andrew Waterman
4
-4
/
+190
2017-11-07
RISC-V: Define MUSL_DYNAMIC_LINKER
Michael Clark
1
-0
/
+11
2017-11-05
RISC-V: Emit "i" suffix for instructions with immediate operands
Michael Clark
2
-19
/
+25
2017-11-05
RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune
Andrew Waterman
1
-1
/
+5
2017-11-05
RISC-V: Set SLOW_BYTE_ACCESS=1
Andrew Waterman
1
-1
/
+6
2017-11-03
RISC-V: Handle non-legitimate address in riscv_legitimize_move
Kito Cheng
1
-0
/
+16
2017-10-25
RISC-V: Add Sign/Zero extend patterns for PIC loads
Palmer Dabbelt
2
-2
/
+12
2017-10-23
Convert STARTING_FRAME_OFFSET to a hook
Richard Sandiford
1
-2
/
+0
2017-09-25
Turn CONSTANT_ALIGNMENT into a hook
Richard Sandiford
2
-16
/
+14
2017-09-15
Turn TRULY_NOOP_TRUNCATION into a hook
Richard Sandiford
2
-3
/
+2
2017-09-15
Turn CANNOT_CHANGE_MODE_CLASS into a hook
Richard Sandiford
2
-3
/
+11
2017-09-13
Turn SECONDARY_MEMORY_NEEDED into a hook
Richard Sandiford
2
-7
/
+17
2017-09-12
Turn HARD_REGNO_NREGS into a target hook
Richard Sandiford
3
-15
/
+14
2017-09-12
Turn SLOW_UNALIGNED_ACCESS into a target hook
Richard Sandiford
2
-6
/
+14
2017-09-04
Turn MODES_TIEABLE_P into a target hook
Richard Sandiford
2
-7
/
+16
2017-09-04
Turn HARD_REGNO_MODE_OK into a target hook
Richard Sandiford
3
-8
/
+6
2017-09-04
PR82045: Avoid passing machine modes through "..."
Richard Sandiford
1
-1
/
+1
2017-08-08
trans.c: Include header files.
Martin Liska
1
-0
/
+2
2017-07-27
Add RTEMS support
Sebastian Huber
1
-0
/
+31
2017-07-12
riscv.c: Remove unnecessary includes.
Jeff Law
2
-58
/
+3
2017-07-05
Remove enum before machine_mode
Richard Sandiford
2
-56
/
+56
2017-06-05
frame-header-opt.c: Include profile-count.h.
Jan Hubicka
1
-0
/
+1
2017-05-05
RISC-V: Add -mstrict-align option
Andrew Waterman
3
-7
/
+27
2017-05-05
RISC-V: Unify indention in riscv.md
Kito Cheng
1
-272
/
+287
2017-03-20
RISC-V: Don't prefer FP_REGS for integers
Palmer Dabbelt
1
-13
/
+0
2017-03-20
Use more conservative fences on RISC-V
Palmer Dabbelt
2
-2
/
+2
2017-03-14
Use gcc_fallthrough() instead of __attribute__((fallthrough)
Kito Cheng
1
-2
/
+2
2017-03-13
riscv.c (riscv_emit_float_compare): Use fallthru attribute rather than comments.
Jeff Law
1
-2
/
+2
2017-02-08
[riscv] Fix build due to INT16_MAX issue
Kyrylo Tkachov
1
-1
/
+3
2017-02-06
RISC-V Port: gcc
Palmer Dabbelt
23
-0
/
+8678