riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-25	RISC-V: Enable len_mask{load, store} and remove len_{load, store}	Juzhe-Zhong	1	-3/+7
2023-06-25	Revert "RISC-V:Add float16 tuple type abi"	Pan Li	1	-18/+13
2023-06-25	RISC-V:Add float16 tuple type abi	yulong	1	-13/+18
2023-06-24	RISC-V: Support RVV floating-point auto-vectorization	Juzhe-Zhong	1	-2/+2
2023-06-19	RISC-V: Bugfix for RVV widenning reduction in ZVE32/64	Pan Li	1	-84/+159
2023-06-19	RISC-V: Bugfix for RVV float reduction in ZVE32/64	Pan Li	1	-129/+234
2023-06-17	RISC-V: Bugfix for RVV integer reduction in ZVE32/64.	Pan Li	1	-58/+150
2023-06-06	RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.	Li Xu	1	-3/+3
2023-06-04	RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109	Juzhe-Zhong	1	-120/+0
2023-06-04	RISC-V: Move optimization patterns into autovec-opt.md	Juzhe-Zhong	1	-39/+0
2023-06-04	RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill	Pan Li	1	-0/+35
2023-06-03	RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizat...	Juzhe-Zhong	1	-1/+2
2023-06-02	RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization	Juzhe-Zhong	1	-4/+25
2023-05-31	RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)	Juzhe-Zhong	1	-3/+1
2023-05-31	RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening convers...	Juzhe-Zhong	1	-3/+1
2023-05-31	RISC-V: Remove FRM for vfncvt.rod instruction	Juzhe-Zhong	1	-3/+1
2023-05-29	RISC-V: Fix ternary instruction attribute bug	Juzhe-Zhong	1	-1/+1
2023-05-25	RISC-V: Remove FRM_REGNUM dependency for rtx conversions	Juzhe-Zhong	1	-9/+3
2023-05-24	RISC-V: Fix incorrect code of reaching inaccessible memory address	Juzhe-Zhong	1	-2/+2
2023-05-23	RISC-V: Fix warning of vxrm pattern	Juzhe-Zhong	1	-1/+1
2023-05-23	RISC-V: Refactor the framework of RVV auto-vectorization	Juzhe-Zhong	1	-30/+10
2023-05-17	RISC-V: Add mode switching target hook to insert rounding mode config for fix...	Juzhe-Zhong	1	-0/+29
2023-05-17	RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool1_t	Pan Li	1	-0/+10
2023-05-16	RISC-V: Add FRM and rounding mode operand into floating point intrinsics	Juzhe-Zhong	1	-48/+210
2023-05-15	RISC-V: Add rounding mode operand for fixed-point patterns	Juzhe-Zhong	1	-20/+54
2023-05-11	RISC-V: Update RVV integer compare simplification comments	Pan Li	1	-1/+8
2023-05-11	RISC-V: Clarify vlmax and length handling.	Robin Dapp	1	-5/+7
2023-05-06	RISC-V: Enable basic RVV auto-vectorization support.	Juzhe-Zhong	1	-1/+3
2023-05-05	RISC-V: Legitimise the const0_rtx for RVV indexed load/store	Pan Li	1	-31/+31
2023-05-03	RISC-V: Support segment intrinsics	Ju-Zhe Zhong	1	-63/+485
2023-05-03	RISC-V: Add tuple types support	Ju-Zhe Zhong	1	-0/+44
2023-04-28	RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR	Pan Li	1	-0/+32
2023-04-26	RISC-V: Fine tune vmadc/vmsbc RA constraint	Ju-Zhe Zhong	1	-88/+88
2023-04-26	RISC-V: Optimize comparison patterns for register allocation	Juzhe-Zhong	1	-88/+351
2023-04-26	RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen	Ju-Zhe Zhong	1	-8/+7
2023-04-26	RISC-V: Fine tune gather load RA constraint	Ju-Zhe Zhong	1	-27/+27
2023-04-24	RISC-V: Optimize fault only first load	Juzhe-Zhong	1	-1/+9
2023-04-19	RISC-V: Support 128 bit vector chunk	Juzhe-Zhong	1	-47/+186
2023-04-05	[PATCH] RISC-V: Fix SEW64 of vrsub.vx runtime fail in RV32 system	Ju-Zhe Zhong	1	-1/+1
2023-04-02	RISC-V: Fix reload fail issue on vector mac instructions	Juzhe-Zhong	1	-185/+205
2023-04-02	RISC-V: Fix ICE and codegen error of scalar move in RV32 system.	Juzhe-Zhong	1	-6/+2
2023-03-23	RISC-V: Fix LRA issue for LMUL < 1 vector spillings [PR109244]	Ju-Zhe Zhong	1	-0/+56
2023-03-23	RISC-V: Fix wrong vsetvli fusion for vmv.s.x	Ju-Zhe Zhong	1	-2/+2
2023-03-23	RISC-V: Fix wrong RTL pattern for ternary instructions.	Ju-Zhe Zhong	1	-149/+564
2023-03-17	RISC-V: Handle undef for vector mask patterns	Ju-Zhe Zhong	1	-542/+347
2023-03-14	RISC-V: Fine tunning merge operand constraint	Ju-Zhe Zhong	1	-445/+445
2023-03-14	RISC-V: Fine tune RA constraint for narrow instructions	Ju-Zhe Zhong	1	-84/+84
2023-03-10	RISC-V: Add fault first load C/C++ support	Ju-Zhe Zhong	1	-5/+48
2023-03-10	RISC-V: Fine tune merge operand constraint for integer/load/store	Ju-Zhe Zhong	1	-609/+634
2023-03-05	RISC-V: Add RVV misc intrinsic support	Ju-Zhe Zhong	1	-2/+132