riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-18	RISC-V: Rewrite some instructions using ASM targethook	Jun Sha (Joshua)	1	-0/+207
2024-01-18	RISC-V: Handle differences between XTheadvector and Vector	Jun Sha (Joshua)	1	-2/+21
2024-01-18	RISC-V: Adds the prefix "th." for the instructions of XTheadVector.	Jun Sha (Joshua)	1	-0/+13
2024-01-10	RISC-V: T-HEAD: Add support for the XTheadInt ISA extension	Jin Ma	1	-0/+77
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-12-07	RISC-V: xtheadfmemidx: Disable if xtheadmemidx is not available	Christoph Müllner	1	-1/+2
2023-11-19	[committed] RISC-V: Infrastructure for instruction fusion	Philipp Tomsich	1	-34/+0
2023-10-31	riscv: thead: Add support for the XTheadFMemIdx ISA extension	Christoph Müllner	1	-3/+66
2023-10-31	riscv: thead: Add support for the XTheadMemIdx ISA extension	Christoph Müllner	1	-0/+452
2023-10-09	THead: Fix missing CFI directives for th.sdd in prologue.	Xianmiao Qu	1	-5/+6
2023-07-12	riscv: xtheadmempair: Fix doc for th_mempair_order_operands()	Christoph Müllner	1	-2/+2
2023-07-12	riscv: xtheadmempair: Fix CFA reg notes	Christoph Müllner	1	-2/+6
2023-03-15	riscv: thead: Add support for the XTheadMemPair ISA extension	Christoph Müllner	1	-0/+427