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Age
Commit message (
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Author
Files
Lines
2024-04-11
RISC-V: Bugfix ICE for the vector return arg in mode switch
Pan Li
1
-2
/
+6
2024-04-08
RISC-V: Implement TLS Descriptors.
Tatsuyuki Ishi
1
-2
/
+7
2024-03-28
RISC-V: Add vxsat as a register
Palmer Dabbelt
1
-1
/
+1
2024-02-16
RISC-V: Add new option -march=help to print all supported extensions
Kito Cheng
1
-1
/
+6
2024-02-04
RISC-V: Support scheduling for sifive p400 series
Monk Chiang
1
-0
/
+1
2024-02-01
RISC-V: Support scheduling for sifive p600 series
Monk Chiang
1
-1
/
+3
2024-01-18
RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Jun Sha (Joshua)
1
-0
/
+4
2024-01-16
RISC-V: delete all the vector psabi checking.
Yanzhang Wang
1
-2
/
+0
2024-01-10
RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
Jin Ma
1
-0
/
+3
2024-01-03
Update copyright years.
Jakub Jelinek
1
-1
/
+1
2023-11-27
RISC-V: Initial RV64E and LP64E support
Tsukasa OI
1
-4
/
+13
2023-11-16
RISC-V: Implement target attribute
Kito Cheng
1
-0
/
+6
2023-10-31
riscv: thead: Add support for the XTheadFMemIdx ISA extension
Christoph Müllner
1
-0
/
+2
2023-10-31
riscv: thead: Add support for the XTheadMemIdx ISA extension
Christoph Müllner
1
-1
/
+3
2023-10-12
RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal...
Kito Cheng
1
-0
/
+5
2023-10-10
RISC-V: far-branch: Handle far jumps and branches for functions larger than 1MB
Andrew Waterman
1
-2
/
+2
2023-09-06
RISC-V: Part-3: Output .variant_cc directive for vector function
Lehua Ding
1
-0
/
+15
2023-09-06
RISC-V: Part-2: Save/Restore vector registers which need to be preversed
Lehua Ding
1
-0
/
+3
2023-09-06
RISC-V: Part-1: Select suitable vector registers for vector type args and ret...
Lehua Ding
1
-0
/
+25
2023-08-30
RISC-V: support cm.push cm.pop cm.popret in zcmp
Fei Gao
1
-0
/
+25
2023-08-29
RISC-V: generate builtin macro for compilation with strict alignment
Edwin Lu
1
-0
/
+1
2023-08-14
RISC-V: Enable compressible features when use ZC* extensions.
Jiawei
1
-1
/
+1
2023-08-10
RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
Pan Li
1
-1
/
+1
2023-07-20
RISC-V: Refactor RVV machine modes
Juzhe-Zhong
1
-0
/
+1
2023-07-12
riscv: Prepare backend for index registers
Christoph Müllner
1
-2
/
+4
2023-07-12
riscv: Define Xmode macro
Christoph Müllner
1
-0
/
+4
2023-06-29
RISC-V: Support vfadd static rounding mode by mode switching
Pan Li
1
-2
/
+2
2023-06-13
RISC-V: Add vector psabi checking.
Yanzhang Wang
1
-1
/
+4
2023-05-29
RISC-V: Using merge approach to optimize repeating sequence in vec_init
Pan Li
1
-0
/
+1
2023-05-17
RISC-V: Remove trailing spaces on lines.
Jin Ma
1
-1
/
+1
2023-05-17
RISC-V: Add mode switching target hook to insert rounding mode config for fix...
Juzhe-Zhong
1
-1
/
+5
2023-05-16
RISC-V: Add FRM and rounding mode operand into floating point intrinsics
Juzhe-Zhong
1
-2
/
+5
2023-05-15
RISC-V: Add rounding mode operand for fixed-point patterns
Juzhe-Zhong
1
-1
/
+4
2023-05-05
RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
Pan Li
1
-0
/
+5
2023-04-20
RISC-V: Fix RVV register order
Juzhe-Zhong
1
-7
/
+6
2023-03-23
RISC-V: Bugfix for rvv bool mode size adjustment
Pan Li
1
-0
/
+1
2023-03-07
RISC-V: Bugfix for rvv bool mode precision adjustment
Pan Li
1
-0
/
+1
2023-02-13
RISC-V: Handle vlenb correctly in unwinding
Kito Cheng
1
-0
/
+7
2023-02-12
RISC-V: Add integer widening instructions
Ju-Zhe Zhong
1
-3
/
+0
2023-02-10
RISC-V: Add binary vx C/C++ support
Ju-Zhe Zhong
1
-1
/
+1
2023-02-03
RISC-V: Remove unnecessary register class.
Monk Chiang
1
-7
/
+1
2023-01-02
Update copyright years.
Jakub Jelinek
1
-1
/
+1
2022-12-02
RISC-V: Add duplicate vector support.
Ju-Zhe Zhong
1
-0
/
+3
2022-11-18
RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori
Philipp Tomsich
1
-0
/
+8
2022-11-11
RISC-V: Add RVV registers register spilling
Ju-Zhe Zhong
1
-0
/
+3
2022-10-26
RISC-V: ADJUST_NUNITS according to -march.
Ju-Zhe Zhong
1
-0
/
+1
2022-10-26
RISC-V: Support load/store in mov<mode> pattern for RVV modes.
Ju-Zhe Zhong
1
-0
/
+2
2022-10-24
RISC-V: Fix REG_CLASS_CONTENTS.
Ju-Zhe Zhong
1
-1
/
+1
2022-10-05
RISC-V: Introduce RVV header to enable builtin types
Ju-Zhe Zhong
1
-0
/
+2
2022-09-23
RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand
Vineet Gupta
1
-6
/
+7
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