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AgeCommit message (Expand)AuthorFilesLines
2024-01-18RISC-V: Handle differences between XTheadvector and VectorJun Sha (Joshua)1-1/+2
2024-01-18RISC-V: Introduce XTheadVector as a subset of V1.0.0Jun Sha (Joshua)1-2/+6
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-20RISC-V: Support -mcmodel=large.Kuan-Lin Chen1-0/+4
2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-1/+2
2023-11-16RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]Edwin Lu1-3/+3
2023-11-08RISC-V: Eliminate unused parameter warning.xuli1-1/+1
2023-11-06RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsicxuli1-1/+35
2023-08-29RISC-V: generate builtin macro for compilation with strict alignmentEdwin Lu1-0/+7
2023-08-14RISC-V: Enable compressible features when use ZC* extensions.Jiawei1-1/+1
2023-03-28RISC-V: Define __riscv_v_intrinsic [PR109312]Kito Cheng1-4/+14
2023-03-05RISC-V: Add RVV misc intrinsic supportJu-Zhe Zhong1-0/+20
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-10-27RISC-V: Target support for z*inx extension.Jiawei1-1/+1
2022-10-10RISC-V: Add newline to the end of file [NFC]Kito Cheng1-1/+1
2022-10-05RISC-V: Introduce RVV header to enable builtin typesJu-Zhe Zhong1-0/+41
2022-10-05RISC-V: remove deprecate pic code model macroVineet Gupta1-5/+0
2022-03-21RISC-V: Implement misc macro for vector extensions.Kito Cheng1-0/+18
2022-01-21PR middle-end/104140: bootstrap ICE on riscv.Roger Sayle1-0/+3
2022-01-17Rename .c files to .cc files.Martin Liska1-0/+136