riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-12-15	[PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors	Mary Bennett	1	-7/+8
2023-12-15	Re: [PATCH] RISC-V: fix scalar crypto patterns	Jeff Law	1	-8/+0
2023-11-30	RISC-V: Rename vconstraint into group_overlap	Juzhe-Zhong	1	-6/+6
2023-11-29	RISC-V: Support highpart register overlap for vwcvt	Juzhe-Zhong	1	-0/+23
2023-10-31	riscv: thead: Add support for the XTheadMemIdx ISA extension	Christoph Müllner	1	-0/+26
2023-10-11	[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	1	-0/+7
2023-09-21	RISC-V: Optimized for strided load/store with stride == element width[PR111450]	xuli	1	-0/+20
2023-08-25	[PATCH v10] RISC-V: Add support for the Zfa extension	Jin Ma	1	-8/+13
2023-05-19	RISC-V: Remove masking third operand of rotate instructions	Joern Rennecke	1	-2/+2
2023-03-15	riscv: thead: Add support for the XTheadFmv ISA extension	Christoph Müllner	1	-0/+8
2023-03-06	RISC-V: Implement ZKND and ZKNE extensions	Liao Shihua	1	-0/+8
2023-03-05	RISC-V: Add scalar move support and fix VSETVL bugs	Ju-Zhe Zhong	1	-0/+6
2023-02-12	RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support	Ju-Zhe Zhong	1	-13/+0
2023-02-10	RISC-V: Add binary vx C/C++ support	Ju-Zhe Zhong	1	-2/+15
2023-02-01	RISC-V: Add integer binary vv C/C++ API support	Ju-Zhe Zhong	1	-0/+10
2023-01-16	Update copyright years.	Jakub Jelinek	1	-1/+1
2022-12-02	RISC-V: Add duplicate vector support.	Ju-Zhe Zhong	1	-0/+5
2022-10-27	RISC-V: Limit regs use for z*inx extension.	Jiawei	1	-2/+3
2022-10-26	RISC-V: Support load/store in mov<mode> pattern for RVV modes.	Ju-Zhe Zhong	1	-0/+22
2022-09-01	RISC-V: Add RVV constraints.	zhongjuzhe	1	-0/+20
2022-08-24	[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand	Andrew Pinski	1	-0/+10
2022-08-24	[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask	Andrew Pinski	1	-0/+12
2022-08-24	[RISCV] Use constraints/predicates instead of checking const_int directly for...	Andrew Pinski	1	-0/+6
2022-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2021-07-13	docs: Add 'S' to Machine Constraints for RISC-V	Kito Cheng	1	-2/+1
2021-01-04	Update copyright years.	Jakub Jelinek	1	-1/+1
2020-01-01	Update copyright years.	Jakub Jelinek	1	-1/+1
2019-04-30	RISC-V: Short-forward-branch opt for SiFive 7 series cores.	Andrew Waterman	1	-0/+5
2019-01-01	Update copyright years.	Jakub Jelinek	1	-1/+1
2018-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2017-02-06	RISC-V Port: gcc	Palmer Dabbelt	1	-0/+78