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2024-05-28i386: Improve access to _Atomic DImode location via XMM regs for SSE4.1 ↵Uros Bizjak1-8/+28
x86_32 targets Use MOVD/PEXTRD and MOVD/PINSRD insn sequences to move DImode value between XMM and GPR register sets for SSE4.1 x86_32 targets in order to avoid spilling the value to stack. The load from _Atomic location a improves from: movq a, %xmm0 movq %xmm0, (%esp) movl (%esp), %eax movl 4(%esp), %edx to: movq a, %xmm0 movd %xmm0, %eax pextrd $1, %xmm0, %edx The store to _Atomic location b improves from: movl %eax, (%esp) movl %edx, 4(%esp) movq (%esp), %xmm0 movq %xmm0, b to: movd %eax, %xmm0 pinsrd $1, %edx, %xmm0 movq %xmm0, b gcc/ChangeLog: * config/i386/sync.md (atomic_loaddi_fpu): Use movd/pextrd to move DImode value from XMM to GPR for TARGET_SSE4_1. (atomic_storedi_fpu): Use movd/pinsrd to move DImode value from GPR to XMM for TARGET_SSE4_1.
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-07-18Add peephole to eliminate redundant comparison after cmpccxadd.liuhongt1-1/+159
Similar like we did for cmpxchg, but extended to all ix86_comparison_int_operator since cmpccxadd set EFLAGS exactly same as CMP. When operand order in compare insn is same as that in cmpccxadd, compare insn can be eliminated directly. When operand order is swapped in compare insn, only optimize cmpccxadd + cmpl + jcc/setcc to cmpccxadd + jcc/setcc when FLAGS_REG is dead after jcc/setcc. gcc/ChangeLog: PR target/110591 * config/i386/sync.md (cmpccxadd_<mode>): Adjust the pattern to explicitly set FLAGS_REG like *cmp<mode>_1, also add extra 3 define_peephole2 after the pattern. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110591.c: New test. * gcc.target/i386/pr110591-2.c: New test.
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-11-08Revert "i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor}"konglin11-24/+3
This reverts commit 48fa4131e419942efc9dd762694fdc7e819de392.
2022-11-07i386: Prefer remote atomic insn for atomic_fetch{add, and, or, xor}konglin11-3/+24
Add flag -mprefer-remote-atomic to control whether to generate raoint insn for atomic operations. gcc/ChangeLog: * config/i386/i386.opt:Add -mprefer-remote-atomic. * config/i386/sync.md (atomic_<plus_logic><mode>): New define_expand. (atomic_add<mode>): Rename to below one. (atomic_add<mode>_1): To this. (atomic_<logic><mode>): Ditto. (atomic_<logic><mode>_1): Ditto. * doc/invoke.texi: Add -mprefer-remote-atomic. gcc/testsuite/ChangeLog: * gcc.target/i386/raoint-atomic-fetch.c: New test.
2022-11-07Support Intel RAO-INTkonglin11-0/+16
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect raoint. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET, OPTION_MASK_ISA2_RAOINT_UNSET): New. (ix86_handle_option): Handle -mraoint. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_RAOINT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for raoint. * config.gcc: Add raointintrin.h * config/i386/cpuid.h (bit_RAOINT): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __RAOINT__. * config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Add -mraoint. * config/i386/sync.md (rao_a<raointop><mode>): New define insn. * config/i386/i386.opt: Add option -mraoint. * config/i386/x86gprintrin.h: Include raointintrin.h. * doc/extend.texi: Document raoint. * doc/invoke.texi: Document -mraoint. * doc/sourcebuild.texi: Document target raoint. * config/i386/raointintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mraoint. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mraoint. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add raoint target. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: Add check_effective_target_raoint. * gcc.target/i386/rao-helper.h: New test. * gcc.target/i386/raoint-1.c: Ditto. * gcc.target/i386/raoint-aadd-2.c: Ditto. * gcc.target/i386/raoint-aand-2.c: Ditto. * gcc.target/i386/raoint-aor-2.c: Ditto. * gcc.target/i386/raoint-axor-2.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2022-11-04Support Intel CMPccXADDHaochen Jiang1-0/+28
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_CMPCCXADD_SET, OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. (ix86_handle_option): Handle -mcmpccxadd. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_CMPCCXADD. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for cmpccxadd. * config.gcc: Add cmpccxaddintrin.h. * config/i386/cpuid.h (bit_CMPCCXADD): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT) and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __CMPCCXADD__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Add new parameter to indicate constant position. Handle INT_FTYPE_PINT_INT_INT_INT and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT. * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD). * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd. (ix86_valid_target_attribute_inner_p): Handle cmpccxadd. * config/i386/i386.opt: Add option -mcmpccxadd. * config/i386/sync.md (cmpccxadd_<mode>): New define insn. * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h. * doc/extend.texi: Document cmpccxadd. * doc/invoke.texi: Document -mcmpccxadd. * doc/sourcebuild.texi: Document target cmpccxadd. * config/i386/cmpccxaddintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mcmpccxadd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-13.c: Add -mcmpccxadd. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto. * lib/target-supports.exp (check_effective_target_cmpccxadd): New. * gcc.target/i386/cmpccxadd-1.c: New test. * gcc.target/i386/cmpccxadd-2.c: Ditto.
2022-05-30i386: Remove constraints when used with constant integer predicates, take 2Uros Bizjak1-2/+2
const_int_operand and other const*_operand predicates do not need constraints when the constraint is inherited from the range of constant integer predicate. Remove the constraint in case all alternatives use the same inherited constraint. However, when there are operands, commitative with a non-constant operand, the operand effectively matches e.g. nonimmediate_operand|const_int_operand rather than just const_int_operand. We should keep the constraint for const_int_operand that are in a % pair. See PR 105624. 2022-05-30 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386.md: Remove constraints when used with const_int_operand, const0_operand, const_1_operand, constm1_operand, const8_operand, const128_operand, const248_operand, const123_operand, const2367_operand, const1248_operand, const359_operand, const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, const_0_to_255_mul_8_operand, const_1_to_31_operand, const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, const_24_to_27_operand and const_28_to_31_operand. * config/i386/mmx.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/subst.md: Ditto. * config/i386/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr105624.c: New test.
2022-05-17i386: Fix ICE in final_scan_insn_1 [PR105624]Uros Bizjak1-2/+2
Apparently const_int_operand and other const*_operand predicates do need constraints. Revert the offending patch that caused ICE. 2022-05-17 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/105624 Revert: * config/i386/i386.md: Remove constraints when used with const_int_operand, const0_operand, const_1_operand, constm1_operand, const8_operand, const128_operand, const248_operand, const123_operand, const2367_operand, const1248_operand, const359_operand, const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, const_0_to_255_mul_8_operand, const_1_to_31_operand, const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, const_24_to_27_operand and const_28_to_31_operand. * config/i386/mmx.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/subst.md: Ditto. * config/i386/sync.md: Ditto. gcc/testsuite/ChangeLog: PR target/105624 * gcc.target/i386/pr105624.c: New test.
2022-05-15i386: Remove constraints when used with constant integer predicates.Uros Bizjak1-2/+2
const_int_operand and other const*_operand predicates do not need constraints when the constraint is inherited from the range of constant integer predicate. Remove the constraint in case all alternatives use the same inherited constraint. 2022-05-15 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386.md: Remove constraints when used with const_int_operand, const0_operand, const_1_operand, constm1_operand, const8_operand, const128_operand, const248_operand, const123_operand, const2367_operand, const1248_operand, const359_operand, const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, const_0_to_255_mul_8_operand, const_1_to_31_operand, const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, const_24_to_27_operand and const_28_to_31_operand. * config/i386/mmx.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/subst.md: Ditto. * config/i386/sync.md: Ditto.
2022-02-22i386: Relax cmpxchg instruction under -mrelax-cmpxchg-loop [PR103069]Hongyu Wang1-23/+42
For cmpxchg, it is commonly used in spin loop, and several user code such as pthread directly takes cmpxchg as loop condition, which cause huge cache bouncing. This patch extends previous implementation to relax all cmpxchg instruction under -mrelax-cmpxchg-loop with an extra atomic load, compare and emulate the failed cmpxchg behavior. For original spin loop which looks like loop: mov %eax,%r8d or $1,%r8d lock cmpxchg %r8d,(%rdi) jne loop It will now truns to loop: mov %eax,%r8d or $1,%r8d mov (%r8),%rsi <--- load lock first cmp %rsi,%rax <--- compare with expected input jne .L2 <--- lock ne expected lock cmpxchg %r8d,(%rdi) jne loop L2: mov %rsi,%rax <--- perform the behavior of failed cmpxchg jne loop under -mrelax-cmpxchg-loop. gcc/ChangeLog: PR target/103069 * config/i386/i386-expand.cc (ix86_expand_atomic_fetch_op_loop): Split atomic fetch and loop part. (ix86_expand_cmpxchg_loop): New expander for cmpxchg loop. * config/i386/i386-protos.h (ix86_expand_cmpxchg_loop): New prototype. * config/i386/sync.md (atomic_compare_and_swap<mode>): Call new expander under TARGET_RELAX_CMPXCHG_LOOP. (atomic_compare_and_swap<mode>): Likewise for doubleword modes. gcc/testsuite/ChangeLog: PR target/103069 * gcc.target/i386/pr103069-2.c: Adjust result check. * gcc.target/i386/pr103069-3.c: New test. * gcc.target/i386/pr103069-4.c: Likewise.
2022-01-03i386, fab: Optimize __atomic_{add,sub,and,or,xor}_fetch (x, y, z) ↵Jakub Jelinek1-0/+104
{==,!=,<,<=,>,>=} 0 [PR98737] On Wed, Jan 27, 2021 at 12:27:13PM +0100, Ulrich Drepper via Gcc-patches wrote: > On 1/27/21 11:37 AM, Jakub Jelinek wrote: > > Would equality comparison against 0 handle the most common cases. > > > > The user can write it as > > __atomic_sub_fetch (x, y, z) == 0 > > or > > __atomic_fetch_sub (x, y, z) - y == 0 > > thouch, so the expansion code would need to be able to cope with both. > > Please also keep !=0, <0, <=0, >0, and >=0 in mind. They all can be > useful and can be handled with the flags. <= 0 and > 0 don't really work well with lock {add,sub,inc,dec}, x86 doesn't have comparisons that would look solely at both SF and ZF and not at other flags (and emitting two separate conditional jumps or two setcc insns and oring them together looks awful). But the rest can work. Here is a patch that adds internal functions and optabs for these, recognizes them at the same spot as e.g. .ATOMIC_BIT_TEST_AND* internal functions (fold all builtins pass) and expands them appropriately (or for the <= 0 and > 0 cases of +/- FAILs and let's middle-end fall back). So far I have handled just the op_fetch builtins, IMHO instead of handling also __atomic_fetch_sub (x, y, z) - y == 0 etc. we should canonicalize __atomic_fetch_sub (x, y, z) - y to __atomic_sub_fetch (x, y, z) (and vice versa). 2022-01-03 Jakub Jelinek <jakub@redhat.com> PR target/98737 * internal-fn.def (ATOMIC_ADD_FETCH_CMP_0, ATOMIC_SUB_FETCH_CMP_0, ATOMIC_AND_FETCH_CMP_0, ATOMIC_OR_FETCH_CMP_0, ATOMIC_XOR_FETCH_CMP_0): New internal fns. * internal-fn.h (ATOMIC_OP_FETCH_CMP_0_EQ, ATOMIC_OP_FETCH_CMP_0_NE, ATOMIC_OP_FETCH_CMP_0_LT, ATOMIC_OP_FETCH_CMP_0_LE, ATOMIC_OP_FETCH_CMP_0_GT, ATOMIC_OP_FETCH_CMP_0_GE): New enumerators. * internal-fn.c (expand_ATOMIC_ADD_FETCH_CMP_0, expand_ATOMIC_SUB_FETCH_CMP_0, expand_ATOMIC_AND_FETCH_CMP_0, expand_ATOMIC_OR_FETCH_CMP_0, expand_ATOMIC_XOR_FETCH_CMP_0): New functions. * optabs.def (atomic_add_fetch_cmp_0_optab, atomic_sub_fetch_cmp_0_optab, atomic_and_fetch_cmp_0_optab, atomic_or_fetch_cmp_0_optab, atomic_xor_fetch_cmp_0_optab): New direct optabs. * builtins.h (expand_ifn_atomic_op_fetch_cmp_0): Declare. * builtins.c (expand_ifn_atomic_op_fetch_cmp_0): New function. * tree-ssa-ccp.c: Include internal-fn.h. (optimize_atomic_bit_test_and): Add . before internal fn call in function comment. Change return type from void to bool and return true only if successfully replaced. (optimize_atomic_op_fetch_cmp_0): New function. (pass_fold_builtins::execute): Use optimize_atomic_op_fetch_cmp_0 for BUILT_IN_ATOMIC_{ADD,SUB,AND,OR,XOR}_FETCH_{1,2,4,8,16} and BUILT_IN_SYNC_{ADD,SUB,AND,OR,XOR}_AND_FETCH_{1,2,4,8,16}, for *XOR* ones only if optimize_atomic_bit_test_and failed. * config/i386/sync.md (atomic_<plusminus_mnemonic>_fetch_cmp_0<mode>, atomic_<logic>_fetch_cmp_0<mode>): New define_expand patterns. (atomic_add_fetch_cmp_0<mode>_1, atomic_sub_fetch_cmp_0<mode>_1, atomic_<logic>_fetch_cmp_0<mode>_1): New define_insn patterns. * doc/md.texi (atomic_add_fetch_cmp_0<mode>, atomic_sub_fetch_cmp_0<mode>, atomic_and_fetch_cmp_0<mode>, atomic_or_fetch_cmp_0<mode>, atomic_xor_fetch_cmp_0<mode>): Document new named patterns. * gcc.target/i386/pr98737-1.c: New test. * gcc.target/i386/pr98737-2.c: New test. * gcc.target/i386/pr98737-3.c: New test. * gcc.target/i386/pr98737-4.c: New test. * gcc.target/i386/pr98737-5.c: New test. * gcc.target/i386/pr98737-6.c: New test. * gcc.target/i386/pr98737-7.c: New test.
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-15PR target/103069: Relax cmpxchg loop for x86 targetHongyu Wang1-0/+117
From the CPU's point of view, getting a cache line for writing is more expensive than reading. See Appendix A.2 Spinlock in: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ xeon-lock-scaling-analysis-paper.pdf The full compare and swap will grab the cache line exclusive and causes excessive cache line bouncing. The atomic_fetch_{or,xor,and,nand} builtins generates cmpxchg loop under -march=x86-64 like: movl v(%rip), %eax .L2: movl %eax, %ecx movl %eax, %edx orl $1, %ecx lock cmpxchgl %ecx, v(%rip) jne .L2 movl %edx, %eax andl $1, %eax ret To relax above loop, GCC should first emit a normal load, check and jump to .L2 if cmpxchgl may fail. Before jump to .L2, PAUSE should be inserted to yield the CPU to another hyperthread and to save power, so the code is like .L84: movl (%rdi), %ecx movl %eax, %edx orl %esi, %edx cmpl %eax, %ecx jne .L82 lock cmpxchgl %edx, (%rdi) jne .L84 .L82: rep nop jmp .L84 This patch adds corresponding atomic_fetch_op expanders to insert load/ compare and pause for all the atomic logic fetch builtins. Add flag -mrelax-cmpxchg-loop to control whether to generate relaxed loop. gcc/ChangeLog: PR target/103069 * config/i386/i386-expand.c (ix86_expand_atomic_fetch_op_loop): New expand function. * config/i386/i386-options.c (ix86_target_string): Add -mrelax-cmpxchg-loop flag. (ix86_valid_target_attribute_inner_p): Likewise. * config/i386/i386-protos.h (ix86_expand_atomic_fetch_op_loop): New expand function prototype. * config/i386/i386.opt: Add -mrelax-cmpxchg-loop. * config/i386/sync.md (atomic_fetch_<logic><mode>): New expander for SI,HI,QI modes. (atomic_<logic>_fetch<mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. (atomic_fetch_<logic><mode>): New expander for DI,TI modes. (atomic_<logic>_fetch<mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. * doc/invoke.texi: Document -mrelax-cmpxchg-loop. gcc/testsuite/ChangeLog: PR target/103069 * gcc.target/i386/pr103069-1.c: New test. * gcc.target/i386/pr103069-2.c: Ditto.
2021-11-15i386: Fix up x86 atomic_bit_test* expanders for !TARGET_HIMODE_MATH [PR103205]Jakub Jelinek1-3/+3
With !TARGET_HIMODE_MATH, the OPTAB_DIRECT expand_simple_binop fail and so we ICE. We don't really care if they are done promoted in SImode instead. 2021-11-15 Jakub Jelinek <jakub@redhat.com> PR target/103205 * config/i386/sync.md (atomic_bit_test_and_set<mode>, atomic_bit_test_and_complement<mode>, atomic_bit_test_and_reset<mode>): Use OPTAB_WIDEN instead of OPTAB_DIRECT. * gcc.target/i386/pr103205.c: New test.
2021-07-20i386: Remove atomic_storedi_fpu and atomic_loaddi_fpu peepholes [PR100182]Uros Bizjak1-152/+0
These patterns result in non-atomic sequence. 2021-07-21 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/100182 * config/i386/sync.md (define_peephole2 atomic_storedi_fpu): Remove. (define_peephole2 atomic_loaddi_fpu): Ditto. gcc/testsuite/ PR target/100182 * gcc.target/i386/pr71245-1.c: Remove. * gcc.target/i386/pr71245-2.c: Ditto.
2021-04-23i386: Fix atomic FP peepholes [PR100182]Uros Bizjak1-8/+16
64bit loads to/stores from x87 and SSE registers are atomic also on 32-bit targets, so there is no need for additional atomic moves to a temporary register. Introduced load peephole2 patterns assume that there won't be any additional loads from the load location outside the peepholed sequence and wrongly removed the source location initialization. OTOH, introduced store peephole2 patterns assume there won't be any additional loads from the stored location outside the peepholed sequence and wrongly removed the destination location initialization. Note that we can't use plain x87 FST instruction to initialize destination location because FST converts the value to the double-precision format, changing bits during move. The patch restores removed initializations in load and store patterns. Additionally, plain x87 FST in store peephole2 patterns is prevented by limiting the store operand source to SSE registers. 2021-04-23 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/100182 * config/i386/sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2): Copy operand 3 to operand 4. Use sse_reg_operand as operand 3 predicate. (FILD_ATOMIC/FIST_ATOMIC FP load peephole2 with mem blockage): Ditto. (LDX_ATOMIC/STX_ATOMIC FP load peephole2): Ditto. (LDX_ATOMIC/LDX_ATOMIC FP load peephole2 with mem blockage): Ditto. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2): Copy operand 1 to operand 0. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2 with mem blockage): Ditto. (LDX_ATOMIC/STX_ATOMIC FP store peephole2): Ditto. (LDX_ATOMIC/LDX_ATOMIC FP store peephole2 with mem blockage): Ditto. gcc/testsuite/ PR target/100182 * gcc.target/i386/pr100182.c: New test. * gcc.target/i386/pr71245-1.c (dg-final): Xfail scan-assembler-not. * gcc.target/i386/pr71245-2.c (dg-final): Ditto.
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-07-24i386: Emit mfence_sse2 for -Os [PR95750]Uros Bizjak1-1/+2
2020-07-24 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/95750 * config/i386/sync.md (mmem_thread_fence): Emit mfence_sse2 for -Os.
2020-07-21i386: Fix insn conditions of mfence patterns [PR95750]Uros Bizjak1-4/+2
2020-07-21 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/95750 * config/i386/sync.md (mfence_sse2): Enable for TARGET_64BIT and TARGET_SSE2. (mfence_nosse): Always enable.
2020-07-20i386: Use lock prefixed insn instead of MFENCE [PR95750]Uros Bizjak1-7/+14
Currently, __atomic_thread_fence(seq_cst) on x86 and x86-64 generates mfence instruction. A dummy atomic instruction (a lock-prefixed instruction or xchg with a memory operand) would provide the same sequential consistency guarantees while being more efficient on most current CPUs. The mfence instruction additionally orders non-temporal stores, which is not relevant for atomic operations and are not ordered by seq_cst atomic operations anyway. 2020-07-20 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/95750 * config/i386/i386.h (TARGET_AVOID_MFENCE): Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE. * config/i386/sync.md (mfence_sse2): Disable for TARGET_AVOID_MFENCE. (mfence_nosse): Enable also for TARGET_AVOID_MFENCE. Emit stack referred memory in word_mode. (mem_thread_fence): Do not generate mfence_sse2 pattern when TARGET_AVOID_MFENCE is true. (atomic_store<mode>): Update for rename. * config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE): Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE. gcc/testsuite/ChangeLog: PR target/95750 * gcc.target/i386/pr95750.c: New test.
2020-07-16i386: Additional peephole2 to use flags from CMPXCHG more [PR96189]Uros Bizjak1-0/+34
CMPXCHG instruction sets ZF flag if the values in the destination operand and EAX register are equal; otherwise the ZF flag is cleared and value from destination operand is loaded to EAX. Following assembly: xorl %eax, %eax lock cmpxchgl %edx, (%rdi) testl %eax, %eax sete %al can be optimized by removing the unneeded comparison, since set ZF flag signals that no update to EAX happened. This patch adds peephole2 pattern to also handle XOR zeroing and load of -1 by OR. 2020-07-16 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/96189 * config/i386/sync.md (peephole2 to remove unneded compare after CMPXCHG): New pattern, also handle XOR zeroing and load of -1 by OR. gcc/testsuite/ChangeLog: PR target/96189 * gcc.target/i386/pr96189-1.c: New test.
2020-07-15i386: Introduce peephole2 to use flags from CMPXCHG more [PR96189]Uros Bizjak1-0/+35
CMPXCHG instruction sets ZF flag if the values in the destination operand and EAX register are equal; otherwise the ZF flag is cleared and value from destination operand is loaded to EAX. Following assembly: movl %esi, %eax lock cmpxchgl %edx, (%rdi) cmpl %esi, %eax sete %al can be optimized by removing the unneeded comparison, since set ZF flag signals that no update to EAX happened. 2020-15-07 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/95355 * config/i386/sync.md (peephole2 to remove unneded compare after CMPXCHG): New pattern. gcc/testsuite/ChangeLog: PR target/95355 * gcc.target/i386/pr96189.c: New test.
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r279813
2019-09-16* config/i386/sync.md (atomic_store<mode>): Improve comment.Uros Bizjak1-2/+2
From-SVN: r275755
2019-09-16re PR target/91719 (gcc compiles seq_cst store on x86-64 differently from ↵Uros Bizjak1-2/+5
clang/icc) PR target/91719 * config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro. * config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New. * config/i386/sync.md (atomic_store<mode>): emit XCHG for TARGET_USE_XCHG_FOR_ATOMIC_STORE. From-SVN: r275754
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r267494
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-10-14sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2): Use ↵Uros Bizjak1-8/+92
any_fp_register_operand as operand[3] predicate. * config/i386/sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2): Use any_fp_register_operand as operand[3] predicate. Simplify equality test for operands[2] and operands[4] memory location. (LDX_ATOMIC/STX_ATOMIC FP load peephole2): Ditto. (FILD_ATOMIC/FIST_ATOMIC FP load peephole2 with mem blockage): New. (LDX_ATOMIC/LDX_ATOMIC FP load peephole2 with mem blockage): Ditto. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2): Use any_fp_register_operand as operand[1] predicate. Simplify equality test for operands[0] and operands[3] memory location. (LDX_ATOMIC/STX_ATOMIC FP store peephole2): Ditto. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2 with mem blockage): New. (LDX_ATOMIC/LDX_ATOMIC FP storepeephole2 with mem blockage): Ditto. From-SVN: r253751
2017-05-11re PR target/80706 (peephole2 uses uninitialized stack variables on i686)Uros Bizjak1-15/+46
PR target/80706 * config/i386/sync.md (UNSPEC_LDX_ATOMIC): New unspec. (UNSPEC_STX_ATOMIC): Ditto. (loaddi_via_sse): New insn. (storedi_via_sse): Ditto. (atomic_loaddi_fpu): Emit loaddi_via_sse and storedi_via_sse. Update corresponding peephole2 patterns. (atomic_storedi_fpu): Ditto. testsuite/ChangeLog: PR target/80706 * gcc.target/i386/pr80706.c: New test. From-SVN: r247921
2017-02-19Revert:Uros Bizjak1-1/+1
2016-05-30 Uros Bizjak <ubizjak@gmail.com> * config/i386/sync.md (mfence_nosse): Use "lock orl $0, -4(%esp)". From-SVN: r245577
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r243994
2016-05-30sync.md (mfence_nosse): Use "lock orl $0, -4(%esp)".Uros Bizjak1-1/+1
* config/i386/sync.md (mfence_nosse): Use "lock orl $0, -4(%esp)". From-SVN: r236895
2016-05-29re PR target/71245 (std::atomic<double> load/store bounces the data to the ↵Uros Bizjak1-0/+56
stack using fild/fistp) PR target/71245 * config/i386/sync.md (define_peephole2 atomic_storedi_fpu): New peepholes to remove unneeded fild/fistp pairs. (define_peephole2 atomic_loaddi_fpu): Ditto. testsuite/ChangeLog: PR target/71245 * gcc.target/i386/pr71245-1.c: New test. * gcc.target/i386/pr71245-2.c: Ditto. From-SVN: r236863
2016-05-03re PR target/49244 (__sync or __atomic builtins will not emit 'lock ↵Jakub Jelinek1-0/+111
bts/btr/btc') PR target/49244 * tree-ssa-ccp.c: Include stor-layout.h and optabs-query.h. (optimize_atomic_bit_test_and): New function. (pass_fold_builtins::execute): Use it. * optabs.def (atomic_bit_test_and_set_optab, atomic_bit_test_and_complement_optab, atomic_bit_test_and_reset_optab): New optabs. * internal-fn.def (ATOMIC_BIT_TEST_AND_SET, ATOMIC_BIT_TEST_AND_COMPLEMENT, ATOMIC_BIT_TEST_AND_RESET): New ifns. * builtins.h (expand_ifn_atomic_bit_test_and): New prototype. * builtins.c (expand_ifn_atomic_bit_test_and): New function. * internal-fn.c (expand_ATOMIC_BIT_TEST_AND_SET, expand_ATOMIC_BIT_TEST_AND_COMPLEMENT, expand_ATOMIC_BIT_TEST_AND_RESET): New functions. * doc/md.texi (atomic_bit_test_and_set@var{mode}, atomic_bit_test_and_complement@var{mode}, atomic_bit_test_and_reset@var{mode}): Document. * config/i386/sync.md (atomic_bit_test_and_set<mode>, atomic_bit_test_and_complement<mode>, atomic_bit_test_and_reset<mode>): New expanders. (atomic_bit_test_and_set<mode>_1, atomic_bit_test_and_complement<mode>_1, atomic_bit_test_and_reset<mode>_1): New insns. * gcc.target/i386/pr49244-1.c: New test. * gcc.target/i386/pr49244-2.c: New test. From-SVN: r235813
2016-04-28re PR target/70821 (x86_64: __atomic_fetch_add/sub() uses XADD rather than ↵Jakub Jelinek1-0/+30
DECL in some cases) PR target/70821 * config/i386/sync.md (define_peephole2 *atomic_fetch_add_cmp<mode>): Add new peephole2 where the first insn is *mov<mode>_or instead of *mov<mode>_internal. * gcc.target/i386/pr70821.c: New test. From-SVN: r235586
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r232055
2015-05-12re PR target/65697 (__atomic memory barriers not strong enough for __sync ↵Andrew MacLeod1-5/+5
builtins) 2015-05-12 Andrew MacLeod <amacleod@redhat.com> PR target/65697 * coretypes.h (MEMMODEL_SYNC, MEMMODEL_BASE_MASK): New macros. (enum memmodel): Add SYNC_{ACQUIRE,RELEASE,SEQ_CST}. * tree.h (memmodel_from_int, memmodel_base, is_mm_relaxed, is_mm_consume,is_mm_acquire, is_mm_release, is_mm_acq_rel, is_mm_seq_cst, is_mm_sync): New accessor functions. * builtins.c (expand_builtin_sync_operation, expand_builtin_compare_and_swap): Use MEMMODEL_SYNC_SEQ_CST. (expand_builtin_sync_lock_release): Use MEMMODEL_SYNC_RELEASE. (get_memmodel, expand_builtin_atomic_compare_exchange, expand_builtin_atomic_load, expand_builtin_atomic_store, expand_builtin_atomic_clear): Use new accessor routines. (expand_builtin_sync_synchronize): Use MEMMODEL_SYNC_SEQ_CST. * optabs.c (expand_compare_and_swap_loop): Use MEMMODEL_SYNC_SEQ_CST. (maybe_emit_sync_lock_test_and_set): Use new accessors and MEMMODEL_SYNC_ACQUIRE. (expand_sync_lock_test_and_set): Use MEMMODEL_SYNC_ACQUIRE. (expand_mem_thread_fence, expand_mem_signal_fence, expand_atomic_load, expand_atomic_store): Use new accessors. * emit-rtl.c (need_atomic_barrier_p): Add additional enum cases. * tsan.c (instrument_builtin_call): Update check for memory model beyond final enum to use MEMMODEL_LAST. * c-family/c-common.c: Use new accessor for memmodel_base. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Use new accessors. * config/aarch64/atomics.md (atomic_load<mode>,atomic_store<mode>, arch64_load_exclusive<mode>, aarch64_store_exclusive<mode>, mem_thread_fence, *dmb): Likewise. * config/alpha/alpha.c (alpha_split_compare_and_swap, alpha_split_compare_and_swap_12): Likewise. * config/arm/arm.c (arm_expand_compare_and_swap, arm_split_compare_and_swap, arm_split_atomic_op): Likewise. * config/arm/sync.md (atomic_load<mode>, atomic_store<mode>, atomic_loaddi): Likewise. * config/i386/i386.c (ix86_destroy_cost_data, ix86_memmodel_check): Likewise. * config/i386/sync.md (mem_thread_fence, atomic_store<mode>): Likewise. * config/ia64/ia64.c (ia64_expand_atomic_op): Add new memmodel cases and use new accessors. * config/ia64/sync.md (mem_thread_fence, atomic_load<mode>, atomic_store<mode>, atomic_compare_and_swap<mode>, atomic_exchange<mode>): Use new accessors. * config/mips/mips.c (mips_process_sync_loop): Likewise. * config/pa/pa.md (atomic_loaddi, atomic_storedi): Likewise. * config/rs6000/rs6000.c (rs6000_pre_atomic_barrier, rs6000_post_atomic_barrier): Add new cases. (rs6000_expand_atomic_compare_and_swap): Use new accessors. * config/rs6000/sync.md (mem_thread_fence): Add new cases. (atomic_load<mode>): Add new cases and use new accessors. (store_quadpti): Add new cases. * config/s390/s390.md (mem_thread_fence, atomic_store<mode>): Use new accessors. * config/sparc/sparc.c (sparc_emit_membar_for_model): Use new accessors. * doc/extend.texi: Update docs to indicate 16 bits are used for memory model, not 8. From-SVN: r223096
2015-04-02sync.md (UNSPEC_FILD_ATOMIC, [...]): New.Uros Bizjak1-2/+7
* config/i386/sync.md (UNSPEC_FILD_ATOMIC, UNSPEC_FIST_ATOMIC): New. (loaddi_via_fpu): Use UNSPEC_FILD_ATOMIC. (storedi_via_fpu): Use UNSPEC_FIST_ATOMIC. * reg-stack.c (get_true_reg): Change UNSPEC_LDA to UNSPEC_FILD_ATOMIC. (subst_stack_regs_pat): Change UNSPEC_STA to UNSPEC_FIST_ATOMIC. From-SVN: r221830
2015-04-01sync.md (UNSPEC_MOVA): Remove.Uros Bizjak1-11/+25
* config/i386/sync.md (UNSPEC_MOVA): Remove. (atomic_load<mode>): Change operand 0 predicate to nonimmediate_operand and fix up the destination when needed. Use UNSPEC_LDA. (atomic_loaddi_fpu): Use UNSPEC_LDA. (atomic_store<mode>): Change operand 1 predicate to nonimmendate_operand and move the source to register when needed. Use UNSPEC_STA. (atomic_store<mode>_1): Use UNSPEC_STA. (atomic_storedi_fpu): Change operand 1 to nonimmediate_operand. Fix moves from memory operand. Use UNSPEC_STA. From-SVN: r221811
2015-03-31re PR target/58945 (Improve atomic_compare_and_swap*_doubleword pattern)Uros Bizjak1-39/+25
PR target/58945 * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): Do not split operands 0 and operands 2 to halfmode. (atomic_compare_and_swap<mode>): Update for atomic_compare_and_swap<dwi>_doubleword changes. From-SVN: r221798
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r219188
2014-10-29decl.c, [...]: Remove redundant enum from machine_mode.Richard Sandiford1-1/+1
gcc/ada/ * gcc-interface/decl.c, gcc-interface/gigi.h, gcc-interface/misc.c, gcc-interface/trans.c, gcc-interface/utils.c, gcc-interface/utils2.c: Remove redundant enum from machine_mode. gcc/c-family/ * c-common.c, c-common.h, c-cppbuiltin.c, c-lex.c: Remove redundant enum from machine_mode. gcc/c/ * c-decl.c, c-tree.h, c-typeck.c: Remove redundant enum from machine_mode. gcc/cp/ * constexpr.c: Remove redundant enum from machine_mode. gcc/fortran/ * trans-types.c, trans-types.h: Remove redundant enum from machine_mode. gcc/go/ * go-lang.c: Remove redundant enum from machine_mode. gcc/java/ * builtins.c, java-tree.h, typeck.c: Remove redundant enum from machine_mode. gcc/lto/ * lto-lang.c: Remove redundant enum from machine_mode. gcc/ * addresses.h, alias.c, asan.c, auto-inc-dec.c, bt-load.c, builtins.c, builtins.h, caller-save.c, calls.c, calls.h, cfgexpand.c, cfgloop.h, cfgrtl.c, combine.c, compare-elim.c, config/aarch64/aarch64-builtins.c, config/aarch64/aarch64-protos.h, config/aarch64/aarch64-simd.md, config/aarch64/aarch64.c, config/aarch64/aarch64.h, config/aarch64/aarch64.md, config/alpha/alpha-protos.h, config/alpha/alpha.c, config/arc/arc-protos.h, config/arc/arc.c, config/arc/arc.h, config/arc/predicates.md, config/arm/aarch-common-protos.h, config/arm/aarch-common.c, config/arm/arm-protos.h, config/arm/arm.c, config/arm/arm.h, config/arm/arm.md, config/arm/neon.md, config/arm/thumb2.md, config/avr/avr-log.c, config/avr/avr-protos.h, config/avr/avr.c, config/avr/avr.md, config/bfin/bfin-protos.h, config/bfin/bfin.c, config/c6x/c6x-protos.h, config/c6x/c6x.c, config/c6x/c6x.md, config/cr16/cr16-protos.h, config/cr16/cr16.c, config/cris/cris-protos.h, config/cris/cris.c, config/cris/cris.md, config/darwin-protos.h, config/darwin.c, config/epiphany/epiphany-protos.h, config/epiphany/epiphany.c, config/epiphany/epiphany.md, config/fr30/fr30.c, config/frv/frv-protos.h, config/frv/frv.c, config/frv/predicates.md, config/h8300/h8300-protos.h, config/h8300/h8300.c, config/i386/i386-builtin-types.awk, config/i386/i386-protos.h, config/i386/i386.c, config/i386/i386.md, config/i386/predicates.md, config/i386/sse.md, config/i386/sync.md, config/ia64/ia64-protos.h, config/ia64/ia64.c, config/iq2000/iq2000-protos.h, config/iq2000/iq2000.c, config/iq2000/iq2000.md, config/lm32/lm32-protos.h, config/lm32/lm32.c, config/m32c/m32c-protos.h, config/m32c/m32c.c, config/m32r/m32r-protos.h, config/m32r/m32r.c, config/m68k/m68k-protos.h, config/m68k/m68k.c, config/mcore/mcore-protos.h, config/mcore/mcore.c, config/mcore/mcore.md, config/mep/mep-protos.h, config/mep/mep.c, config/microblaze/microblaze-protos.h, config/microblaze/microblaze.c, config/mips/mips-protos.h, config/mips/mips.c, config/mmix/mmix-protos.h, config/mmix/mmix.c, config/mn10300/mn10300-protos.h, config/mn10300/mn10300.c, config/moxie/moxie.c, config/msp430/msp430-protos.h, config/msp430/msp430.c, config/nds32/nds32-cost.c, config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c, config/nds32/nds32-protos.h, config/nds32/nds32.c, config/nios2/nios2-protos.h, config/nios2/nios2.c, config/pa/pa-protos.h, config/pa/pa.c, config/pdp11/pdp11-protos.h, config/pdp11/pdp11.c, config/rl78/rl78-protos.h, config/rl78/rl78.c, config/rs6000/altivec.md, config/rs6000/rs6000-c.c, config/rs6000/rs6000-protos.h, config/rs6000/rs6000.c, config/rs6000/rs6000.h, config/rx/rx-protos.h, config/rx/rx.c, config/s390/predicates.md, config/s390/s390-protos.h, config/s390/s390.c, config/s390/s390.h, config/s390/s390.md, config/sh/predicates.md, config/sh/sh-protos.h, config/sh/sh.c, config/sh/sh.md, config/sparc/predicates.md, config/sparc/sparc-protos.h, config/sparc/sparc.c, config/sparc/sparc.md, config/spu/spu-protos.h, config/spu/spu.c, config/stormy16/stormy16-protos.h, config/stormy16/stormy16.c, config/tilegx/tilegx-protos.h, config/tilegx/tilegx.c, config/tilegx/tilegx.md, config/tilepro/tilepro-protos.h, config/tilepro/tilepro.c, config/v850/v850-protos.h, config/v850/v850.c, config/v850/v850.md, config/vax/vax-protos.h, config/vax/vax.c, config/vms/vms-c.c, config/xtensa/xtensa-protos.h, config/xtensa/xtensa.c, coverage.c, cprop.c, cse.c, cselib.c, cselib.h, dbxout.c, ddg.c, df-problems.c, dfp.c, dfp.h, doc/md.texi, doc/rtl.texi, doc/tm.texi, doc/tm.texi.in, dojump.c, dse.c, dwarf2cfi.c, dwarf2out.c, dwarf2out.h, emit-rtl.c, emit-rtl.h, except.c, explow.c, expmed.c, expmed.h, expr.c, expr.h, final.c, fixed-value.c, fixed-value.h, fold-const.c, function.c, function.h, fwprop.c, gcse.c, gengenrtl.c, genmodes.c, genopinit.c, genoutput.c, genpreds.c, genrecog.c, gensupport.c, gimple-ssa-strength-reduction.c, graphite-clast-to-gimple.c, haifa-sched.c, hooks.c, hooks.h, ifcvt.c, internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c, ira-emit.c, ira-int.h, ira-lives.c, ira.c, ira.h, jump.c, langhooks.h, libfuncs.h, lists.c, loop-doloop.c, loop-invariant.c, loop-iv.c, loop-unroll.c, lower-subreg.c, lower-subreg.h, lra-assigns.c, lra-constraints.c, lra-eliminations.c, lra-int.h, lra-lives.c, lra-spills.c, lra.c, lra.h, machmode.h, omp-low.c, optabs.c, optabs.h, output.h, postreload.c, print-tree.c, read-rtl.c, real.c, real.h, recog.c, recog.h, ree.c, reg-stack.c, regcprop.c, reginfo.c, regrename.c, regs.h, reload.c, reload.h, reload1.c, rtl.c, rtl.h, rtlanal.c, rtlhash.c, rtlhooks-def.h, rtlhooks.c, sched-deps.c, sel-sched-dump.c, sel-sched-ir.c, sel-sched-ir.h, sel-sched.c, simplify-rtx.c, stmt.c, stor-layout.c, stor-layout.h, target.def, targhooks.c, targhooks.h, tree-affine.c, tree-call-cdce.c, tree-complex.c, tree-data-ref.c, tree-dfa.c, tree-if-conv.c, tree-inline.c, tree-outof-ssa.c, tree-scalar-evolution.c, tree-ssa-address.c, tree-ssa-ccp.c, tree-ssa-loop-ivopts.c, tree-ssa-loop-ivopts.h, tree-ssa-loop-manip.c, tree-ssa-loop-prefetch.c, tree-ssa-math-opts.c, tree-ssa-reassoc.c, tree-ssa-sccvn.c, tree-streamer-in.c, tree-switch-conversion.c, tree-vect-data-refs.c, tree-vect-generic.c, tree-vect-loop.c, tree-vect-patterns.c, tree-vect-slp.c, tree-vect-stmts.c, tree-vrp.c, tree.c, tree.h, tsan.c, ubsan.c, valtrack.c, var-tracking.c, varasm.c: Remove redundant enum from machine_mode. gcc/ * gengtype.c (main): Treat machine_mode as a scalar typedef. * genmodes.c (emit_insn_modes_h): Hide inline functions if USED_FOR_TARGET. From-SVN: r216834
2014-10-15re PR go/59432 (sync/atomic FAILs on 32bit x86 systems without .cfi directives)Uros Bizjak1-45/+11
PR go/59432 * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): Remove the second alternative. (regprefix): Remove mode attribute. (atomic_compare_and_swap<mode>): Do not fixup operand 2. * config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Remove. Revert: 2013-11-05 Ian Lance Taylor <iant@google.com> * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): If possible, add .cfi directives to record change to bx. * config/i386/i386.c (ix86_emit_cfi): New function. * config/i386/i386-protos.h (ix86_emit_cfi): Declare. From-SVN: r216281
2014-01-02Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r206289
2013-11-06sync.md (atomic_compare_and_swap<dwi>_doubleword): If possible, add .cfi ↵Ian Lance Taylor1-2/+13
directives to record change to bx. * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): If possible, add .cfi directives to record change to bx. * config/i386/i386.c (ix86_emit_cfi): New function. * config/i386/i386-protos.h (ix86_emit_cfi): Declare. From-SVN: r204433
2013-01-17re PR target/55981 (std::atomic store is split in two smaller stores)Uros Bizjak1-9/+6
PR target/55981 * config/i386/sync.md (atomic_store<mode>): Always generate SWImode store through atomic_store<mode>_1. (atomic_store<mode>_1): Macroize insn using SWI mode iterator. testsuite/ChangeLog: PR target/55981 * gcc.target/pr55981.c: New test. From-SVN: r195273
2013-01-14re PR target/55948 (__atomic_clear / __atomic_store_n ignore HLE_RELEASE flags)Uros Bizjak1-2/+14
PR target/55948 * config/i386/sync.md (atomic_store<mode>_1): New pattern. (atomic_store<mode>): Call atomic_store<mode>_1 for IX86_HLE_RELEASE memmodel flag. testsuite/ChangeLog PR target/55948 * gcc.target/i386/hle-clear-rel.c: New file * gcc.target/i386/hle-store-rel.c: New file. From-SVN: r195155
2013-01-13sync.md (mem_thread_fence): Mask operands[0] with MEMMODEL_MASK to determine ↵Uros Bizjak1-2/+4
memory model. * config/i386/sync.md (mem_thread_fence): Mask operands[0] with MEMMODEL_MASK to determine memory model. (atomic_store<mode>): Ditto from operands[2]. * config/i386/i386.c (ix86_memmodel_check): Declare "strong" as bool. From-SVN: r195137
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