aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/i386/immintrin.h
AgeCommit message (Collapse)AuthorFilesLines
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang1-0/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_COMPLEX. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-complex. * config.gcc: Add amxcomplexintrin.h. * config/i386/cpuid.h (bit_AMX_COMPLEX): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_COMPLEX__. * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-complex. * config/i386/i386.opt: Add option -mamx-complex. * config/i386/immintrin.h: Include amxcomplexintrin.h. * doc/extend.texi: Document amx-complex. * doc/invoke.texi: Document -mamx-complex. * doc/sourcebuild.texi: Document target amx-complex. * config/i386/amxcomplexintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-complex. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX. * gcc.target/i386/amx-helper.h: Add amx-complex support. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-complex. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-complex. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_complex): New. * gcc.target/i386/amxcomplex-asmatt-1.c: New test. * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto. * gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto.
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-11-04Support Intel AMX-FP16 ISAHongyu Wang1-0/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect amx-fp16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET, OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros. (ix86_handle_option): Handle -mamx-fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_FP16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-fp16. * config.gcc: Add amxfp16intrin.h. * config/i386/cpuid.h (bit_AMX_FP16): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_FP16__. * config/i386/i386-isa.def: Add DEF_PTA for AMX_FP16. * config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16. (ix86_valid_target_attribute_inner_p): Add new ATTR. (ix86_option_override_internal): Handle AMX-FP16. * config/i386/i386.opt: Add -mamx-fp16. * config/i386/immintrin.h: Include amxfp16intrin.h. * doc/extend.texi: Document -mamx-fp16. * doc/invoke.texi: Document amx-fp16. * doc/sourcebuild.texi: Document amx_fp16. * config/i386/amxfp16intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-fp16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_amx_fp16): New proc. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: Add AMX_FP16. * gcc.target/i386/amx-helper.h: New file to support amx-fp16. * gcc.target/i386/amxfp16-asmatt-1.c: New test. * gcc.target/i386/amxfp16-asmintel-1.c: Ditto. * gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-31Support Intel AVX-NE-CONVERTkonglin11-0/+2
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXNECONVERT_SET, OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New. (ix86_handle_option): Handle -mavxneconvert, unset avxneconvert when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXNECONVERT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxneconvert. * common/config/i386/cpuinfo.h (get_available_features): Detect avxneconvert. * config.gcc: Add avxneconvertintrin.h * config/i386/avxneconvertintrin.h: New. * config/i386/avx512bf16vlintrin.h (_mm256_cvtneps_pbh): Unified builtin with avxneconvert. (_mm_cvtneps_pbh): Ditto. * config/i386/cpuid.h (bit_AVXNECONVERT): New. * config/i386/i386-builtin-types.def: Add DEF_POINTER_TYPE (PCV8HF, V8HF, CONST), DEF_POINTER_TYPE (PCV8BF, V8BF, CONST), DEF_POINTER_TYPE (PCV16HF, V16HF, CONST), DEF_POINTER_TYPE (PCV16BF, V16BF, CONST), DEF_FUNCTION_TYPE (V4SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCV8BF), DEF_FUNCTION_TYPE (V4SF, PCV8HF), DEF_FUNCTION_TYPE (V8SF, PCV16HF), DEF_FUNCTION_TYPE (V8SF, PCV16BF), * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXNECONVERT__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Handle V4SF_FTYPE_PCBFLOAT16,V8SF_FTYPE_PCBFLOAT16, V4SF_FTYPE_PCFLOAT16, V8SF_FTYPE_PCFLOAT16,V4SF_FTYPE_PCV8BF, V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF. * config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New. * config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert. (ix86_valid_target_attribute_inner_p): Handle avxneconvert. * config/i386/i386.md: Add attr avx512bf16vl and avxneconvert. * config/i386/i386.opt: Add option -mavxneconvert. * config/i386/immintrin.h: Inculde avxneconvertintrin.h. * config/i386/sse.md (vbcstnebf162ps_<mode>): New define_insn. (vbcstnesh2ps_<mode>): Ditto. (vcvtnee<bf16_ph>2ps_<mode>):Ditto. (vcvtneo<bf16_ph>2ps_<mode>):Ditto. (vcvtneps2bf16_v4sf): Ditto. (*vcvtneps2bf16_v4sf): Ditto. (vcvtneps2bf16_v8sf): Ditto. * doc/invoke.texi: Document -mavxneconvert. * doc/extend.texi: Document avxneconvert. * doc/sourcebuild.texi: Document target avxneconvert. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-check.h: Add avxneconvert check. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxneconvert. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp:add check_effective_target_avxneconvert. * gcc.target/i386/avx-ne-convert-1.c: New test. * gcc.target/i386/avx-ne-convert-vbcstnebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vbcstnesh2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneeph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneobf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneoph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneps2bf16-2.c: Ditto. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Rename.. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: To this. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: New test.
2022-10-31i386:: using __bf16 for AVX512BF16 intrinsicskonglin11-0/+2
gcc/ChangeLog: * config/i386/avx512bf16intrin.h (__attribute__): Change short to bf16. (_mm_cvtsbh_ss): Ditto. (_mm512_cvtne2ps_pbh): Ditto. (_mm512_mask_cvtne2ps_pbh): Ditto. (_mm512_maskz_cvtne2ps_pbh): Ditto. * config/i386/avx512bf16vlintrin.h (__attribute__): Ditto. (_mm256_cvtne2ps_pbh): Ditto. (_mm256_mask_cvtne2ps_pbh): Ditto. (_mm256_maskz_cvtne2ps_pbh): Ditto. (_mm_cvtne2ps_pbh): Ditto. (_mm_mask_cvtne2ps_pbh): Ditto. (_mm_maskz_cvtne2ps_pbh): Ditto. (_mm_cvtness_sbh): Ditto. * config/i386/i386-builtin-types.def (V8BF): Add new DEF_VECTOR_TYPE for BFmode. (V16BF): Ditto. (V32BF): Ditto. * config/i386/i386-builtin.def (BDESC): Fixed builtins. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Changed avx512bf16 ix86_builtin_func_type included HI to BF. * config/i386/immintrin.h: Add SSE2 depend for avx512bf16. * config/i386/sse.md (TARGET_AVX512VL): Changed HI vector to BF vector. (avx512f_cvtneps2bf16_v4sf): New define_expand. (*avx512f_cvtneps2bf16_v4sf): New define_insn. (avx512f_cvtneps2bf16_v4sf_maskz):Ditto. (avx512f_cvtneps2bf16_v4sf_mask): Ditto. (avx512f_cvtneps2bf16_v4sf_mask_1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bf16-cvtsbh2ss-1.c: Add fpmath option. * gcc.target/i386/avx512bf16-vdpbf16ps-2.c: Fixed scan-assembler. * gcc.target/i386/avx512bf16vl-cvtness2sbh-1.c: Add x/y suffix for vcvtneps2bf16. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Ditto.
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling1-0/+2
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint8. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT8. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint8. * config.gcc: Add avxvnniint8intrin.h. * config/i386/avxvnniint8intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT8): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT8__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8. (ix86_valid_target_attribute_inner_p): Handle avxvnniint8. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New.. * config/i386/i386.opt: Add option -mavxvnniint8. * config/i386/immintrin.h: Include avxvnniint8intrin.h. * config/i386/sse.md (UNSPEC_VPMADDUBSWACCD UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD, UNSPEC_VPMADDWDACCSSD): Rename according to new style. (vpdp<vpdotprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint8. * doc/invoke.texi: Document -mavxvnniint8. * doc/sourcebuild.texi: Document target avxvnniint8. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint8. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint8 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint8. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint8): New. * gcc.target/i386/avxvnniint8-1.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-21Support Intel AVX-IFMAHongyu Wang1-0/+2
gcc/ * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, OPTION_MASK_ISA2_AVX2_UNSET): New macro. (ix86_handle_option): Handle -mavxifma. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXIFMA. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxifma. * common/config/i386/cpuinfo.h (get_available_features): Detect avxifma. * config.gcc: Add avxifmaintrin.h * config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change to macro. (_mm_madd52hi_epu64): Likewise. (_mm256_madd52lo_epu64): Likewise. (_mm256_madd52hi_epu64): Likewise. * config/i386/avxifmaintrin.h: New header. * config/i386/cpuid.h (bit_AVXIFMA): New. * config/i386/i386-builtin.def: Add new builtins, and correct pattern names for AVX512IFMA. * config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA builtins like AVX-VNNI. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXIFMA__. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Relax ISA masks for AVXIFMA. * config/i386/i386-isa.def: Add AVXIFMA. * config/i386/i386-options.cc (isa2_opts): Add -mavxifma. (ix86_valid_target_attribute_inner_p): Handle avxifma. * config/i386/i386.md (isa): Add attr avxifma and avxifmavl. * config/i386/i386.opt: Add option -mavxifma. * config/i386/immintrin.h: Inculde avxifmaintrin.h. * config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>): Remove. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove. (vpamdd52huq<mode>_maskz): Rename to ... (vpmadd52huq<mode>_maskz): ... this. (vpamdd52luq<mode>_maskz): Rename to ... (vpmadd52luq<mode>_maskz): ... this. (vpmadd52<vpmadd52type><mode>): New define_insn. (vpmadd52<vpmadd52type>v8di): Likewise. (vpmadd52<vpmadd52type><mode>_maskz_1): Likewise. (vpamdd52<vpmadd52type><mode>_mask): Rename to ... (vpmadd52<vpmadd52type><mode>_mask): ... this. * doc/invoke.texi: Document -mavxifma. * doc/extend.texi: Document avxifma. * doc/sourcebuild.texi: Document target avxifma. gcc/testsuite/ * gcc.target/i386/avx-check.h: Add avxifma check. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane.. * gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test. * gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto. * gcc.target/i386/avx-ifma-1.c: Ditto. * gcc.target/i386/avx-ifma-2.c: Ditto. * gcc.target/i386/avx-ifma-3.c: Ditto. * gcc.target/i386/avx-ifma-4.c: Ditto. * gcc.target/i386/avx-ifma-5.c: Ditto. * gcc.target/i386/avx-ifma-6.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/sse-12.c: Add -mavxifma. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxifma): New.
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-09-09AVX512FP16: Add vaddph/vsubph/vdivph/vmulph.liuhongt1-0/+2
gcc/ChangeLog: * config.gcc: Add avx512fp16vlintrin.h. * config/i386/avx512fp16intrin.h: (_mm512_add_ph): New intrinsic. (_mm512_mask_add_ph): Likewise. (_mm512_maskz_add_ph): Likewise. (_mm512_sub_ph): Likewise. (_mm512_mask_sub_ph): Likewise. (_mm512_maskz_sub_ph): Likewise. (_mm512_mul_ph): Likewise. (_mm512_mask_mul_ph): Likewise. (_mm512_maskz_mul_ph): Likewise. (_mm512_div_ph): Likewise. (_mm512_mask_div_ph): Likewise. (_mm512_maskz_div_ph): Likewise. (_mm512_add_round_ph): Likewise. (_mm512_mask_add_round_ph): Likewise. (_mm512_maskz_add_round_ph): Likewise. (_mm512_sub_round_ph): Likewise. (_mm512_mask_sub_round_ph): Likewise. (_mm512_maskz_sub_round_ph): Likewise. (_mm512_mul_round_ph): Likewise. (_mm512_mask_mul_round_ph): Likewise. (_mm512_maskz_mul_round_ph): Likewise. (_mm512_div_round_ph): Likewise. (_mm512_mask_div_round_ph): Likewise. (_mm512_maskz_div_round_ph): Likewise. * config/i386/avx512fp16vlintrin.h: New header. * config/i386/i386-builtin-types.def (V16HF, V8HF, V32HF): Add new builtin types. * config/i386/i386-builtin.def: Add corresponding builtins. * config/i386/i386-expand.c (ix86_expand_args_builtin): Handle new builtin types. (ix86_expand_round_builtin): Likewise. * config/i386/immintrin.h: Include avx512fp16vlintrin.h * config/i386/sse.md (VFH): New mode_iterator. (VF2H): Likewise. (avx512fmaskmode): Add HF vector modes. (avx512fmaskhalfmode): Likewise. (<plusminus_insn><mode>3<mask_name><round_name>): Adjust to for HF vector modes. (*<plusminus_insn><mode>3<mask_name><round_name>): Likewise. (mul<mode>3<mask_name><round_name>): Likewise. (*mul<mode>3<mask_name><round_name>): Likewise. (div<mode>3): Likewise. (<sse>_div<mode>3<mask_name><round_name>): Likewise. * config/i386/subst.md (SUBST_V): Add HF vector modes. (SUBST_A): Likewise. (round_mode512bit_condition): Adjust for V32HFmode. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add -mavx512vl and test for new intrinsics. * gcc.target/i386/avx-2.c: Add -mavx512vl. * gcc.target/i386/avx512fp16-11a.c: New test. * gcc.target/i386/avx512fp16-11b.c: Ditto. * gcc.target/i386/avx512vlfp16-11a.c: Ditto. * gcc.target/i386/avx512vlfp16-11b.c: Ditto. * gcc.target/i386/sse-13.c: Add test for new builtins. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add test for new intrinsics. * gcc.target/i386/sse-22.c: Ditto.
2021-09-08AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 ↵Guo, Xuepeng1-0/+4
instructions. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect FEATURE_AVX512FP16. * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512FP16_SET, OPTION_MASK_ISA_AVX512FP16_UNSET, OPTION_MASK_ISA2_AVX512FP16_SET, OPTION_MASK_ISA2_AVX512FP16_UNSET): New. (OPTION_MASK_ISA2_AVX512BW_UNSET, OPTION_MASK_ISA2_AVX512BF16_UNSET): Add AVX512FP16. (ix86_handle_option): Handle -mavx512fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX512FP16. * common/config/i386/i386-isas.h: Add entry for AVX512FP16. * config.gcc: Add avx512fp16intrin.h. * config/i386/avx512fp16intrin.h: New intrinsic header. * config/i386/cpuid.h: Add bit_AVX512FP16. * config/i386/i386-builtin-types.def: (FLOAT16): New primitive type. * config/i386/i386-builtins.c: Support _Float16 type for i386 backend. (ix86_register_float16_builtin_type): New function. (ix86_float16_type_node): New. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512FP16__. * config/i386/i386-expand.c (ix86_expand_branch): Support HFmode. (ix86_prepare_fp_compare_args): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_expand_fp_movcc): Ditto. * config/i386/i386-isa.def: Add PTA define for AVX512FP16. * config/i386/i386-options.c (isa2_opts): Add -mavx512fp16. (ix86_valid_target_attribute_inner_p): Add avx512fp16 attribute. * config/i386/i386.c (ix86_get_ssemov): Use vmovdqu16/vmovw/vmovsh for HFmode/HImode scalar or vector. (ix86_get_excess_precision): Use FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 when TARGET_AVX512FP16 existed. (sse_store_index): Use SFmode cost for HFmode cost. (inline_memory_move_cost): Add HFmode, and perfer SSE cost over GPR cost for HFmode. (ix86_hard_regno_mode_ok): Allow HImode in sse register. (ix86_mangle_type): Add manlging for _Float16 type. (inline_secondary_memory_needed): No memory is needed for 16bit movement between gpr and sse reg under TARGET_AVX512FP16. (ix86_multiplication_cost): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_division_cost): Ditto. (ix86_rtx_costs): Ditto. (ix86_add_stmt_cost): Ditto. (ix86_optab_supported_p): Ditto. * config/i386/i386.h (VALID_AVX512F_SCALAR_MODE): Add HFmode. (SSE_FLOAT_MODE_SSEMATH_OR_HF_P): Add HFmode. (PTA_SAPPHIRERAPIDS): Add PTA_AVX512FP16. * config/i386/i386.md (mode): Add HFmode. (MODE_SIZE): Add HFmode. (isa): Add avx512fp16. (enabled): Handle avx512fp16. (ssemodesuffix): Add sh suffix for HFmode. (comm): Add mult, div. (plusminusmultdiv): New code iterator. (insn): Add mult, div. (*movhf_internal): Adjust for avx512fp16 instruction. (*movhi_internal): Ditto. (*cmpi<unord>hf): New define_insn for HFmode. (*ieee_s<ieee_maxmin>hf3): Likewise. (extendhf<mode>2): Likewise. (trunc<mode>hf2): Likewise. (float<floatunssuffix><mode>hf2): Likewise. (*<insn>hf): Likewise. (cbranchhf4): New expander. (movhfcc): Likewise. (<insn>hf3): Likewise. (mulhf3): Likewise. (divhf3): Likewise. * config/i386/i386.opt: Add mavx512fp16. * config/i386/immintrin.h: Include avx512fp16intrin.h. * doc/invoke.texi: Add mavx512fp16. * doc/extend.texi: Add avx512fp16 Usage Notes. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add -mavx512fp16 in dg-options. * gcc.target/i386/avx-2.c: Ditto. * gcc.target/i386/avx512-check.h: Check cpuid for AVX512FP16. * gcc.target/i386/funcspec-56.inc: Add new target attribute check. * gcc.target/i386/sse-13.c: Add -mavx512fp16. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_avx512fp16): New. * g++.target/i386/float16-1.C: New test. * g++.target/i386/float16-2.C: Ditto. * g++.target/i386/float16-3.C: Ditto. * gcc.target/i386/avx512fp16-12a.c: Ditto. * gcc.target/i386/avx512fp16-12b.c: Ditto. * gcc.target/i386/float16-3a.c: Ditto. * gcc.target/i386/float16-3b.c: Ditto. * gcc.target/i386/float16-4a.c: Ditto. * gcc.target/i386/float16-4b.c: Ditto. * gcc.target/i386/pr54855-12.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com> Co-Authored-By: Liu Hongtao <hongtao.liu@intel.com> Co-Authored-By: Wang Hongyu <hongyu.wang@intel.com> Co-Authored-By: Xu Dianhong <dianhong.xu@intel.com>
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-11-11Support Intel AVX VNNIliuhongt1-0/+2
2020-10-13 Hongtao Liu <hongtao.liu@intel.com> Hongyu Wang <hongyu.wang@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect AVXVNNI. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AVXVNNI_SET, OPTION_MASK_ISA2_AVXVNNI_UNSET): New. (OPTION_MASK_ISA2_AVX2_UNSET): Add AVXVNNI. (ix86_hanlde_option): Handle -mavxvnni, unset avxvnni when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNI. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avxvnni. * config.gcc: Add avxvnniintrin.h. * config/i386/avx512vnnivlintrin.h: Reimplement 128/256 bit non-mask intrinsics with macros to support unified interface. * config/i386/avxvnniintrin.h: New header file. * config/i386/cpuid.h (bit_AVXVNNI): New. * config/i386/i386-builtins.c (def_builtin): Handle AVXVNNI mask for unified builtin. * config/i386/i386-builtin.def (BDESC): Adjust AVX512VNNI builtins for AVXVNNI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVXVNNI__. * config/i386/i386-expand.c (ix86_expand_builtin): Handle bisa for AVXVNNI to support unified intrinsic name, since there is no dependency between AVX512VNNI and AVXVNNI. * config/i386/i386-options.c (isa2_opts): Add -mavxvnni. (ix86_valid_target_attribute_inner_p): Handle avxnnni. (ix86_option_override_internal): Ditto. * config/i386/i386.h (TARGET_AVXVNNI, TARGET_AVXVNNI_P, TARGET_AVXVNNI_P, PTA_AVXVNNI): New. (PTA_SAPPHIRERAPIDS): Add AVX_VNNI. (PTA_ALDERLAKE): Likewise. * config/i386/i386.md ("isa"): Add avxvnni, avx512vnnivl. ("enabled"): Adjust for avxvnni and avx512vnnivl. * config/i386/i386.opt: Add option -mavxvnni. * config/i386/immintrin.h: Include avxvnniintrin.h. * config/i386/sse.md (vpdpbusd_<mode>): Adjust for AVXVNNI. (vpdpbusds_<mode>): Likewise. (vpdpwssd_<mode>): Likewise. (vpdpwssds_<mode>): Likewise. (vpdpbusd_v16si): New. (vpdpbusds_v16si): Likewise. (vpdpwssd_v16si): Likewise. (vpdpwssds_v16si): Likewise. * doc/invoke.texi: Document -mavxvnni. * doc/extend.texi: Document avxvnni. * doc/sourcebuild.texi: Document target avxvnni. gcc/testsuite/ * gcc.target/i386/avx512vl-vnni-1.c: Rename.. * gcc.target/i386/avx512vl-vnni-1a.c: To This. * gcc.target/i386/avx512vl-vnni-1b.c: New test. * gcc.target/i386/avx512vl-vnni-2.c: Ditto. * gcc.target/i386/avx512vl-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-1.c: Ditto. * gcc.target/i386/avx-vnni-2.c: Ditto. * gcc.target/i386/avx-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-4.c: Ditto. * gcc.target/i386/avx-vnni-5.c: Ditto. * gcc.target/i386/avx-vnni-6.c: Ditto. * gcc.target/i386/avx-vpdpbusd-2.c: Ditto. * gcc.target/i386/avx-vpdpbusds-2.c: Ditto. * gcc.target/i386/avx-vpdpwssd-2.c: Ditto. * gcc.target/i386/avx-vpdpwssds-2.c: Ditto. * gcc.target/i386/vnni_inline_error.c: Ditto. * gcc.target/i386/avx512vnnivl-builtin.c: Ditto. * gcc.target/i386/avxvnni-builtin.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxvnni. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp (check_effective_target_avxvnni): New proc.
2020-10-29Enable GCC to support Intel Key Locker ISAliuhongt1-0/+2
gcc/ChangeLog 2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com> Hongyu Wang <hongyu.wang@intel.com> Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/cpuinfo.h (get_available_features): Detect KL, AESKLE and WIDEKL features. * common/config/i386/i386-common.c (OPTION_MASK_ISA_KL_SET): New. (OPTION_MASK_ISA_WIDEKL_SET): Likewise. (OPTION_MASK_ISA_KL_UNSET): Likewise. (OPTION_MASK_ISA_WIDEKL_UNSET): Likewise. (OPTION_MASK_ISA2_AVX2_UNSET): Likewise. (OPTION_MASK_ISA2_AVX_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_UNSET): Likewise. (OPTION_MASK_ISA2_SSSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE_UNSET): Likewise. (ix86_handle_option): Handle kl and widekl, add dependency chain for KL and SSE2. * common/config/i386/i386-cpuinfo.h (enum processor_features): (FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for KL, AESKLE and WIDEKL. * config.gcc: Add keylockerintrin.h. * doc/invoke.texi: Document new option -mkl and -mwidekl. * doc/extend.texi: Document kl and widekl. * config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New. * config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID), (UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT), (UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New function types. * config/i386/i386-builtin.def: Add __builtin_ia32_loadiwkey, __builtin_ia32_aesdec128kl_u8, __builtin_ia32_aesdec256kl_u8, __builtin_ia32_aesenc128kl_u8, __builtin_ia32_aesenc256kl_u8, __builtin_ia32_aesdecwide128kl_u8, __builtin_ia32_aesdecwide256kl_u8, __builtin_ia32_aesencwide128kl_u8, __builtin_ia32_aesencwide256kl_u8, __builtin_ia32_encodekey128_u32, __builtin_ia32_encodekey256_u32. * config/i386/i386-c.c (ix86_target_macros_internal): Handle kl and widekl. * config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl. (ix86_option_override_internal): Handle KL and WIDEKL. (ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl. * config/i386/i386-expand.c (ix86_expand_builtin): Expand Keylocker Builtins. * config/i386/i386.h (TARGET_KL): New. (TARGET_KL_P): Likewise. (TARGET_WIDEKL): Likewise. (TARGET_WIDEKL_P): Likewise. (PTA_KL): Likewise. (PTA_WIDEKL): Likewise. (PTA_TIGERLAKE): Add PTA_KL, PTA_WIDEKL. (PTA_ALDERLAKE): Likewise. * config/i386/i386.opt: Add new option mkl and mwidekl. * config/i386/keylockerintrin.h: New header file for Keylocker. * config/i386/immintrin.h: Include keylockerintrin.h. * config/i386/predicates.md (encodekey128_operation): New predicate. (encodekey256_operation): Likewise. (aeswidekl_operation): Likewise. * config/i386/sse.md (UNSPECV_LOADIWKEY): New. (UNSPECV_AESDEC128KLU8): Likewise. (UNSPECV_AESENC128KLU8): Likewise. (UNSPECV_AESDEC256KLU8): Likewise. (UNSPECV_AESENC256KLU8): Likewise. (UNSPECV_AESDECWIDE128KLU8): Likewise. (UNSPECV_AESENCWIDE128KLU8): Likewise. (UNSPECV_AESDECWIDE256KLU8): Likewise. (UNSPECV_AESENCWIDE256KLU8): Likewise. (UNSPECV_ENCODEKEY128U32): Likewise. (UNSPECV_ENCODEKEY256U32): Likewise. (encodekey128u32): New expander. (encodekey256u32): Likewise. (aes<aeswideklvariant>u8): Likewise. (loadiwkey): New insn pattern. (*encodekey128u32): Likewise. (*encodekey256u32): Likewise. (aes<aesklvariant>u8): Likewise. (*aes<aeswideklvariant>u8): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/keylocker-aesdec128kl.c: New test. * gcc.target/i386/keylocker-aesdec256kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise. * gcc.target/i386/keylocker-aesenc128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide256kl.c: Likewise. * gcc.target/i386/keylocker-encodekey128.c: Likewise. * gcc.target/i386/keylocker-encodekey256.c: Likewise. * gcc.target/i386/keylocker-loadiwkey.c: Likewise. * g++.dg/other/i386-2.C: Add -mkl and -mwidekl. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Add kl and widekl. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/funcspec-56.inc: Add new target attribute test.
2020-10-09x86: Add <x86gprintrin.h>H.J. Lu1-205/+2
For sources which can't use any vector instructions, <x86intrin.h> and <immintrin.h> cannot be included for compiler intrinsics: $ echo "#include <x86intrin.h>" | gcc -S -O2 -mno-sse -mno-mmx -x c - In file included from /usr/include/stdlib.h:1013, from /usr/lib/gcc/x86_64-redhat-linux/10/include/mm_malloc.h:27, from /usr/lib/gcc/x86_64-redhat-linux/10/include/xmmintrin.h:34, from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:29, from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32, from <stdin>:1: /usr/include/bits/stdlib-float.h: In function ‘atof’: /usr/include/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled 26 | { | ^ $ libgcc/config/i386/shadow-stack-unwind.h has a workaround: /* NB: We need _get_ssp and _inc_ssp from <cetintrin.h>. But we can't include <x86intrin.h> which ends up including <mm_malloc.h>, which includes <stdlib.h> and <errno.h> unconditionally. But we can't include any libc system headers unconditionally from libgcc. Avoid including <mm_malloc.h> here by defining _IMMINTRIN_H_INCLUDED. */ #define _IMMINTRIN_H_INCLUDED #include <cetintrin.h> #undef _IMMINTRIN_H_INCLUDED Add a standalone intrinsic header file, <x86gprintrin.h>, to provide integer only intrinsics. All integer only intrinsics are placed in <x86gprintrin.h>. <x86intrin.h> and <immintrin.h> simply include <x86gprintrin.h>. gcc/ PR target/97148 * config.gcc (extra_headers): Add x86gprintrin.h. * config/i386/adxintrin.h: Check _X86GPRINTRIN_H_INCLUDED for <x86gprintrin.h>. * config/i386/bmi2intrin.h: Likewise. * config/i386/bmiintrin.h: Likewise. * config/i386/cetintrin.h: Likewise. * config/i386/cldemoteintrin.h: Likewise. * config/i386/clflushoptintrin.h: Likewise. * config/i386/clwbintrin.h: Likewise. * config/i386/enqcmdintrin.h: Likewise. * config/i386/fxsrintrin.h: Likewise. * config/i386/ia32intrin.h: Likewise. * config/i386/lwpintrin.h: Likewise. * config/i386/lzcntintrin.h: Likewise. * config/i386/movdirintrin.h: Likewise. * config/i386/pconfigintrin.h: Likewise. * config/i386/pkuintrin.h: Likewise. * config/i386/rdseedintrin.h: Likewise. * config/i386/rtmintrin.h: Likewise. * config/i386/serializeintrin.h: Likewise. * config/i386/tbmintrin.h: Likewise. * config/i386/tsxldtrkintrin.h: Likewise. * config/i386/waitpkgintrin.h: Likewise. * config/i386/wbnoinvdintrin.h: Likewise. * config/i386/xsavecintrin.h: Likewise. * config/i386/xsaveintrin.h: Likewise. * config/i386/xsaveoptintrin.h: Likewise. * config/i386/xsavesintrin.h: Likewise. * config/i386/xtestintrin.h: Likewise. * config/i386/immintrin.h: Include <x86gprintrin.h> instead of <fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>, <xsavesintrin.h>, <xsavecintrin.h>, <lzcntintrin.h>, <bmiintrin.h>, <bmi2intrin.h>, <xtestintrin.h>, <cetintrin.h>, <movdirintrin.h>, <sgxintrin.h, <pconfigintrin.h>, <waitpkgintrin.h>, <cldemoteintrin.h>, <enqcmdintrin.h>, <serializeintrin.h>, <tsxldtrkintrin.h>, <adxintrin.h>, <clwbintrin.h>, <clflushoptintrin.h>, <wbnoinvdintrin.h> and <pkuintrin.h>. (_wbinvd): Moved to config/i386/x86gprintrin.h. (_rdrand16_step): Likewise. (_rdrand32_step): Likewise. (_rdpid_u32): Likewise. (_readfsbase_u32): Likewise. (_readfsbase_u64): Likewise. (_readgsbase_u32): Likewise. (_readgsbase_u64): Likewise. (_writefsbase_u32): Likewise. (_writefsbase_u64): Likewise. (_writegsbase_u32): Likewise. (_writegsbase_u64): Likewise. (_rdrand64_step): Likewise. (_ptwrite64): Likewise. (_ptwrite32): Likewise. * config/i386/x86gprintrin.h: New file. * config/i386/x86intrin.h: Include <x86gprintrin.h>. Don't include <ia32intrin.h>, <lwpintrin.h>, <tbmintrin.h>, <popcntintrin.h>, <mwaitxintrin.h> and <clzerointrin.h>. gcc/testsuite/ * gcc.target/i386/avx-1.c (__builtin_ia32_lwpval32): New to support <lwpintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_lwpval64): Likewise. (__builtin_ia32_lwpins32): Likewise. (__builtin_ia32_lwpins64): Likewise. (__builtin_ia32_bextri_u32): New to support <tbmintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_bextri_u64): Likewise. * gcc.target/i386/x86gprintrin-1.c: New test. * gcc.target/i386/x86gprintrin-2.c: Likewise. * gcc.target/i386/x86gprintrin-3.c: Likewise. * gcc.target/i386/x86gprintrin-4.c: Likewise. * gcc.target/i386/x86gprintrin-4a.c: Likewise. * gcc.target/i386/x86gprintrin-5.c: Likewise. * gcc.target/i386/x86gprintrin-5a.c: Likewise. * gcc.target/i386/x86gprintrin-5b.c: Likewise. * gcc.target/i386/x86gprintrin-6.c: Likewise. libgcc/ PR target/97148 * config/i386/shadow-stack-unwind.h: Include <x86gprintrin.h> instead of <cetintrin.h>.
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt1-0/+6
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto.
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt1-0/+2
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET, OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros. * config.gcc: Add tsxldtrkintrin.h to extra_headers. * config/i386/driver-i386.c (host_detect_local_cpu): Detect TSXLDTRK. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __TSXLDTRK__. * config/i386/i386-options.c (ix86_target_string): Add -mtsxldtrk. (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk. * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P): New. * config/i386/i386.md (define_c_enum "unspec"): Add UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK. (TSXLDTRK): New define_int_iterator. ("<tsxldtrk>"): New define_insn. * config/i386/i386.opt: Add -mtsxldtrk. * config/i386/immintrin.h: Include tsxldtrkintrin.h. * config/i386/tsxldtrkintrin.h: New. * doc/invoke.texi: Document -mtsxldtrk. gcc/testsuite/ * g++.dg/other/i386-2.c: Add -mtsxldtrk. * g++.dg/other/i386-3.c: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewsie. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/tsxldtrk-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add target attribute tests for tsxldtrk.
2020-05-06Enable GCC support for SERIALIZEliuhongt1-0/+2
2020-03-04 Hongtao Liu <hongtao.liu@intel.com> 2020-03-04 Wei Xiao <wei3.xiao@intel.com> gcc/Changelog: * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET, OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros. (ix86_handle_option): Handle -mserialize. * gcc/config.gcc (serializeintrin.h): New header file. * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit. * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect -mserialize. * gcc/config/i386/i386-builtin.def: Add new builtin. * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro. * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts): Add -mserialize. * (ix86_valid_target_attribute_inner_p): Add target attribute * for serialize. * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P): New macros. * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec. (serialize): New define_insn. * gcc/config/i386/i386.opt (mserialize): New option * gcc/config/i386/immintrin.h: Include serailizeintrin.h. * gcc/config/i386/serializeintrin.h: New header file. * gcc/doc/invoke.texi: Add documents for -mserialize. gcc/testsuite/Changelog * gcc/testsuite/gcc.target/i386/serialize-1.c: New test. * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize. * gcc/testsuite/g++.dg/other/i386-3.C: Ditto. * gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto. * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r279813
2019-06-26Enable GCC support for AVX512_VP2INTERSECT which will be in tigerlaker.Hongtao Liu1-0/+4
There are two instructions for AVX512_VP2INTERSECT: VP2INTERSECTD and VP2INTERSECTQ. gcc/ 2019-06-05 Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VP2INTERSECT_SET, OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET): New macros. (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET. (ix86_handle_option): Handle -mavx512vp2intersect. * config/i386/avx512vp2intersectintrin.h: New. * config/i386/avx512vp2intersectvlintrin.h: New. * config/i386/cpuid.h (bit_AVX512VP2INTERSECT): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX512VP2INTERSECT. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-builtins.c: (enum processor_features): Add F_AVX512VP2INTERSECT. (static const _isa_names_table isa_names_table): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512VP2INTERSECT__. * config/i386/i386-expand.c (ix86_expand_builtin): Expand IX86_BUILTIN_2INTERSECTD512, IX86_BUILTIN_2INTERSECTQ512, IX86_BUILTIN_2INTERSECTD256, IX86_BUILTIN_2INTERSECTQ256, IX86_BUILTIN_2INTERSECTD128, IX86_BUILTIN_2INTERSECTQ128. * config/i386/i386-modes.def (P2QI, P2HI): New modes. * config/i386/i386-options.c (ix86_target_string): Add -mavx512vp2intersect. (ix86_option_override_internal): Handle AVX512VP2INTERSECT. * config/i386/i386.c (ix86_hard_regno_nregs): Allocate two regs for P2HImode and P2QImode. (ix86_hard_regno_mode_ok): Register pair only starts at even hardreg number for P2QImode and P2HImode. (ix86_regmode_natural_size): New function. * config/i386/i386.h (TARGET_AVX512VP2INTERSECT, TARGET_AVX512VP2INTERSECT_P, PTA_AVX512VP2INTERSECT REGMODE_NATURAL_SIZE, MASK_PAIR_REGNO_P): New. * config/i386/i386-protos.h (ix86_regmode_natural_size): Declare * config/i386/i386.opt: Add -mavx512vp2intersect. * config/i386/immintrin.h: Include avx512vp2intersectintrin.h and avx512vp2intersectvlintrin.h. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_VP2INTERSECT. (define_mode_iterator VI48_AVX512VP2VL): New. (avx512vp2intersect_2intersect<mode>, avx512vp2intersect_2intersectv16si): New define_insn patterns. * config.gcc: Add avx512vp2intersectvlintrin.h and avx512vp2intersectintrin.h to extra_headers. * doc/invoke.texi: Document -mavx512vp2intersect. gcc/testsuite 2019-06-06 Hongtao Liu <hongtao.liu@intel.com> Olga Makhotina <olga.makhotina@intel.com> * gcc.target/i386/avx512-check.h: Handle bit_AVX512VP2INTERSECT. * gcc.target/i386/avx512vp2intersect-2intersect-1a.c: New test. * gcc.target/i386/avx512vp2intersect-2intersect-1b.c: Likewise. * gcc.target/i386/avx512vp2intersect-2intersectvl-1a.c: Likewise. * gcc.target/i386/avx512vp2intersect-2intersectvl-1b.c: Likewise. * gcc.target/i386/sse-12.c: Add -mavx512vp2intersect. * gcc.target/i386/sse-13.c: Likewsie. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. * g++.dg/other/i386-2.C: Likewise. * g++.dg/other/i386-3.C: Likewise. Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com> Co-Authored-By: Olga Makhotina <olga.makhotina@intel.com> From-SVN: r272668
2019-05-28Add GCC support to ENQCMD.Xuepeng Guo1-0/+2
gcc/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_ENQCMD_SET, OPTION_MASK_ISA_ENQCMD_UNSET): New macros. (ix86_handle_option): Handle -menqcmd. * config.gcc (enqcmdintrin.h): New header file. * config/i386/cpuid.h (bit_ENQCMD): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -menqcmd. * config/i386/i386-builtin-types.def ((INT, PVOID, PCVOID)): New function type. * config/i386/i386-builtin.def (__builtin_ia32_enqcmd, __builtin_ia32_enqcmds): New builtins. * config/i386/i386-c.c (__ENQCMD__): New macro. * config/i386/i386-option.c (ix86_target_string): Add -menqcmd. (ix86_valid_target_attribute_inner_p): Likewise. * config/i386/i386-expand.c (ix86_expand_builtin): Expand IX86_BUILTIN_ENQCMD and IX86_BUILTIN_ENQCMDS. * config/i386/i386.h (TARGET_ENQCMD): New. * config/i386/i386.md (UNSPECV_ENQCMD, UNSPECV_ENQCMDS): New. (@enqcmd<enqcmd_sfx>_<mode>): New insn pattern. (movdir64b_<mode>): Parameterize to enable share expansion code with ENQCMD in function ix86_expand_builtin. * config/i386/i386.opt: Add -menqcmd. * config/i386/immintrin.h: Include enqcmdintrin.h. * config/i386/enqcmdintrin.h: New intrinsic file. * doc/invoke.texi: Add -menqcmd. gcc/testsuite/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * gcc.target/i386/enqcmd.c: New test. * gcc.target/i386/enqcmds.c: Likewise. * g++.dg/other/i386-2.C: Add -menqcmd. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. From-SVN: r271678
2019-05-08Enable support for bfloat16 which will be in Future Cooper Lake.Hongtao Liu1-0/+4
There are 3 instructions for AVX512BF16: VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting: - VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data. - VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data. - VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision. 2019-05-07 Wei Xiao <wei3.xiao@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BF16_SET OPTION_MASK_ISA_AVX512BF16_UNSET, OPTION_MASK_ISA2_AVX512BW_UNSET): New. (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA_AVX512BF16_UNSET. (ix86_handle_option): Handle -mavx512bf16. * config.gcc: Add avx512bf16vlintrin.h and avx512bf16intrin.h to extra_headers. * config/i386/avx512bf16vlintrin.h: New. * config/i386/avx512bf16intrin.h: New. * config/i386/cpuid.h (bit_AVX512BF16): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect BF16. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512BF16__. * config/i386/i386-option.c (ix86_target_string): Add -mavx512bf16. (ix86_option_override_internal): Handle BF16. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386-expand.c (ix86_expand_args_builtin): Ditto. * config/i386/i386-builtin.c (enum processor_features): Add F_AVX512BF16. (static const _isa_names_table isa_names_table): Ditto. * config/i386/i386.h (TARGET_AVX512BF16, TARGET_AVX512BF16_P): New. (PTA_AVX512BF16): Ditto. * config/i386/i386.opt: Add -mavx512bf16. * config/i386/immintrin.h: Include avx512bf16intrin.h and avx512bf16vlintrin.h. * config/i386/sse.md (avx512f_cvtne2ps2bf16_<mode><mask_name>, avx512f_cvtneps2bf16_<mode><mask_name>, avx512f_dpbf16ps_<mode><mask_half_name>): New define_insn patterns. * config/i386/subst.md (mask_half): Add new subst. * doc/invoke.texi: Document -mavx512bf16. 2019-05-07 Wei Xiao <wei3.xiao@intel.com> * gcc.target/i386/avx512bf16-vcvtne2ps2bf16-1.c: New test. * gcc.target/i386/avx512bf16-vcvtneps2bf16-1.c: New test. * gcc.target/i386/avx512bf16-vdpbf16ps-1.c: New test. * gcc.target/i386/avx512bf16vl-vcvtne2ps2bf16-1.c: New test. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: New test. * gcc.target/i386/avx512bf16vl-vdpbf16ps-1.c: New test. * gcc.target/i386/builtin_target.c: Handle avx512bf16. * gcc.target/i386/sse-12.c: Add -mavx512bf16. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. 2019-05-07 Hongtao Liu <hongtao.liu@intel.com> * config/i386/cpuinfo.c (get_available_features): Detect BF16. * config/i386/cpuinfo.h (enum processor_features): Add FEATURE_AVX512BF16. From-SVN: r271006
2019-01-21i386: Move Intel intrinsics head files to <immintrin.h>H.J. Lu1-0/+24
According to Intel Intrinsics Guide: https://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel intrinsics should be available by including <immintrin.h>. This patch moves remaining Intel intrinsics head files from <x86intrin.h> to <immintrin.h>. PR target/71659 * config/i386/adxintrin.h: Just check _IMMINTRIN_H_INCLUDED. * config/i386/clflushoptintrin.h: Check _IMMINTRIN_H_INCLUDED instead of _X86INTRIN_H_INCLUDED. * onfig/i386/clwbintrin.h: Likewise. * config/i386/pkuintrin.h: Likewise. * config/i386/prfchwintrin.h: Likewise. * config/i386/rdseedintrin.h: Likewise. * config/i386/wbnoinvdintrin.h: Likewise. * config/i386/xsavecintrin.h: Likewise. * config/i386/xsavesintrin.h: Likewise. * config/i386/fxsrintrin.h: Enable _IMMINTRIN_H_INCLUDED check. * config/i386/xsaveintrin.h: Likewise. * config/i386/xsaveoptintrin.h: Likewise. * config/i386/x86intrin.h: Move "#include" <rdseedintrin.h>, <prfchwintrin.h>, <fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>, <adxintrin.h>, <clwbintrin.h>, <clflushoptintrin.h>, <xsavesintrin.h>, <xsavecintrin.h>, <wbnoinvdintrin.h> and <pkuintrin.h> to ... * config/i386/immintrin.h: Here. From-SVN: r268113
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r267494
2018-11-09Add PTWRITE builtins for x86Andi Kleen1-0/+26
Add builtins/intrinsics for PTWRITE. PTWRITE is a new instruction on Intel Gemini Lake/ Goldmont Plus that allows to write values into the Processor Trace log. This allows very light weight instrumentation of programs. The intrinsics are compatible to icc. Automatically enabled for Goldmont Plus. gcc/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_PTWRITE_SET): New. (OPTION_MASK_ISA_PTWRITE_UNSET): New. (ix86_handle_option): Handle OPT_mptwrite. * config/i386/cpuid.h (bit_PTWRITE): Add. * config/i386/driver-i386.c (host_detect_local_cpu): Detect ptwrite. * config/i386/i386-builtin.def (BDESC): Add ptwrite32/64. * config/i386/i386-c.c (ix86_target_macros_internal): Define __PTWRITE__. * config/i386/i386.c (ix86_target_string): Handle ptwrite. (ix86_option_override_internal): Handle PTA_PTWRITE. (ix86_valid_target_attribute_inner_p): Define ptwrite. (def_builtin2): Force UINT64 to be 64bit only. * config/i386/i386.h (TARGET_PTWRITE): Add. (TARGET_PTWRITE_P): Add. (PTA_PTWRITE): Add. * config/i386/i386.md: Define ptwrite. * config/i386/i386.opt: Add -mptwrite. * config/i386/immintrin.h (_ptwrite64): Add. (_ptwrite32): Add * doc/extend.texi: Document __builtin_ia32_ptwrite*. * doc/invoke.texi: Document -mptwrite. gcc/testsuite/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * gcc.target/i386/ptwrite1.c: New test. * gcc.target/i386/ptwrite2.c: New test. From-SVN: r265947
2018-06-04cldemoteintrin.h: Change define from _X86INTRIN_H_INCLUDED to ↵Sebastian Peryt1-0/+8
_IMMINTRIN_H_INCLUDED. 2018-06-04 Sebastian Peryt <sebastian.peryt@intel.com> * config/i386/cldemoteintrin.h: Change define from _X86INTRIN_H_INCLUDED to _IMMINTRIN_H_INCLUDED. * config/i386/pconfigintrin.h: Ditto. * config/i386/waitpkgintrin.h: Ditto. * config/i386/immintrin.h: Add includes for sgxintrin.h, pconfigintrin.h, waitpkgintrin.h and cldemoteintrin.h. * config/i386/x86intrin.h: Remove includes for mintrin.h, xmmintrin.h, emmintrin.h, pmmintrin.h, tmmintrin.h, smmintrin.h, wmmintrin.h, bmiintrin.h, bmi2intrin.h, lzcntintrin.h, sgxintrin.h, pconfigintrin.h, waitpkgintrin.h and cldemoteintrin.h. From-SVN: r261144
2018-04-19i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, [...]): New defines.Sebastian Peryt1-0/+2
2018-04-19 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, OPTION_MASK_ISA_MOVDIR64B_SET, OPTION_MASK_ISA_MOVDIRI_UNSET, OPTION_MASK_ISA_MOVDIR64B_UNSET): New defines. (ix86_handle_option): Handle -mmovdiri and -mmovdir64b. * config.gcc (movdirintrin.h): New header. * config/i386/cpuid.h (bit_MOVDIRI, bit_MOVDIR64B): New bits. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mmovdiri and -mmvodir64b. * config/i386/i386-builtin-types.def ((VOID, PUNSIGNED, UNSIGNED), (VOID, PVOID, PCVOID)): New function types. * config/i386/i386-builtin.def (__builtin_ia32_directstoreu_u32, __builtin_ia32_directstoreu_u64, __builtin_ia32_movdir64b): New builtins. * config/i386/i386-c.c (__MOVDIRI__, __MOVDIR64B__): New. * config/i386/i386.c (ix86_target_string): Added -mmovdir64b and -mmovdiri. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_special_args_builtin): Added VOID_FTYPE_PUNSIGNED_UNSIGNED and VOID_FTYPE_PUNSIGNED_UNSIGNED. (ix86_expand_builtin): Expand IX86_BUILTIN_MOVDIR64B. * config/i386/i386.h (TARGET_MOVDIRI, TARGET_MOVDIRI_P, TARGET_MOVDIR64B, TARGET_MOVDIR64B_P): New. * config/i386/i386.md (UNSPECV_MOVDIRI, UNSPECV_MOVDIR64B): New. (movdiri<mode>, movdir64b_<mode>): New. * config/i386/i386.opt: Add -mmovdiri and -mmovdir64b. * config/i386/immintrin.h: Include movdirintrin.h. * config/i386/movdirintrin.h: New file. * doc/invoke.texi: Added -mmovdiri and -mmovdir64b. gcc/testsuite/ * gcc.target/i386/movdir-1.c: New test. From-SVN: r259495
2018-03-05Enable WBOINVD and PCONFIG instructions.Olga Makhotina1-0/+7
2018-03-05 Olga Makhotina <olga.makhotina@intel.com> Enable WBOINVD and PCONFIG instructions. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig and -mwbnoinvd. * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, __builtin_ia32_wbinvd): New builtins. (SPECIAL_ARGS2): New. * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. (SPECIAL_ARGS2): New. * config/i386/i386.c (ix86_target_string): Add -mpconfig and -mwbnoinvd. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_init_mmx_sse_builtins): Add special_args2. * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, TARGET_WBNOINVD, TARGET_WBNOINVD_P): New. * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. (define_insn "wbinvd", define_insn "wbnoinvd"): New. * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. * config/i386/immintrin.h (_wbinvd): New intrinsic. * config/i386/pconfigintrin.h: New file. * config/i386/wbnoinvdintrin.h: Ditto. * config/i386/x86intrin.h: Add headers pconfigintrin.h and wbnoinvdintrin.h. * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. * gcc.target/i386/wbinvd-1.c: New test. * gcc.target/i386/wbnoinvd-1.c: Ditto. * gcc.target/i386/pconfig-1.c: Ditto. From-SVN: r258247
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-12-22Enable AVX512BITALGJulia Koval1-0/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET, OPTION_MASK_ISA_AVX512BITALG_UNSET): New. (ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting. * config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16, _mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16, _mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8, _mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8, _mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16, _mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask, _mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8, _mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8, _mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics. * config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64, _mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32, _mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64, _mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64, _mm256_maskz_popcnt_epi64): New intrinsics. * config/i386/cpuid.h (bit_AVX512BITALG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI, V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI, V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types. * config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di, __builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di, __builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si, __builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si, __builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi, __builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi, __builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi, __builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi, __builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi, __builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask, __builtin_ia32_vpshufbitqmb256_mask, __builtin_ia32_vpshufbitqmb512_mask): New builtins. * config/i386/i386-c.c (__AVX512BITALG__): New. * config/i386/i386.c (isa2_opts): Add -mavx512bitalg. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_args_builtin): Handle new types. * config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New. * config/i386/i386.opt: Add -mavx512bitalg. * config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/sse.md (VI48_AVX512VLBW): New iterator. (vpopcount<mode><mask_name>): Add more types. (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New. * doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq. gcc/testsuite/ * g++.dg/other/i386-2.C: Add new options. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG. * gcc.target/i386/avx512bitalg-vpopcntb-1.c: New. * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New. * gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types. * gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics. * gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto. * gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto. Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com> From-SVN: r255975
2017-12-20Enable VPCLMULQDQ supportJulia Koval1-0/+2
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET, OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New. (ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2. * config.gcc: Include vpclmulqdqintrin.h. * config/i386/cpuid.h: Handle bit_VPCLMULQDQ. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -mvpclmulqdq. * config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di, __builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New. * config/i386/i386-c.c (__VPCLMULQDQ__): New. * config/i386/i386.c (isa2_opts): Add -mcx16. (isa_opts): Add -mpclmulqdq, remove -mcx16. (ix86_option_override_internal): Move mcx16 to flags2. (ix86_valid_target_attribute_inner_p): Add vpclmulqdq. (ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ. * config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New. * config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2. * config/i386/immintrin.h: Include vpclmulqdqintrin.h. * config/i386/sse.md (vpclmulqdq_<mode>): New pattern. * config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128, _mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics. * doc/invoke.texi: Add -mvpclmulqdq. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_VPCLMULQDQ. * gcc.target/i386/avx512f-vpclmulqdq-2.c: New test. * gcc.target/i386/avx512vl-vpclmulqdq-2.c: Ditto. * gcc.target/i386/vpclmulqdq.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_vpclmulqdq): New. From-SVN: r255850
2017-12-12Enable VAES support [2/5]Julia Koval1-0/+2
gcc/ * config.gcc: Add vaesintrin.h. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type. * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi, __builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins. * config/i386/i386.c (ix86_expand_args_builtin): Handle new type. * config/i386/immintrin.h: Include vaesintrin.h. * config/i386/sse.md (vaesdec_<mode>): New pattern. * config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128, _mm_aesdec_epi128): New intrinsics. gcc/testsuite/ * gcc.target/i386/avx512-check.h: Handle bit_VAES. * gcc.target/i386/avx512f-aesdec-2.c: New test. * gcc.target/i386/avx512fvl-vaes-1.c: Ditto. * gcc.target/i386/avx512vl-aesdec-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New. From-SVN: r255572
2017-12-07Enable VAES support [2/5]Julia Koval1-0/+4
gcc/ * config.gcc: Add vaesintrin.h. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type. * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi, __builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins. * config/i386/i386.c (ix86_expand_args_builtin): Handle new type. * config/i386/immintrin.h: Include vaesintrin.h. * config/i386/sse.md (vaesdec_<mode>): New pattern. * config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128, _mm_aesdec_epi128): New intrinsics. gcc/testsuite/ * gcc.target/i386/avx512-check.h: Handle bit_VAES. * gcc.target/i386/avx512f-aesdec-2.c: New test. * gcc.target/i386/avx512fvl-vaes-1.c: Ditto. * gcc.target/i386/avx512vl-aesdec-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New. From-SVN: r255461
2017-11-23Enable VBMI2 support [2/7]Julia Koval1-0/+4
gcc/ config.gcc (avx512vbmi2intrin.h, avx512vbmi2vlintrin): New headers. config/i386/avx512vbmi2intrin.h (_mm512_mask_compress_epi8, _mm512_maskz_compress_epi8, _mm512_mask_compressstoreu_epi8, _mm512_mask_compress_epi16, _mm512_maskz_compress_epi16, _mm512_mask_compressstoreu_epi16): New. config/i386/avx512vbmi2vlintrin.h (_mm_mask_compress_epi8, _mm_maskz_compress_epi8, _mm256_mask_compressstoreu_epi16, _mm_mask_compress_epi16, _mm_maskz_compress_epi16, _mm256_mask_compress_epi16, _mm256_maskz_compress_epi16, _mm_mask_compressstoreu_epi8, _mm_mask_compressstoreu_epi16, _mm256_mask_compress_epi8, _mm256_maskz_compress_epi8, _mm256_mask_compressstoreu_epi8): New. config/i386/i386-builtin-types.def (VOID_FTYPE_PV64QI_V64QI_UDI, VOID_FTYPE_PV32HI_V32HI_USI, VOID_FTYPE_PV32QI_V32QI_USI, VOID_FTYPE_PV16QI_V16QI_UHI, VOID_FTYPE_PV16HI_V16HI_UHI, VOID_FTYPE_PV8HI_V8HI_UQI): New types. config/i386/i386-builtin.def (__builtin_ia32_compressqi512_mask, __builtin_ia32_compresshi512_mask, __builtin_ia32_compressqi256_mask, __builtin_ia32_compressqi128_mask, __builtin_ia32_compresshi256_mask, __builtin_ia32_compresshi128_mask, __builtin_ia32_compressstoreuqi512_mask, __builtin_ia32_compressstoreuhi512_mask, __builtin_ia32_compressstoreuqi256_mask, __builtin_ia32_compressstoreuqi128_mask, __builtin_ia32_compressstoreuhi256_mask, __builtin_ia32_compressstoreuhi128_mask): New builtins. config/i386/i386.c (ix86_init_mmx_sse_builtins): Create special args array for flags2. (ix86_expand_special_args_builtin): Handle new types. (s4fma_expand): Handle new builtin array. config/i386/immintrin.h: Include new headers. config/i386/sse.md (VI12_AVX512VLBW): New iterator. (compress<mode>_mask, compressstore<mode>_mask): New patterns. gcc/testsuite/ gcc.target/i386/avx512-check.h: Handle AVX512VBMI2 bit. gcc.target/i386/avx512f-vpcompressb-1.c: New test. gcc.target/i386/avx512f-vpcompressb-2.c: Ditto. gcc.target/i386/avx512f-vpcompressw-1.c: Ditto. gcc.target/i386/avx512f-vpcompressw-2.c: Ditto. gcc.target/i386/avx512vl-vpcompressb-1.c: Ditto. gcc.target/i386/avx512vl-vpcompressb-2.c: Ditto. gcc.target/i386/avx512vl-vpcompressw-1.c: Ditto. gcc.target/i386/avx512vl-vpcompressw-2.c: Ditto. gcc.target/i386/i386.exp (check_effective_target_avx512vbmi2): New. From-SVN: r255119
2017-10-31GFNI enabling [2/4]Julia Koval1-0/+2
gcc/ * config.gcc: Add gfniintrin.h. * config/i386/gfniintrin.h: New. * config/i386/i386-builtin-types.def ( __builtin_ia32_vgf2p8affineinvqb_v64qi, __builtin_ia32_vgf2p8affineinvqb_v64qi_mask, __builtin_ia32_vgf2p8affineinvqb_v32qi __builtin_ia32_vgf2p8affineinvqb_v32qi_mask, __builtin_ia32_vgf2p8affineinvqb_v16qi, __builtin_ia32_vgf2p8affineinvqb_v16qi_mask): New builtins. * config/i386/i386-builtin.def (V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI, V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI, V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI, V64QI_FTYPE_V64QI_V64QI_INT): New types. * config/i386/i386.c (ix86_expand_args_builtin): Handle new types. * config/i386/immintrin.h: Include gfniintrin.h. * config/i386/sse.md (vgf2p8affineinvqb_*) New pattern. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/avx512-check.h: Check GFNI bit. * gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/gfni-1.c: New. * gcc.target/i386/gfni-2.c: New. * gcc.target/i386/gfni-3.c: New. * gcc.target/i386/gfni-4.c: New. * gcc.target/i386/i386.exp: (check_effective_target_gfni): New. * gcc.target/i386/sse-12.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r254250
2017-10-21Update x86 backend to enable Intel CET.Igor Tsimbalist1-0/+2
All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977
2017-02-17i386-common.c (OPTION_MASK_ISA_RDPID_SET): New.Julia Koval1-0/+16
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RDPID_SET): New. (OPTION_MASK_ISA_PKU_UNSET): New. (ix86_handle_option): Handle -mrdpid. * config/i386/cpuid.h (bit_RDPID): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect RDPID feature. * config/i386/i386-builtin.def (__builtin_ia32_rdpid): New. * config/i386/i386-c.c (ix86_target_macros_internal): Handle RDPID flag. * config/i386/i386.c (ix86_target_string): Add -mrdpid to isa2_opts. (ix86_valid_target_attribute_inner_p): Add "rdpid". (ix86_expand_builtin): Handle IX86_BUILTIN_RDPID. * config/i386/i386.h (TARGET_RDPID, TARGET_RDPID_P): New. * config/i386/i386.md (define_insn "rdpid"): New. * config/i386/i386.opt Add -mrdpid. * config/i386/immintrin.h (_rdpid_u32): New. testsuite/ChangeLog: * gcc.target/i386/rdpid.c New test. * gcc.target/i386/sse-12.c: Add -mrdpid. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r245540
2017-01-10Enable AVX-512 VPOPCNTD/VPOPCNTQ instructions.Andrew Senkevich1-0/+2
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET, OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET): New. * config.gcc: Add avx512vpopcntdqintrin.h. * config/i386/avx512vpopcntdqintrin.h: New. * config/i386/cpuid.h (bit_AVX512VPOPCNTDQ): New. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def (__builtin_ia32_vpopcountd_v16si, __builtin_ia32_vpopcountd_v16si_mask, __builtin_ia32_vpopcountq_v8di, __builtin_ia32_vpopcountq_v8di_mask): New. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512VPOPCNTDQ__. * config/i386/i386.c (ix86_target_string): Add -mavx512vpopcntdq. (PTA_AVX512VPOPCNTDQ): Define. * config/i386/i386.h (TARGET_AVX512VPOPCNTDQ, TARGET_AVX512VPOPCNTDQ_P): Define. * config/i386/i386.opt: Add mavx512vpopcntdq. * config/i386/immintrin.h: Include avx512vpopcntdqintrin.h. * config/i386/sse.md (define_insn "vpopcount<mode><mask_name>"): New. libgcc/ * config/i386/cpuinfo.h (processor_features): Add FEATURE_AVX512VPOPCNTDQ. * config/i386/cpuinfo.c (get_available_features): Habdle new feature. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mavx512vpopcntdq. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/builtin_target.c: Handle new option. * gcc.target/i386/funcspec-56.inc: Test new attributes. * gcc.target/i386/avx512vpopcntdq-vpopcntd.c: New test. * gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto. From-SVN: r244263
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r243994
2016-11-17Enable AVX512_4FMAPS and AVX512_4VNNIW instructionsKirill Yukhin1-0/+4
This requires additional patch for register allocator from Vladimir Makarov. gcc/ 2016-11-17 Kirill Yukhin <kirill.yukhin@gmail.com> Andrew Senkevich <andrew.senkevich@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX5124FMAPS_SET, OPTION_MASK_ISA_AVX5124FMAPS_UNSET, OPTION_MASK_ISA_AVX5124VNNIW_SET, OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New. (ix86_handle_option): Handle OPT_mavx5124fmaps, OPT_mavx5124vnniw. * config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h. * config/i386/avx5124fmapsintrin.h: New file. * config/i386/avx5124vnniwintrin.h: Ditto. * config/i386/constraints.md (h): New constraint. * config/i386/cpuid.h: (bit_AVX5124VNNIW, bit_AVX5124FMAPS): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx5124fmaps, avx5124vnniw. * config/i386/i386-builtin-types.def: Add types V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI, V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF, V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF, V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI, V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI, V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI. * config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask, __builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss, __builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask, __builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss, __builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd, __builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds, __builtin_ia32_vp4dpwssds_mask): New. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX5124FMAPS__, __AVX5124VNNIW__. * config/i386/i386-modes.def: Fixed comment typos, added new modes (VECTOR_MODES (FLOAT, 256), VECTOR_MODE (INT, SI, 64)). * config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps, -mavx5124vnniw. (PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Add avx5124fmaps, avx5124vnniw. (ix86_expand_builtin): Handle new builtins. (ix86_additional_allocno_class_p): New. * config/i386/i386.h (TARGET_AVX5124FMAPS, TARGET_AVX5124FMAPS_P, TARGET_AVX5124VNNIW, TARGET_AVX5124VNNIW_P): Define. (reg_class): Add MOD4_SSE_REGS. (MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New. * config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw. * config/i386/immintrin.h: Include avx5124fmapsintrin.h, avx5124vnniwintrin.h. * config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD, UNSPEC_VP4FNMADD, UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS. (define_mode_iterator IMOD4): New. (define_mode_attr imod4_narrow): Ditto. (define_insn "mov<mode>"): Ditto. (define_insn "avx5124fmaddps_4fmaddps"): Ditto. (define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto. (define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto. (define_insn "avx5124fmaddps_4fmaddss"): Ditto. (define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto. (define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto. (define_insn "avx5124fmaddps_4fnmaddps"): Ditto. (define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto. (define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto. (define_insn "avx5124fmaddps_4fnmaddss"): Ditto. (define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto. (define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto. (define_insn "avx5124vnniw_vp4dpwssd"): Ditto. (define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto. (define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto. (define_insn "avx5124vnniw_vp4dpwssds"): Ditto. (define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto. (define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto. * init-regs.c (initialize_uninitialized_regs): Add emit_clobber call. * genmodes.c (mode_size_inline): Extend return type. * machmode.h (mode_size, mode_base_align): Extend type. gcc/testsuite/ 2016-11-17 Kirill Yukhin <kirill.yukhin@gmail.com> Andrew Senkevich <andrew.senkevich@intel.com> * gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: New test. * gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto. * gcc.target/i386/avx5124fmaps-check.h: Ditto. * gcc.target/i386/avx5124vnniw-check.h: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto. * gcc.target/i386/avx512f-helper.h: Add avx5124fmaps-check.h, avx5124vnniw-check.h. * gcc.target/i386/i386.exp (check_effective_target_avx5124fmaps, check_effective_target_avx5124vnniw): New. * gcc.target/i386/m128-check.h (ESP_FLOAT, ESP_DOUBLE): Set under ifndef. * gcc.target/i386/sse-12.c: Add -mavx5124fmaps, -mavx5124vnniw. * gcc.target/i386/sse-13.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. From-SVN: r242569
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r232055
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r219188
2014-11-21Add avx512vbmi instructions.Ilya Tocar1-0/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI_SET OPTION_MASK_ISA_AVX512VBMI_UNSET): New. (ix86_handle_option): Handle OPT_mavx512vbmi. * config.gcc: Add avx512vbmiintrin.h, avx512vbmivlintrin.h. * config/i386/avx512vbmiintrin.h: New file. * config/i386/avx512vbmivlintrin.h: Ditto. * config/i386/cpuid.h (bit_AVX512VBMI): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512vbmi. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512VBMI__. * config/i386/i386.c (ix86_target_string): Add -mavx512vbmi. (PTA_AVX512VBMI): Define. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Add avx512vbmi, (ix86_builtins): Add IX86_BUILTIN_VPMULTISHIFTQB512, IX86_BUILTIN_VPMULTISHIFTQB256, IX86_BUILTIN_VPMULTISHIFTQB128, IX86_BUILTIN_VPERMVARQI512_MASK, IX86_BUILTIN_VPERMT2VARQI512, IX86_BUILTIN_VPERMT2VARQI512_MASKZ, IX86_BUILTIN_VPERMI2VARQI512, IX86_BUILTIN_VPERMVARQI256_MASK, IX86_BUILTIN_VPERMVARQI128_MASK, IX86_BUILTIN_VPERMT2VARQI256, IX86_BUILTIN_VPERMT2VARQI256_MASKZ, IX86_BUILTIN_VPERMT2VARQI128, IX86_BUILTIN_VPERMI2VARQI256, IX86_BUILTIN_VPERMI2VARQI128. (bdesc_special_args): Add __builtin_ia32_vpmultishiftqb512_mask, __builtin_ia32_vpmultishiftqb256_mask, __builtin_ia32_vpmultishiftqb128_mask, __builtin_ia32_permvarqi512_mask, __builtin_ia32_vpermt2varqi512_mask, __builtin_ia32_vpermt2varqi512_maskz, __builtin_ia32_vpermi2varqi512_mask, __builtin_ia32_permvarqi256_mask, __builtin_ia32_permvarqi128_mask, __builtin_ia32_vpermt2varqi256_mask, __builtin_ia32_vpermt2varqi256_maskz, __builtin_ia32_vpermt2varqi128_mask, __builtin_ia32_vpermt2varqi128_maskz, __builtin_ia32_vpermi2varqi256_mask, __builtin_ia32_vpermi2varqi128_mask. (ix86_hard_regno_mode_ok): Allow big masks for AVX512VBMI. * config/i386/i386.h (TARGET_AVX512VBMI, TARGET_AVX512VBMI_P): Define. * config/i386/i386.opt: Add mavx512vbmi. * config/i386/immintrin.h: Include avx512vbmiintrin.h, avx512vbmivlintrin.h. * config/i386/sse.md (unspec): Add UNSPEC_VPMULTISHIFT. (VI1_AVX512VL): New iterator. (<avx512>_permvar<mode><mask_name>): Use it. (<avx512>_vpermi2var<mode>3_maskz): Ditto. (<avx512>_vpermi2var<mode>3<sd_maskz_name>): Ditto. (<avx512>_vpermi2var<mode>3_mask): Ditto. (<avx512>_vpermt2var<mode>3_maskz): Ditto. (<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto. (<avx512>_vpermt2var<mode>3_mask): Ditto. (vpmultishiftqb<mode><mask_name>): Ditto. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mavx512vbmi. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx512f-helper.h: Add avx512vbmi-check.h. * gcc.target/i386/avx512vbmi-check.h: Ditto. * gcc.target/i386/avx512vbmi-vpermb-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermb-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpermi2b-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermi2b-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpermt2b-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpermt2b-2.c: Ditto. * gcc.target/i386/avx512vbmi-vpmultishiftqb-1.c: Ditto. * gcc.target/i386/avx512vbmi-vpmultishiftqb-2.c: Ditto. * gcc.target/i386/avx512vl-vpermb-2.c: Ditto. * gcc.target/i386/avx512vl-vpermi2b-2.c: Ditto. * gcc.target/i386/avx512vl-vpermt2b-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddluq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmultishiftqb-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512vbmi): New. * gcc.target/i386/sse-12.c: Add new options. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. From-SVN: r217932
2014-11-21Add avx512ifma instructions.Ilya Tocar1-0/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512IFMA_SET, OPTION_MASK_ISA_AVX512IFMA_UNSET): New. (ix86_handle_option): Handle OPT_mavx512ifma. * config.gcc: Add avx512ifmaintrin.h, avx512ifmavlintrin.h. * config/i386/avx512ifmaintrin.h: New file. * config/i386/avx512ifmaivlntrin.h: Ditto. * config/i386/cpuid.h (bit_AVX512IFMA): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512ifma. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512IFMA__. * config/i386/i386.c (ix86_target_string): Add -mavx512ifma. (PTA_AVX512IFMA): Define. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Add avx512ifma. (ix86_builtins): Add IX86_BUILTIN_VPMADD52LUQ512, IX86_BUILTIN_VPMADD52HUQ512, IX86_BUILTIN_VPMADD52LUQ256, IX86_BUILTIN_VPMADD52HUQ256, IX86_BUILTIN_VPMADD52LUQ128, IX86_BUILTIN_VPMADD52HUQ128, IX86_BUILTIN_VPMADD52LUQ512_MASKZ, IX86_BUILTIN_VPMADD52HUQ512_MASKZ, IX86_BUILTIN_VPMADD52LUQ256_MASKZ, IX86_BUILTIN_VPMADD52HUQ256_MASKZ, IX86_BUILTIN_VPMADD52LUQ128_MASKZ, IX86_BUILTIN_VPMADD52HUQ128_MASKZ. (bdesc_special_args): Add __builtin_ia32_vpmadd52luq512_mask, __builtin_ia32_vpmadd52luq512_maskz, __builtin_ia32_vpmadd52huq512_mask, __builtin_ia32_vpmadd52huq512_maskx, __builtin_ia32_vpmadd52luq256_mask, __builtin_ia32_vpmadd52luq256_maskz, __builtin_ia32_vpmadd52huq256_mask, __builtin_ia32_vpmadd52huq256_maskz, __builtin_ia32_vpmadd52luq128_mask, __builtin_ia32_vpmadd52luq128_maskz, __builtin_ia32_vpmadd52huq128_mask, __builtin_ia32_vpmadd52huq128_maskz, * config/i386/i386.h (TARGET_AVX512IFMA, TARGET_AVX512IFMA_P): Define. * config/i386/i386.opt: Add mavx512ifma. * config/i386/immintrin.h: Include avx512ifmaintrin.h, avx512ifmavlintrin.h. * config/i386/sse.md (unspec): Add UNSPEC_VPMADD52LUQ, UNSPEC_VPMADD52HUQ. (VPMADD52): New iterator. (vpmadd52type): New attribute. (vpamdd52huq<mode>_maskz): New. (vpamdd52luq<mode>_maskz): Ditto. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Ditto. (vpamdd52<vpmadd52type><mode>_mask): Ditto. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mavx512ifma. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx512f-helper.h: Add avx512ifma-check.h. * gcc.target/i386/avx512ifma-check.h: New. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx512vl-vpmaddluq-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512ifma): New. * gcc.target/i386/sse-12.c: Add new options. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. 2014-11-21 Georg-Johann Lay <avr@gjlay.de> From-SVN: r217928
2014-10-28AVX-512. 85/n. Add intrinsics headers.Alexander Ivchenko1-0/+10
gcc/ * config/i386/avx512bwintrin.h: New. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512vlbwintrin.h: Ditto. * config/i386/avx512vldqintrin.h: Ditto. * config/i386/avx512vlintrin.h: Ditto. * config/i386/immintrin.h: Include avx512vlintrin.h, avx512bwintrin.h, avx512dqintrin.h, avx512vlbwintrin.h, avx512vldqintrin.h. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r216798
2014-01-02Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r206289
2013-12-31i386-common.c (OPTION_MASK_ISA_SHA_SET): New.Alexander Ivchenko1-0/+2
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_SHA_SET): New. (OPTION_MASK_ISA_SHA_UNSET): Ditto. (ix86_handle_option): Handle OPT_msha. * config.gcc (extra_headers): Add shaintrin.h. * config/i386/cpuid.h (bit_SHA): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect SHA instructions. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_SHA. * config/i386/i386.c (ix86_target_string): Add -msha. (ix86_option_override_internal): Add PTA_SHA. (ix86_valid_target_attribute_inner_p): Handle OPT_msha. (enum ix86_builtins): Add IX86_BUILTIN_SHA1MSG1, IX86_BUILTIN_SHA1MSG2, IX86_BUILTIN_SHA1NEXTE, IX86_BUILTIN_SHA1RNDS4, IX86_BUILTIN_SHA256MSG1, IX86_BUILTIN_SHA256MSG2, IX86_BUILTIN_SHA256RNDS2. (bdesc_args): Add BUILTINS defined above. (ix86_init_mmx_sse_builtins): Add __builtin_ia32_sha1msg1, __builtin_ia32_sha1msg2, __builtin_ia32_sha1nexte, __builtin_ia32_sha1rnds4, __builtin_ia32_sha256msg1, __builtin_ia32_sha256msg2, __builtin_ia32_sha256rnds2. (ix86_expand_args_builtin): Handle V4SI_FTYPE_V4SI_V4SI_V4SI, add warning for CODE_FOR_sha1rnds4. * config/i386/i386.h (TARGET_SHA): New. (TARGET_SHA_P): Ditto. * config/i386/i386.opt (-msha): Document it. * config/i386/immintrin.h: Add shaintrin.h. * config/i386/shaintrin.h: New. * config/i386/sse.md (unspec): Add UNSPEC_SHA1MSG1, UNSPEC_SHA1MSG2, UNSPEC_SHA1NEXTE, UNSPEC_SHA1RNDS4, UNSPEC_SHA256MSG1, UNSPEC_SHA256MSG2, UNSPEC_SHA256RNDS2. (sha1msg1): New. (sha1msg2): Ditto. (sha1nexte): Ditto. (sha1rnds4): Ditto. (sha256msg1): Ditto. (sha256msg2): Ditto. (sha256rnds2): Ditto. * doc/invoke.texi: Add -msha. testsuite/ * gcc.target/i386/avx-1.c: Add define for __builtin_ia32_sha1rnds4. * gcc.target/i386/i386.exp (check_effective_target_sha): New. * gcc.target/i386/sha-check.h: New file. * gcc.target/i386/sha1msg1-1.c: Ditto. * gcc.target/i386/sha1msg1-2.c: Ditto. * gcc.target/i386/sha1msg2-1.c: Ditto. * gcc.target/i386/sha1msg2-2.c: Ditto. * gcc.target/i386/sha1nexte-1: Ditto. * gcc.target/i386/sha1nexte-2: Ditto. * gcc.target/i386/sha1rnds4-1.c: Ditto. * gcc.target/i386/sha1rnds4-2.c: Ditto. * gcc.target/i386/sha256msg1-1.c: Ditto. * gcc.target/i386/sha256msg1-2.c: Ditto. * gcc.target/i386/sha256msg2-1.c: Ditto. * gcc.target/i386/sha256msg2-2.c: Ditto. * gcc.target/i386/sha256rnds2-1.c: Ditto. * gcc.target/i386/sha256rnds2-2.c: Ditto. * gcc.target/i386/sse-13.c: Add __builtin_ia32_sha1rnds4. * gcc.target/i386/sse-14.c: Add _mm_sha1rnds4_epu32. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Add __builtin_ia32_sha1rnds4. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> Co-Authored-By: Sergey Lega <sergey.s.lega@intel.com> From-SVN: r206263
2013-12-31config.gcc (extra_headers): Add avx512fintrin.h, avx512cdintrin.h, ↵Alexander Ivchenko1-0/+8
avx512erintrin.h, avx512pfintrin.h. gcc/ * config.gcc (extra_headers): Add avx512fintrin.h, avx512cdintrin.h, avx512erintrin.h, avx512pfintrin.h. * config/i386/avx512cdintrin.h: New file. * config/i386/avx512erintrin.h: New file. * config/i386/avx512fintrin.h: New file. * config/i386/avx512pfintrin.h: New file. * config/i386/i386-builtin-types.def: Add V16UHI, V32SF, V16SF, V8DF, V8DI, V16SI, V64QI, PV8DF, PV8DI, PV16SI, PV16SF, PCV8DF, PCV16SF, PCV8DI, PCV16SI, V16QI_FTYPE_V16SI, V8DF_FTYPE_V8SI, V8DF_FTYPE_V8DF, V8HI_FTYPE_V8DI, V16SF_FTYPE_V16SF, V8SI_FTYPE_V8DI, V8SF_FTYPE_V8DF, V8SF_FTYPE_V8DF_V8SF_QI, V16HI_FTYPE_V16SI, V16SF_FTYPE_FLOAT, V16SI_FTYPE_INT, V8DF_FTYPE_DOUBLE, V8DI_FTYPE_INT64, V16SF_FTYPE_V4SF, V8DF_FTYPE_V4DF, V8DI_FTYPE_V4DI, V16QI_FTYPE_V8DI, UINT_FTYPE_V4SF, UINT64_FTYPE_V4SF, UINT_FTYPE_V2DF, UINT64_FTYPE_V2DF, V16SI_FTYPE_V16SI, V16SI_FTYPE_V16SI_V16SI_HI, V8DI_FTYPE_V8DI, V8DI_FTYPE_V8DI_V8DI_QI, V16SI_FTYPE_PV4SI, V16SF_FTYPE_PV4SF, V8DI_FTYPE_PV4DI, V8DF_FTYPE_PV4DF, V8UHI_FTYPE_V8UHI, V8USI_FTYPE_V8USI, V2DF_FTYPE_V2DF_UINT, V2DF_FTYPE_V2DF_UINT64, V4DF_FTYPE_V8DF_INT, V4DF_FTYPE_V8DF_INT_V4DF_QI, V8DF_FTYPE_V8DF_V8DI, V4SF_FTYPE_V4SF_UINT, V4SF_FTYPE_V4SF_UINT64, INT_FTYPE_V4SF_V4SF_INT_INT, INT_FTYPE_V2DF_V2DF_INT_INT, V16SF_FTYPE_V16SF_INT, V4SF_FTYPE_V16SF_INT, V4SF_FTYPE_V16SF_INT_V4SF_QI, V16SF_FTYPE_V16SF_V16SF, V16SF_FTYPE_V16SF_V16SI, V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI, V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI, V8DF_FTYPE_V8DF_INT_V8DF_QI, V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT, V8DF_FTYPE_V8DF_V8DF, V16SF_FTYPE_V16SF_V16SF_INT, V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI, V16SF_FTYPE_V16SF_INT_V16SF_HI, V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI, V16SF_FTYPE_V16SF_V16SF_V16SI_INT, V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI, V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT, V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI, V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT, V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI, V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT, V16SF_FTYPE_V16SF_V4SF_INT, V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI, V16HI_FTYPE_V16SF_INT, V16HI_FTYPE_V16SF_INT_V16HI_HI, V16HI_FTYPE_V16HI_V16HI_INT_V16HI_HI, V16SI_FTYPE_V16SI_V4SI, V16SI_FTYPE_V16SI_V4SI_INT, V4SI_FTYPE_V16SI_INT, V4SI_FTYPE_V16SI_INT_V4SI_QI, V16SI_FTYPE_V16SI_V16SI, V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI, V16SI_FTYPE_V16SI_SI, V16SI_FTYPE_V16SI_INT, V16SI_FTYPE_V16SI_V4SI_V16SI_HI, V16SI_FTYPE_V16SI_INT_V16SI_HI, V8DI_FTYPE_V8DI_V8DI, V16SI_FTYPE_V8DF_V8DF, V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI, V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI, V8DI_FTYPE_V8DI_V2DI, V4DI_FTYPE_V8DI_INT, V4DI_FTYPE_V8DI_INT_V4DI_QI, V8DI_FTYPE_V8DI_V2DI_V8DI_QI, V8DI_FTYPE_V8DI_INT_V8DI_QI, VOID_FTYPE_PDOUBLE_V8DF, VOID_FTYPE_PFLOAT_V16SF, VOID_FTYPE_PV8DI_V8DI, HI_FTYPE_HI, HI_FTYPE_HI_HI, HI_FTYPE_HI_INT, QI_FTYPE_V8DI_V8DI, QI_FTYPE_V8DI_V8DI_QI, HI_FTYPE_V16SI_V16SI, HI_FTYPE_V16SI_V16SI_HI, QI_FTYPE_V8DI_V8DI_INT, QI_FTYPE_V8DI_V8DI_INT_QI, HI_FTYPE_V16SI_V16SI_INT, HI_FTYPE_V16SI_V16SI_INT ,HI, QI_FTYPE_V8DF_V8DF_INT, QI_FTYPE_V8DF_V8DF_INT_QI, QI_FTYPE_V8DF_V8DF_INT_QI_INT, HI_FTYPE_V16SF_V16SF_INT, HI_FTYPE_V16SF_V16SF_INT_HI, HI_FTYPE_V16SF_V16SF_INT_HI_INT, QI_FTYPE_V2DF_V2DF_INT, QI_FTYPE_V2DF_V2DF_INT_QI, QI_FTYPE_V2DF_V2DF_INT_QI_INT, QI_FTYPE_V4SF_V4SF_INT, QI_FTYPE_V4SF_V4SF_INT_QI, QI_FTYPE_V4SF_V4SF_INT_QI_INT, V16SI_FTYPE_HI, V8DI_FTYPE_QI, V8DF_FTYPE_V8DF_V8DF_V8DF, V16SF_FTYPE_V16SF_V16SF_V16SF, V8DF_FTYPE_V8DF_V8DF_QI, V8DF_FTYPE_V8SF_V8DF_QI, V8DF_FTYPE_V8SI_V8DF_QI, V8DI_FTYPE_V8SI_V8DI_QI, V8DI_FTYPE_V8HI_V8DI_QI, V8DI_FTYPE_V16QI_V8DI_QI, V8DI_FTYPE_V8DI_V8DI_V8DI_QI, V8DF_FTYPE_V8DI_V8DF_V8DF, V8DF_FTYPE_V8DI_V8DF_V8DF_QI, V8DF_FTYPE_V8DF_V8DI_V8DF_QI, V8DF_FTYPE_V8DF_V8DF_V8DF_QI, V16SI_FTYPE_V16SI_V16SI_V16SI_HI, V2DF_FTYPE_V2DF_V2DF_V2DF_QI, V2DF_FTYPE_V2DF_V4SF_V2DF_QI, V16SF_FTYPE_V16SF_V16SF_HI, V16SF_FTYPE_V16SI_V16SF_HI, V16SF_FTYPE_V16SF_V16SF_V16SF_HI, V16SF_FTYPE_V16SI_V16SF_V16SF, V16SF_FTYPE_V16SI_V16SF_V16SF_HI, V16SF_FTYPE_V16SF_V16SI_V16SF_HI, V4SF_FTYPE_V4SF_V2DF_V4SF_QI, V4SF_FTYPE_V4SF_V4SF_V4SF_QI, V16SF_FTYPE_V4SF_V16SF_HI, V8DF_FTYPE_V4DF_V8DF_QI, V8DF_FTYPE_V2DF_V8DF_QI, V16SI_FTYPE_V4SI_V16SI_HI, V16SI_FTYPE_SI_V16SI_HI, V16SI_FTYPE_V16HI_V16SI_HI, V16SI_FTYPE_V16QI_V16SI_HI, V8SI_FTYPE_V8DF_V8SI_QI, V8DI_FTYPE_V4DI_V8DI_QI, V8DI_FTYPE_V2DI_V8DI_QI, V8DI_FTYPE_DI_V8DI_QI, V16SF_FTYPE_PCV16SF_V16SF_HI, V8DF_FTYPE_PCV8DF_V8DF_QI, V16SI_FTYPE_PCV16SI_V16SI_HI, V8DI_FTYPE_PCV8DI_V8DI_QI, V2DF_FTYPE_PCDOUBLE_V2DF_QI, V4SF_FTYPE_PCFLOAT_V4SF_QI, V16QI_FTYPE_V16SI_V16QI_HI, V16HI_FTYPE_V16SI_V16HI_HI, V8SI_FTYPE_V8DI_V8SI_QI, V8HI_FTYPE_V8DI_V8HI_QI, V16QI_FTYPE_V8DI_V16QI_QI, VOID_FTYPE_PV8DF_V8DF_QI, VOID_FTYPE_PV16SF_V16SF_HI, VOID_FTYPE_PV8DI_V8DI_QI, VOID_FTYPE_PV16SI_V16SI_HI, VOID_FTYPE_PDOUBLE_V2DF_QI, VOID_FTYPE_PFLOAT_V4SF_QI, V16SI_FTYPE_V16SF_V16SI_HI, V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI, V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI, V8DI_FTYPE_V8DI_V8DI_V8DI, V16SI_FTYPE_V16SI_V16SI_V16SI, V8DF_FTYPE_V8DF_V8DI_V8DF, V16SF_FTYPE_V16SF_V16SI_V16SF, V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI, V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI, V8DI_FTYPE_V16SI_V16SI_V8DI_QI, UINT64_FTYPE_V2DF_INT, UINT64_FTYPE_V4SF_INT, UINT_FTYPE_V2DF_INT, UINT_FTYPE_V4SF_INT, INT64_FTYPE_V2DF_INT, INT64_FTYPE_V4SF_INT, INT_FTYPE_V2DF_INT, INT_FTYPE_V4SF_INT, V2DF_FTYPE_V2DF_UINT64_INT, V4SF_FTYPE_V4SF_UINT64_INT, V4SF_FTYPE_V4SF_UINT_INT, V2DF_FTYPE_V2DF_INT64_INT, V4SF_FTYPE_V4SF_INT64_INT, V4SF_FTYPE_V4SF_INT_INT, V16SI_FTYPE_V16SF_V16SI_HI_INT, V16SF_FTYPE_V16SI_V16SF_HI_INT, V16SF_FTYPE_V16SF_V16SF_HI_INT, V16SF_FTYPE_V16HI_V16SF_HI_INT, V8SI_FTYPE_V8DF_V8SI_QI_INT, V8SF_FTYPE_V8DF_V8SF_QI_INT, V8DF_FTYPE_V8DF_V8DF_QI_INT, V8DF_FTYPE_V8SF_V8DF_QI_INT, V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT, V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT, V4SF_FTYPE_V4SF_V4SF_V4SF_QI_INT, V4SF_FTYPE_V4SF_V2DF_V4SF_QI_INT, V2DF_FTYPE_V2DF_V2DF_V2DF_QI_INT, V2DF_FTYPE_V2DF_V4SF_V2DF_QI_INT, V2DF_FTYPE_V2DF_V2DF_V2DF_INT, V16SF_FTYPE_V16SF_INT_V16SF_HI_INT, V8DF_FTYPE_V8DF_INT_V8DF_QI_INT, V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI_INT, V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI_INT, V8DI_FTYPE_V8DI_SI_V8DI_V8DI, V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT, V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT, V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT, V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT, V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT, V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT, V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT, V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT, V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT, V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT, V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT, V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT, VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT, VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT, VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT, VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT, VOID_FTYPE_PINT_HI_V16SI_V16SI_INT, VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT, VOID_FTYPE_PINT_QI_V8DI_V8SI_INT, VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT, VOID_FTYPE_HI_V16SI_PCINT_INT_INT, VOID_FTYPE_QI_V8DI_PCINT_INT_INT. (ALIAS): Add DEF_FUNCTION_TYPE_ALIAS (V16SI_FTYPE_V8DF_V8DF, ROUND). * config/i386/i386.c (enum ix86_builtins): Add IX86_BUILTIN_ADDPD512, IX86_BUILTIN_ADDPS512, IX86_BUILTIN_ADDSD_MASK, IX86_BUILTIN_ADDSS_MASK, IX86_BUILTIN_ALIGND512, IX86_BUILTIN_ALIGNQ512, IX86_BUILTIN_BLENDMD512, IX86_BUILTIN_BLENDMPD512, IX86_BUILTIN_BLENDMPS512, IX86_BUILTIN_BLENDMQ512, IX86_BUILTIN_BROADCASTF32X4_512, IX86_BUILTIN_BROADCASTF64X4_512, IX86_BUILTIN_BROADCASTI32X4_512, IX86_BUILTIN_BROADCASTI64X4_512, IX86_BUILTIN_BROADCASTSD512, IX86_BUILTIN_BROADCASTSS512, IX86_BUILTIN_CMPD512, IX86_BUILTIN_CMPPD512, IX86_BUILTIN_CMPPS512, IX86_BUILTIN_CMPQ512, IX86_BUILTIN_CMPSD_MASK, IX86_BUILTIN_CMPSS_MASK, IX86_BUILTIN_COMIDF, IX86_BUILTIN_COMISF, IX86_BUILTIN_COMPRESSPD512, IX86_BUILTIN_COMPRESSPDSTORE512, IX86_BUILTIN_COMPRESSPS512, IX86_BUILTIN_COMPRESSPSSTORE512, IX86_BUILTIN_CVTDQ2PD512, IX86_BUILTIN_CVTDQ2PS512, IX86_BUILTIN_CVTPD2DQ512, IX86_BUILTIN_CVTPD2PS512, IX86_BUILTIN_CVTPD2UDQ512, IX86_BUILTIN_CVTPH2PS512, IX86_BUILTIN_CVTPS2DQ512, IX86_BUILTIN_CVTPS2PD512, IX86_BUILTIN_CVTPS2PH512, IX86_BUILTIN_CVTPS2UDQ512, IX86_BUILTIN_CVTSD2SS_MASK, IX86_BUILTIN_CVTSI2SD64, IX86_BUILTIN_CVTSI2SS32, IX86_BUILTIN_CVTSI2SS64, IX86_BUILTIN_CVTSS2SD_MASK, IX86_BUILTIN_CVTTPD2DQ512, IX86_BUILTIN_CVTTPD2UDQ512, IX86_BUILTIN_CVTTPS2DQ512, IX86_BUILTIN_CVTTPS2UDQ512, IX86_BUILTIN_CVTUDQ2PD512, IX86_BUILTIN_CVTUDQ2PS512, IX86_BUILTIN_CVTUSI2SD32, IX86_BUILTIN_CVTUSI2SD64, IX86_BUILTIN_CVTUSI2SS32, IX86_BUILTIN_CVTUSI2SS64, IX86_BUILTIN_DIVPD512, IX86_BUILTIN_DIVPS512, IX86_BUILTIN_DIVSD_MASK, IX86_BUILTIN_DIVSS_MASK, IX86_BUILTIN_EXPANDPD512, IX86_BUILTIN_EXPANDPD512Z, IX86_BUILTIN_EXPANDPDLOAD512, IX86_BUILTIN_EXPANDPDLOAD512Z, IX86_BUILTIN_EXPANDPS512, IX86_BUILTIN_EXPANDPS512Z, IX86_BUILTIN_EXPANDPSLOAD512, IX86_BUILTIN_EXPANDPSLOAD512Z, IX86_BUILTIN_EXTRACTF32X4, IX86_BUILTIN_EXTRACTF64X4, IX86_BUILTIN_EXTRACTI32X4, IX86_BUILTIN_EXTRACTI64X4, IX86_BUILTIN_FIXUPIMMPD512_MASK, IX86_BUILTIN_FIXUPIMMPD512_MASKZ, IX86_BUILTIN_FIXUPIMMPS512_MASK, IX86_BUILTIN_FIXUPIMMPS512_MASKZ, IX86_BUILTIN_FIXUPIMMSD128_MASK, IX86_BUILTIN_FIXUPIMMSD128_MASKZ, IX86_BUILTIN_FIXUPIMMSS128_MASK, IX86_BUILTIN_FIXUPIMMSS128_MASKZ, IX86_BUILTIN_GETEXPPD512, IX86_BUILTIN_GETEXPPS512, IX86_BUILTIN_GETEXPSD128, IX86_BUILTIN_GETEXPSS128, IX86_BUILTIN_GETMANTPD512, IX86_BUILTIN_GETMANTPS512, IX86_BUILTIN_GETMANTSD128, IX86_BUILTIN_GETMANTSS128, IX86_BUILTIN_INSERTF32X4, IX86_BUILTIN_INSERTF64X4, IX86_BUILTIN_INSERTI32X4, IX86_BUILTIN_INSERTI64X4, IX86_BUILTIN_LOADAPD512, IX86_BUILTIN_LOADAPS512, IX86_BUILTIN_LOADDQUDI512, IX86_BUILTIN_LOADDQUSI512, IX86_BUILTIN_LOADSD, IX86_BUILTIN_LOADSS, IX86_BUILTIN_LOADUPD512, IX86_BUILTIN_LOADUPS512, IX86_BUILTIN_MAXPD512, IX86_BUILTIN_MAXPS512, IX86_BUILTIN_MAXSD_MASK, IX86_BUILTIN_MAXSS_MASK, IX86_BUILTIN_MINPD512, IX86_BUILTIN_MINPS512, IX86_BUILTIN_MINSD_MASK, IX86_BUILTIN_MINSS_MASK, IX86_BUILTIN_MOVAPD512, IX86_BUILTIN_MOVAPS512, IX86_BUILTIN_MOVDDUP512, IX86_BUILTIN_MOVDQA32LOAD512, IX86_BUILTIN_MOVDQA32STORE512, IX86_BUILTIN_MOVDQA32_512, IX86_BUILTIN_MOVDQA64LOAD512, IX86_BUILTIN_MOVDQA64STORE512, IX86_BUILTIN_MOVDQA64_512, IX86_BUILTIN_MOVESD, IX86_BUILTIN_MOVESS, IX86_BUILTIN_MOVNTDQ512, IX86_BUILTIN_MOVNTPD512, IX86_BUILTIN_MOVNTPS512, IX86_BUILTIN_MOVSHDUP512, IX86_BUILTIN_MOVSLDUP512, IX86_BUILTIN_MULPD512, IX86_BUILTIN_MULPS512, IX86_BUILTIN_MULSD_MASK, IX86_BUILTIN_MULSS_MASK, IX86_BUILTIN_PABSD512, IX86_BUILTIN_PABSQ512, IX86_BUILTIN_PADDD512, IX86_BUILTIN_PADDQ512, IX86_BUILTIN_PANDD512, IX86_BUILTIN_PANDND512, IX86_BUILTIN_PANDNQ512, IX86_BUILTIN_PANDQ512, IX86_BUILTIN_PBROADCASTD512, IX86_BUILTIN_PBROADCASTD512_GPR, IX86_BUILTIN_PBROADCASTMB512, IX86_BUILTIN_PBROADCASTMW512, IX86_BUILTIN_PBROADCASTQ512, IX86_BUILTIN_PBROADCASTQ512_GPR, IX86_BUILTIN_PBROADCASTQ512_MEM, IX86_BUILTIN_PCMPEQD512_MASK, IX86_BUILTIN_PCMPEQQ512_MASK, IX86_BUILTIN_PCMPGTD512_MASK, IX86_BUILTIN_PCMPGTQ512_MASK, IX86_BUILTIN_PCOMPRESSD512, IX86_BUILTIN_PCOMPRESSDSTORE512, IX86_BUILTIN_PCOMPRESSQ512, IX86_BUILTIN_PCOMPRESSQSTORE512, IX86_BUILTIN_PEXPANDD512, IX86_BUILTIN_PEXPANDD512Z, IX86_BUILTIN_PEXPANDDLOAD512, IX86_BUILTIN_PEXPANDDLOAD512Z, IX86_BUILTIN_PEXPANDQ512, IX86_BUILTIN_PEXPANDQ512Z, IX86_BUILTIN_PEXPANDQLOAD512, IX86_BUILTIN_PEXPANDQLOAD512Z, IX86_BUILTIN_PMAXSD512, IX86_BUILTIN_PMAXSQ512, IX86_BUILTIN_PMAXUD512, IX86_BUILTIN_PMAXUQ512, IX86_BUILTIN_PMINSD512, IX86_BUILTIN_PMINSQ512, IX86_BUILTIN_PMINUD512, IX86_BUILTIN_PMINUQ512, IX86_BUILTIN_PMOVDB512, IX86_BUILTIN_PMOVDW512, IX86_BUILTIN_PMOVQB512, IX86_BUILTIN_PMOVQD512, IX86_BUILTIN_PMOVQW512, IX86_BUILTIN_PMOVSDB512, IX86_BUILTIN_PMOVSDW512, IX86_BUILTIN_PMOVSQB512, IX86_BUILTIN_PMOVSQD512, IX86_BUILTIN_PMOVSQW512, IX86_BUILTIN_PMOVSXBD512, IX86_BUILTIN_PMOVSXBQ512, IX86_BUILTIN_PMOVSXDQ512, IX86_BUILTIN_PMOVSXWD512, IX86_BUILTIN_PMOVSXWQ512, IX86_BUILTIN_PMOVUSDB512, IX86_BUILTIN_PMOVUSDW512, IX86_BUILTIN_PMOVUSQB512, IX86_BUILTIN_PMOVUSQD512, IX86_BUILTIN_PMOVUSQW512, IX86_BUILTIN_PMOVZXBD512, IX86_BUILTIN_PMOVZXBQ512, IX86_BUILTIN_PMOVZXDQ512, IX86_BUILTIN_PMOVZXWD512, IX86_BUILTIN_PMOVZXWQ512, IX86_BUILTIN_PMULDQ512, IX86_BUILTIN_PMULLD512, IX86_BUILTIN_PMULUDQ512, IX86_BUILTIN_PORD512, IX86_BUILTIN_PORQ512, IX86_BUILTIN_PROLD512, IX86_BUILTIN_PROLQ512, IX86_BUILTIN_PROLVD512, IX86_BUILTIN_PROLVQ512, IX86_BUILTIN_PRORD512, IX86_BUILTIN_PRORQ512, IX86_BUILTIN_PRORVD512, IX86_BUILTIN_PRORVQ512, IX86_BUILTIN_PSHUFD512, IX86_BUILTIN_PSLLD512, IX86_BUILTIN_PSLLDI512, IX86_BUILTIN_PSLLQ512, IX86_BUILTIN_PSLLQI512, IX86_BUILTIN_PSLLVV16SI, IX86_BUILTIN_PSLLVV8DI, IX86_BUILTIN_PSRAD512, IX86_BUILTIN_PSRADI512, IX86_BUILTIN_PSRAQ512, IX86_BUILTIN_PSRAQI512, IX86_BUILTIN_PSRAVV16SI, IX86_BUILTIN_PSRAVV8DI, IX86_BUILTIN_PSRLD512, IX86_BUILTIN_PSRLDI512, IX86_BUILTIN_PSRLQ512, IX86_BUILTIN_PSRLQI512, IX86_BUILTIN_PSRLVV16SI, IX86_BUILTIN_PSRLVV8DI, IX86_BUILTIN_PSUBD512, IX86_BUILTIN_PSUBQ512, IX86_BUILTIN_PTESTMD512, IX86_BUILTIN_PTESTMQ512, IX86_BUILTIN_PTESTNMD512, IX86_BUILTIN_PTESTNMQ512, IX86_BUILTIN_PUNPCKHDQ512, IX86_BUILTIN_PUNPCKHQDQ512, IX86_BUILTIN_PUNPCKLDQ512, IX86_BUILTIN_PUNPCKLQDQ512, IX86_BUILTIN_PXORD512, IX86_BUILTIN_PXORQ512, IX86_BUILTIN_RCP14PD512, IX86_BUILTIN_RCP14PS512, IX86_BUILTIN_RCP14SD, IX86_BUILTIN_RCP14SS, IX86_BUILTIN_RNDSCALEPD, IX86_BUILTIN_RNDSCALEPS, IX86_BUILTIN_RNDSCALESD, IX86_BUILTIN_RNDSCALESS, IX86_BUILTIN_RSQRT14PD512, IX86_BUILTIN_RSQRT14PS512, IX86_BUILTIN_RSQRT14SD, IX86_BUILTIN_RSQRT14SS, IX86_BUILTIN_SCALEFPD512, IX86_BUILTIN_SCALEFPS512, IX86_BUILTIN_SCALEFSD, IX86_BUILTIN_SCALEFSS, IX86_BUILTIN_SHUFPD512, IX86_BUILTIN_SHUFPS512, IX86_BUILTIN_SHUF_F32x4, IX86_BUILTIN_SHUF_F64x2, IX86_BUILTIN_SHUF_I32x4, IX86_BUILTIN_SHUF_I64x2, IX86_BUILTIN_SQRTPD512_MASK, IX86_BUILTIN_SQRTPS512_MASK, IX86_BUILTIN_SQRTSD_MASK, IX86_BUILTIN_SQRTSS_MASK, IX86_BUILTIN_STOREAPD512, IX86_BUILTIN_STOREAPS512, IX86_BUILTIN_STOREDQUDI512, IX86_BUILTIN_STOREDQUSI512, IX86_BUILTIN_STORESD, IX86_BUILTIN_STORESS, IX86_BUILTIN_STOREUPD512, IX86_BUILTIN_STOREUPS512, IX86_BUILTIN_SUBPD512, IX86_BUILTIN_SUBPS512, IX86_BUILTIN_SUBSD_MASK, IX86_BUILTIN_SUBSS_MASK, IX86_BUILTIN_UCMPD512, IX86_BUILTIN_UCMPQ512, IX86_BUILTIN_UNPCKHPD512, IX86_BUILTIN_UNPCKHPS512, IX86_BUILTIN_UNPCKLPD512, IX86_BUILTIN_UNPCKLPS512, IX86_BUILTIN_VCVTSD2SI32, IX86_BUILTIN_VCVTSD2SI64, IX86_BUILTIN_VCVTSD2USI32, IX86_BUILTIN_VCVTSD2USI64, IX86_BUILTIN_VCVTSS2SI32, IX86_BUILTIN_VCVTSS2SI64, IX86_BUILTIN_VCVTSS2USI32, IX86_BUILTIN_VCVTSS2USI64, IX86_BUILTIN_VCVTTSD2SI32, IX86_BUILTIN_VCVTTSD2SI64, IX86_BUILTIN_VCVTTSD2USI32, IX86_BUILTIN_VCVTTSD2USI64, IX86_BUILTIN_VCVTTSS2SI32, IX86_BUILTIN_VCVTTSS2SI64, IX86_BUILTIN_VCVTTSS2USI32, IX86_BUILTIN_VCVTTSS2USI64, IX86_BUILTIN_VFMADDPD512_MASK, IX86_BUILTIN_VFMADDPD512_MASK3, IX86_BUILTIN_VFMADDPD512_MASKZ, IX86_BUILTIN_VFMADDPS512_MASK, IX86_BUILTIN_VFMADDPS512_MASK3, IX86_BUILTIN_VFMADDPS512_MASKZ, IX86_BUILTIN_VFMADDSD3_MASK, IX86_BUILTIN_VFMADDSD3_MASK3, IX86_BUILTIN_VFMADDSD3_MASKZ, IX86_BUILTIN_VFMADDSS3_MASK, IX86_BUILTIN_VFMADDSS3_MASK3, IX86_BUILTIN_VFMADDSS3_MASKZ, IX86_BUILTIN_VFMADDSUBPD512_MASK, IX86_BUILTIN_VFMADDSUBPD512_MASK3, IX86_BUILTIN_VFMADDSUBPD512_MASKZ, IX86_BUILTIN_VFMADDSUBPS512_MASK, IX86_BUILTIN_VFMADDSUBPS512_MASK3, IX86_BUILTIN_VFMADDSUBPS512_MASKZ, IX86_BUILTIN_VFMSUBADDPD512_MASK3, IX86_BUILTIN_VFMSUBADDPS512_MASK3, IX86_BUILTIN_VFMSUBPD512_MASK3, IX86_BUILTIN_VFMSUBPS512_MASK3, IX86_BUILTIN_VFMSUBSD3_MASK3, IX86_BUILTIN_VFMSUBSS3_MASK3, IX86_BUILTIN_VFNMADDPD512_MASK, IX86_BUILTIN_VFNMADDPS512_MASK, IX86_BUILTIN_VFNMSUBPD512_MASK, IX86_BUILTIN_VFNMSUBPD512_MASK3, IX86_BUILTIN_VFNMSUBPS512_MASK, IX86_BUILTIN_VFNMSUBPS512_MASK3, IX86_BUILTIN_VPCLZCNTD512, IX86_BUILTIN_VPCLZCNTQ512, IX86_BUILTIN_VPCONFLICTD512, IX86_BUILTIN_VPCONFLICTQ512, IX86_BUILTIN_VPERMDF512, IX86_BUILTIN_VPERMDI512, IX86_BUILTIN_VPERMI2VARD512, IX86_BUILTIN_VPERMI2VARPD512, IX86_BUILTIN_VPERMI2VARPS512, IX86_BUILTIN_VPERMI2VARQ512, IX86_BUILTIN_VPERMILPD512, IX86_BUILTIN_VPERMILPS512, IX86_BUILTIN_VPERMILVARPD512, IX86_BUILTIN_VPERMILVARPS512, IX86_BUILTIN_VPERMT2VARD512, IX86_BUILTIN_VPERMT2VARD512_MASKZ, IX86_BUILTIN_VPERMT2VARPD512, IX86_BUILTIN_VPERMT2VARPD512_MASKZ, IX86_BUILTIN_VPERMT2VARPS512, IX86_BUILTIN_VPERMT2VARPS512_MASKZ, IX86_BUILTIN_VPERMT2VARQ512, IX86_BUILTIN_VPERMT2VARQ512_MASKZ, IX86_BUILTIN_VPERMVARDF512, IX86_BUILTIN_VPERMVARDI512, IX86_BUILTIN_VPERMVARSF512, IX86_BUILTIN_VPERMVARSI512, IX86_BUILTIN_VTERNLOGD512_MASK, IX86_BUILTIN_VTERNLOGD512_MASKZ, IX86_BUILTIN_VTERNLOGQ512_MASK, IX86_BUILTIN_VTERNLOGQ512_MASKZ, IX86_BUILTIN_KAND16, IX86_BUILTIN_KANDN16, IX86_BUILTIN_KNOT16, IX86_BUILTIN_KOR16, IX86_BUILTIN_KORTESTC16, IX86_BUILTIN_KORTESTZ16, IX86_BUILTIN_KUNPCKBW, IX86_BUILTIN_KXNOR16, IX86_BUILTIN_KXOR16, IX86_BUILTIN_GATHER3SIV8DI, IX86_BUILTIN_SCATTERDIV16SF, IX86_BUILTIN_SCATTERDIV16SI, IX86_BUILTIN_SCATTERDIV8DF, IX86_BUILTIN_SCATTERDIV8DI, IX86_BUILTIN_SCATTERSIV16SF, IX86_BUILTIN_SCATTERSIV16SI, IX86_BUILTIN_SCATTERSIV8DF, IX86_BUILTIN_SCATTERSIV8DI, IX86_BUILTIN_GATHERPFDPS, IX86_BUILTIN_GATHERPFQPS, IX86_BUILTIN_SCATTERPFDPS, IX86_BUILTIN_SCATTERPFQPS, IX86_BUILTIN_EXP2PD_MASK, IX86_BUILTIN_EXP2PS_MASK, IX86_BUILTIN_RCP28PD, IX86_BUILTIN_RCP28PS, IX86_BUILTIN_RSQRT28PD, IX86_BUILTIN_RSQRT28PS. (bdesc_special_args): Add __builtin_ia32_compressstoresf512_mask, __builtin_ia32_compressstoresi512_mask, __builtin_ia32_compressstoredf512_mask, __builtin_ia32_compressstoredi512_mask, __builtin_ia32_expandloadsf512_mask, __builtin_ia32_expandloadsf512_maskz, __builtin_ia32_expandloadsi512_mask, __builtin_ia32_expandloadsi512_maskz, __builtin_ia32_expandloaddf512_mask, __builtin_ia32_expandloaddf512_maskz, __builtin_ia32_expandloaddi512_mask, __builtin_ia32_expandloaddi512_maskz, __builtin_ia32_loaddqusi512_mask, __builtin_ia32_loaddqudi512_mask, __builtin_ia32_loadsd_mask, __builtin_ia32_loadss_mask, __builtin_ia32_loadupd512_mask, __builtin_ia32_loadups512_mask, __builtin_ia32_loadaps512_mask, __builtin_ia32_movdqa32load512_mask, __builtin_ia32_loadapd512_mask, __builtin_ia32_movdqa64load512_mask, __builtin_ia32_movntps512, __builtin_ia32_movntpd512, __builtin_ia32_movntdq512, __builtin_ia32_storedqusi512_mask, __builtin_ia32_storedqudi512_mask, __builtin_ia32_storesd_mask, __builtin_ia32_storess_mask, __builtin_ia32_storeupd512_mask, __builtin_ia32_storeups512_mask, __builtin_ia32_storeaps512_mask, __builtin_ia32_movdqa32store512_mask, __builtin_ia32_storeapd512_mask, __builtin_ia32_movdqa64store512_mask, __builtin_ia32_alignd512_mask, __builtin_ia32_alignq512_mask, __builtin_ia32_blendmd_512_mask, __builtin_ia32_blendmpd_512_mask, __builtin_ia32_blendmps_512_mask, __builtin_ia32_blendmq_512_mask, __builtin_ia32_broadcastf32x4_512, __builtin_ia32_broadcastf64x4_512, __builtin_ia32_broadcasti32x4_512, __builtin_ia32_broadcasti64x4_512, __builtin_ia32_broadcastsd512, __builtin_ia32_broadcastss512, __builtin_ia32_cmpd512_mask, __builtin_ia32_cmpq512_mask, __builtin_ia32_compressdf512_mask, __builtin_ia32_compresssf512_mask, __builtin_ia32_cvtdq2pd512_mask, __builtin_ia32_vcvtps2ph512_mask, __builtin_ia32_cvtudq2pd512_mask, __builtin_ia32_cvtusi2sd32, __builtin_ia32_expanddf512_mask, __builtin_ia32_expanddf512_maskz, __builtin_ia32_expandsf512_mask, __builtin_ia32_expandsf512_maskz, __builtin_ia32_extractf32x4_mask, __builtin_ia32_extractf64x4_mask, __builtin_ia32_extracti32x4_mask, __builtin_ia32_extracti64x4_mask, __builtin_ia32_insertf32x4_mask, __builtin_ia32_insertf64x4_mask, __builtin_ia32_inserti32x4_mask, __builtin_ia32_inserti64x4_mask, __builtin_ia32_movapd512_mask, __builtin_ia32_movaps512_mask, __builtin_ia32_movddup512_mask, __builtin_ia32_movdqa32_512_mask, __builtin_ia32_movdqa64_512_mask, __builtin_ia32_movesd_mask, __builtin_ia32_movess_mask, __builtin_ia32_movshdup512_mask, __builtin_ia32_movsldup512_mask, __builtin_ia32_pabsd512_mask, __builtin_ia32_pabsq512_mask, __builtin_ia32_paddd512_mask, __builtin_ia32_paddq512_mask, __builtin_ia32_pandd512_mask, __builtin_ia32_pandnd512_mask, __builtin_ia32_pandnq512_mask, __builtin_ia32_pandq512_mask, __builtin_ia32_pbroadcastd512, __builtin_ia32_pbroadcastd512_gpr_mask, __builtin_ia32_broadcastmb512, __builtin_ia32_broadcastmw512, __builtin_ia32_pbroadcastq512, __builtin_ia32_pbroadcastq512_gpr_mask, __builtin_ia32_pbroadcastq512_mem_mask, __builtin_ia32_pcmpeqd512_mask, __builtin_ia32_pcmpeqq512_mask, __builtin_ia32_pcmpgtd512_mask, __builtin_ia32_pcmpgtq512_mask, __builtin_ia32_compresssi512_mask, __builtin_ia32_compressdi512_mask, __builtin_ia32_expandsi512_mask, __builtin_ia32_expandsi512_maskz, __builtin_ia32_expanddi512_mask, __builtin_ia32_expanddi512_maskz, __builtin_ia32_pmaxsd512_mask, __builtin_ia32_pmaxsq512_mask, __builtin_ia32_pmaxud512_mask, __builtin_ia32_pmaxuq512_mask, __builtin_ia32_pminsd512_mask, __builtin_ia32_pminsq512_mask, __builtin_ia32_pminud512_mask, __builtin_ia32_pminuq512_mask, __builtin_ia32_pmovdb512_mask, __builtin_ia32_pmovdw512_mask, __builtin_ia32_pmovqb512_mask, __builtin_ia32_pmovqd512_mask, __builtin_ia32_pmovqw512_mask, __builtin_ia32_pmovsdb512_mask, __builtin_ia32_pmovsdw512_mask, __builtin_ia32_pmovsqb512_mask, __builtin_ia32_pmovsqd512_mask, __builtin_ia32_pmovsqw512_mask, __builtin_ia32_pmovsxbd512_mask, __builtin_ia32_pmovsxbq512_mask, __builtin_ia32_pmovsxdq512_mask, __builtin_ia32_pmovsxwd512_mask, __builtin_ia32_pmovsxwq512_mask, __builtin_ia32_pmovusdb512_mask, __builtin_ia32_pmovusdw512_mask, __builtin_ia32_pmovusqb512_mask, __builtin_ia32_pmovusqd512_mask, __builtin_ia32_pmovusqw512_mask, __builtin_ia32_pmovzxbd512_mask, __builtin_ia32_pmovzxbq512_mask, __builtin_ia32_pmovzxdq512_mask, __builtin_ia32_pmovzxwd512_mask, __builtin_ia32_pmovzxwq512_mask, __builtin_ia32_pmuldq512_mask, __builtin_ia32_pmulld512_mask, __builtin_ia32_pmuludq512_mask, __builtin_ia32_pord512_mask, __builtin_ia32_porq512_mask, __builtin_ia32_prold512_mask, __builtin_ia32_prolq512_mask, __builtin_ia32_prolvd512_mask, __builtin_ia32_prolvq512_mask, __builtin_ia32_prord512_mask, __builtin_ia32_prorq512_mask, __builtin_ia32_prorvd512_mask, __builtin_ia32_prorvq512_mask, __builtin_ia32_pshufd512_mask, __builtin_ia32_pslld512_mask, __builtin_ia32_pslldi512_mask, __builtin_ia32_psllq512_mask, __builtin_ia32_psllqi512_mask, __builtin_ia32_psllv16si_mask, __builtin_ia32_psllv8di_mask, __builtin_ia32_psrad512_mask, __builtin_ia32_psradi512_mask, __builtin_ia32_psraq512_mask, __builtin_ia32_psraqi512_mask, __builtin_ia32_psrav16si_mask, __builtin_ia32_psrav8di_mask, __builtin_ia32_psrld512_mask, __builtin_ia32_psrldi512_mask, __builtin_ia32_psrlq512_mask, __builtin_ia32_psrlqi512_mask, __builtin_ia32_psrlv16si_mask, __builtin_ia32_psrlv8di_mask, __builtin_ia32_psubd512_mask, __builtin_ia32_psubq512_mask, __builtin_ia32_ptestmd512, __builtin_ia32_ptestmq512, __builtin_ia32_ptestnmd512, __builtin_ia32_ptestnmq512, __builtin_ia32_punpckhdq512_mask, __builtin_ia32_punpckhqdq512_mask, __builtin_ia32_punpckldq512_mask, __builtin_ia32_punpcklqdq512_mask, __builtin_ia32_pxord512_mask, __builtin_ia32_pxorq512_mask, __builtin_ia32_rcp14pd512_mask, __builtin_ia32_rcp14ps512_mask, __builtin_ia32_rcp14sd_mask, __builtin_ia32_rcp14ss_mask, __builtin_ia32_rsqrt14pd512_mask, __builtin_ia32_rsqrt14ps512_mask, __builtin_ia32_rsqrt14sd_mask, __builtin_ia32_rsqrt14ss_mask, __builtin_ia32_shufpd512_mask, __builtin_ia32_shufps512_mask, __builtin_ia32_shuf_f32x4_mask, __builtin_ia32_shuf_f64x2_mask, __builtin_ia32_shuf_i32x4_mask, __builtin_ia32_shuf_i64x2_mask, __builtin_ia32_ucmpd512_mask, __builtin_ia32_ucmpq512_mask, __builtin_ia32_unpckhpd512_mask, __builtin_ia32_unpckhps512_mask, __builtin_ia32_unpcklpd512_mask, __builtin_ia32_unpcklps512_mask, __builtin_ia32_vplzcntd_512_mask, __builtin_ia32_vplzcntq_512_mask, __builtin_ia32_vpconflictsi_512_mask, __builtin_ia32_vpconflictdi_512_mask, __builtin_ia32_permdf512_mask, __builtin_ia32_permdi512_mask, __builtin_ia32_vpermi2vard512_mask, __builtin_ia32_vpermi2varpd512_mask, __builtin_ia32_vpermi2varps512_mask, __builtin_ia32_vpermi2varq512_mask, __builtin_ia32_vpermilpd512_mask, __builtin_ia32_vpermilps512_mask, __builtin_ia32_vpermilvarpd512_mask, __builtin_ia32_vpermilvarps512_mask, __builtin_ia32_vpermt2vard512_mask, __builtin_ia32_vpermt2vard512_maskz, __builtin_ia32_vpermt2varpd512_mask, __builtin_ia32_vpermt2varpd512_maskz, __builtin_ia32_vpermt2varps512_mask, __builtin_ia32_vpermt2varps512_maskz, __builtin_ia32_vpermt2varq512_mask, __builtin_ia32_vpermt2varq512_maskz, __builtin_ia32_permvardf512_mask, __builtin_ia32_permvardi512_mask, __builtin_ia32_permvarsf512_mask, __builtin_ia32_permvarsi512_mask, __builtin_ia32_pternlogd512_mask, __builtin_ia32_pternlogd512_maskz, __builtin_ia32_pternlogq512_mask, __builtin_ia32_pternlogq512_maskz, __builtin_ia32_copysignps512, __builtin_ia32_copysignpd512, __builtin_ia32_sqrtpd512, __builtin_ia32_sqrtps512, __builtin_ia32_exp2ps, __builtin_ia32_roundpd_az_vec_pack_sfix512, __builtin_ia32_floorpd_vec_pack_sfix512, __builtin_ia32_ceilpd_vec_pack_sfix512, __builtin_ia32_kandhi, __builtin_ia32_kandnhi, __builtin_ia32_knothi, __builtin_ia32_korhi, __builtin_ia32_kortestchi, __builtin_ia32_kortestzhi, __builtin_ia32_kunpckhi, __builtin_ia32_kxnorhi, __builtin_ia32_kxorhi, __builtin_ia32_addpd512_mask, __builtin_ia32_addps512_mask, __builtin_ia32_addsd_mask, __builtin_ia32_addss_mask, __builtin_ia32_cmppd512_mask, __builtin_ia32_cmpps512_mask, __builtin_ia32_cmpsd_mask, __builtin_ia32_cmpss_mask, __builtin_ia32_vcomisd, __builtin_ia32_vcomiss, __builtin_ia32_cvtdq2ps512_mask, __builtin_ia32_cvtpd2dq512_mask, __builtin_ia32_cvtpd2ps512_mask, __builtin_ia32_cvtpd2udq512_mask, __builtin_ia32_vcvtph2ps512_mask, __builtin_ia32_cvtps2dq512_mask, __builtin_ia32_cvtps2pd512_mask, __builtin_ia32_cvtps2udq512_mask, __builtin_ia32_cvtsd2ss_mask, __builtin_ia32_cvtsi2sd64, __builtin_ia32_cvtsi2ss32, __builtin_ia32_cvtsi2ss64, __builtin_ia32_cvtss2sd_mask, __builtin_ia32_cvttpd2dq512_mask, __builtin_ia32_cvttpd2udq512_mask, __builtin_ia32_cvttps2dq512_mask, __builtin_ia32_cvttps2udq512_mask, __builtin_ia32_cvtudq2ps512_mask, __builtin_ia32_cvtusi2sd64, __builtin_ia32_cvtusi2ss32, __builtin_ia32_cvtusi2ss64, __builtin_ia32_divpd512_mask, __builtin_ia32_divps512_mask, __builtin_ia32_divsd_mask, __builtin_ia32_divss_mask, __builtin_ia32_fixupimmpd512_mask, __builtin_ia32_fixupimmpd512_maskz, __builtin_ia32_fixupimmps512_mask, __builtin_ia32_fixupimmps512_maskz, __builtin_ia32_fixupimmsd_mask, __builtin_ia32_fixupimmsd_maskz, __builtin_ia32_fixupimmss_mask, __builtin_ia32_fixupimmss_maskz, __builtin_ia32_getexppd512_mask, __builtin_ia32_getexpps512_mask, __builtin_ia32_getexpsd128_mask, __builtin_ia32_getexpss128_mask, __builtin_ia32_getmantpd512_mask, __builtin_ia32_getmantps512_mask, __builtin_ia32_getmantsd_mask, __builtin_ia32_getmantss_mask, __builtin_ia32_maxpd512_mask, __builtin_ia32_maxps512_mask, __builtin_ia32_maxsd_mask, __builtin_ia32_maxss_mask, __builtin_ia32_minpd512_mask, __builtin_ia32_minps512_mask, __builtin_ia32_minsd_mask, __builtin_ia32_minss_mask, __builtin_ia32_mulpd512_mask, __builtin_ia32_mulps512_mask, __builtin_ia32_mulsd_mask, __builtin_ia32_mulss_mask, __builtin_ia32_rndscalepd_mask, __builtin_ia32_rndscaleps_mask, __builtin_ia32_rndscalesd_mask, __builtin_ia32_rndscaless_mask, __builtin_ia32_scalefpd512_mask, __builtin_ia32_scalefps512_mask, __builtin_ia32_scalefsd_mask, __builtin_ia32_scalefss_mask, __builtin_ia32_sqrtpd512_mask, __builtin_ia32_sqrtps512_mask, __builtin_ia32_sqrtsd_mask, __builtin_ia32_sqrtss_mask, __builtin_ia32_subpd512_mask, __builtin_ia32_subps512_mask, __builtin_ia32_subsd_mask, __builtin_ia32_subss_mask, __builtin_ia32_vcvtsd2si32, __builtin_ia32_vcvtsd2si64, __builtin_ia32_vcvtsd2usi32, __builtin_ia32_vcvtsd2usi64, __builtin_ia32_vcvtss2si32, __builtin_ia32_vcvtss2si64, __builtin_ia32_vcvtss2usi32, __builtin_ia32_vcvtss2usi64, __builtin_ia32_vcvttsd2si32, __builtin_ia32_vcvttsd2si64, __builtin_ia32_vcvttsd2usi32, __builtin_ia32_vcvttsd2usi64, __builtin_ia32_vcvttss2si32, __builtin_ia32_vcvttss2si64, __builtin_ia32_vcvttss2usi32, __builtin_ia32_vcvttss2usi64, __builtin_ia32_vfmaddpd512_mask, __builtin_ia32_vfmaddpd512_mask3, __builtin_ia32_vfmaddpd512_maskz, __builtin_ia32_vfmaddps512_mask, __builtin_ia32_vfmaddps512_mask3, __builtin_ia32_vfmaddps512_maskz, __builtin_ia32_vfmaddsd3_mask, __builtin_ia32_vfmaddsd3_mask3, __builtin_ia32_vfmaddsd3_maskz, __builtin_ia32_vfmaddss3_mask, __builtin_ia32_vfmaddss3_mask3, __builtin_ia32_vfmaddss3_maskz, __builtin_ia32_vfmaddsubpd512_mask, __builtin_ia32_vfmaddsubpd512_mask3, __builtin_ia32_vfmaddsubpd512_maskz, __builtin_ia32_vfmaddsubps512_mask, __builtin_ia32_vfmaddsubps512_mask3, __builtin_ia32_vfmaddsubps512_maskz, __builtin_ia32_vfmsubaddpd512_mask3, __builtin_ia32_vfmsubaddps512_mask3, __builtin_ia32_vfmsubpd512_mask3, __builtin_ia32_vfmsubps512_mask3, __builtin_ia32_vfmsubsd3_mask3, __builtin_ia32_vfmsubss3_mask3, __builtin_ia32_vfnmaddpd512_mask, __builtin_ia32_vfnmaddps512_mask, __builtin_ia32_vfnmsubpd512_mask, __builtin_ia32_vfnmsubpd512_mask3, __builtin_ia32_vfnmsubps512_mask, __builtin_ia32_vfnmsubps512_mask3, __builtin_ia32_exp2pd_mask, __builtin_ia32_exp2ps_mask, __builtin_ia32_rcp28pd_mask, __builtin_ia32_rcp28ps_mask, __builtin_ia32_rsqrt28pd_mask, __builtin_ia32_rsqrt28ps_mask, __builtin_ia32_gathersiv16sf, __builtin_ia32_gathersiv8df, __builtin_ia32_gatherdiv16sf, __builtin_ia32_gatherdiv8df, __builtin_ia32_gathersiv16si, __builtin_ia32_gathersiv8di, __builtin_ia32_gatherdiv16si, __builtin_ia32_gatherdiv8di, __builtin_ia32_gatheraltsiv8df , __builtin_ia32_gatheraltdiv8sf , __builtin_ia32_gatheraltsiv8di , __builtin_ia32_gatheraltdiv8si , __builtin_ia32_scattersiv16sf, __builtin_ia32_scattersiv8df, __builtin_ia32_scatterdiv16sf, __builtin_ia32_scatterdiv8df, __builtin_ia32_scattersiv16si, __builtin_ia32_scattersiv8di, __builtin_ia32_scatterdiv16si, __builtin_ia32_scatterdiv8di, __builtin_ia32_gatherpfdps, __builtin_ia32_gatherpfqps, __builtin_ia32_scatterpfdps, __builtin_ia32_scatterpfqps. (ix86_init_mmx_sse_builtins): Handle builtins with AVX512 embeded rounding, builtins for AVX512 gathers/scatters. (ix86_expand_args_builtin): Handle new functions types, add warnings for masked builtins. (ix86_erase_embedded_rounding): Handle patterns with embedded rounding. (ix86_expand_sse_comi_round): Ditto. (ix86_expand_round_builtin): Ditto. (ix86_expand_builtin): Handle AVX512's gathers/scatters and kortest{z}. Call ix86_expand_round_builtin. * config/i386/immintrin.h: Add avx512fintrin.h, avx512erintrin.h, avx512pfintrin.h, avx512cdintrin.h. testsuite/ * gcc.target/i386/avx-1.c: Extend to AVX-512. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> Co-Authored-By: Sergey Lega <sergey.s.lega@intel.com> From-SVN: r206261
2013-06-23Allow mmintrin headers to work with function specific target opts.Sriraman Tallam1-39/+30
Allow mmintrin headers to work with function specific target opts. Please see discussion here: http://gcc.gnu.org/ml/gcc-patches/2013-04/msg00740.html * config/i386/i386.c (ix86_pragma_target_parse): Restore target when current target options does not apply. * config/i386/i386-protos.h (ix86_reset_previous_fndecl): New function. * config/i386/i386.c (ix86_reset_previous_fndecl): Ditto. * config/i386/bmiintrin.h: Pass appropriate target attributes to header. * config/i386/mmintrin.h: Ditto. * config/i386/nmmintrin.h: Ditto. * config/i386/avx2intrin.h: Ditto. * config/i386/fxsrintrin.h: Ditto. * config/i386/tbmintrin.h: Ditto. * config/i386/xsaveintrin.h: Ditto. * config/i386/f16cintrin.h: Ditto. * config/i386/xtestintrin.h: Ditto. * config/i386/xsaveoptintrin.h: Ditto. * config/i386/bmi2intrin.h: Ditto. * config/i386/lzcntintrin.h: Ditto. * config/i386/smmintrin.h: Ditto. * config/i386/wmmintrin.h: Ditto. * config/i386/x86intrin.h: Remove all header include guards. * config/i386/prfchwintrin.h: Ditto. * config/i386/pmmintrin.h: Ditto. * config/i386/tmmintrin.h: Ditto. * config/i386/xmmintrin.h: Ditto. * config/i386/popcntintrin.h: Ditto. * config/i386/rdseedintrin.h: Ditto. * config/i386/ammintrin.h: Ditto. * config/i386/emmintrin.h: Ditto. * config/i386/immintrin.h: Remove all header include guards. * config/i386/fma4intrin.h: Ditto. * config/i386/lwpintrin.h: Ditto. * config/i386/xopintrin.h: Ditto. * config/i386/ia32intrin.h: Ditto. * config/i386/avxintrin.h: Ditto. * config/i386/rtmintrin.h: Ditto. * config/i386/fmaintrin.h: Ditto. * config/i386/mm3dnow.h: Ditto. * testsuite/gcc.target/i386/intrinsics_1.c: New test. * testsuite/gcc.target/i386/intrinsics_2.c: Ditto. * testsuite/gcc.target/i386/intrinsics_3.c: Ditto. * testsuite/gcc.target/i386/intrinsics_4.c: Ditto. * testsuite/gcc.target/i386/intrinsics_5.c: Ditto. * testsuite/gcc.target/i386/intrinsics_6.c: Ditto. * testsuite/gcc.target/i386/avx-1.c: Provide macros for builtins needing immediate arguments in f16cintrin.h and rtmintrin.h. From-SVN: r200349
2013-01-10Update copyright years in gcc/Richard Sandiford1-1/+1
From-SVN: r195098
2013-01-04Update Copyright years for files modified in 2011 and/or 2012.Jakub Jelinek1-1/+1
From-SVN: r194903
generated by cgit v1.1 at 2025-04-18 11:44:46 +0000