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AgeCommit message (Expand)AuthorFilesLines
2017-02-17i386-common.c (OPTION_MASK_ISA_RDPID_SET): New.Julia Koval1-1/+2
2017-02-13i386.h (REG_CLASS_NAMES): Add , in between "MOD4_SSE_REGS" and "ALL_REGS".Jakub Jelinek1-1/+1
2017-02-07re PR tree-optimization/79256 (FAIL: gcc.dg/vect/pr25413a.c execution test)Richard Biener1-2/+2
2017-01-17i386.h (MASK_CLASS_P): New define.Uros Bizjak1-0/+2
2017-01-17i386.h (LIMIT_RELOAD_CLASS): Remove.Uros Bizjak1-24/+0
2017-01-16i386.h (HARD_REGNO_CALLER_SAVE_MODE): Apply HImode and QImode fixups to gener...Uros Bizjak1-2/+3
2017-01-11i386-common.c (OPTION_MASK_ISA_SGX_UNSET): New.Julia Koval1-0/+2
2017-01-10Enable AVX-512 VPOPCNTD/VPOPCNTQ instructions.Andrew Senkevich1-0/+2
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
2016-12-14re PR target/78791 (ACATS cxf2001 failure)Jakub Jelinek1-0/+1
2016-12-12re PR target/78738 (ICE in extract_insn, at recog.c:2311)Uros Bizjak1-3/+6
2016-12-08i386.h (HARD_REGNO_NREGS): Use GENERAL_REGNO_P.Uros Bizjak1-11/+8
2016-11-23[Patch 7/17] Delete TARGET_FLT_EVAL_METHOD and poison it.James Greenhalgh1-11/+0
2016-11-17Enable AVX512_4FMAPS and AVX512_4VNNIW instructionsKirill Yukhin1-3/+21
2016-11-15Fix instances of gen_rtx_REG (VOIDmode, ...)Richard Sandiford1-1/+1
2016-10-17i386.h (TARGET_CUSTOM_FUNCTION_DESCRIPTORS): Move to...Eric Botcazou1-3/+0
2016-10-16re PR ada/37139 (DEP prevents using Ada tasking)Eric Botcazou1-0/+3
2016-10-05Delete x86 deprecated pcommit instruction supportAndrew Senkevich1-2/+0
2016-10-04x86-tune.def (X86_TUNE_VECTORIZE_DOUBLE): Remove.Uros Bizjak1-2/+0
2016-08-11Use TImode for piecewise move in 64-bit modeH.J. Lu1-2/+12
2016-06-24Call tls_get_addr via GOT for GNU TLS if possibleH.J. Lu1-0/+3
2016-06-07i386.h (enum ix86_enitity): Add X86_DIRFLAG.Uros Bizjak1-15/+19
2016-06-03Implement x86 interrupt attributeH.J. Lu1-3/+35
2016-05-24i386.h (TARGET_AVOID_4BYTE_PREFIXES): Define.Jakub Jelinek1-0/+2
2016-05-23i386.h (IS_STACK_MODE): Enable for TARGET_MIX_SSE_I387.Uros Bizjak1-4/+4
2016-05-12constraints.md (Yv): New constraint.Jakub Jelinek1-1/+2
2016-03-29re PR target/63890 (Compiling trivial program with -O -p leads to misaligned ...Mike Stump1-1/+2
2016-03-08ipa-polymorphic-call.c (walk_ssa_copies): Fix spelling - becuase -> because.Jakub Jelinek1-1/+1
2016-03-07re PR target/70064 (Wrong code with custom flags and quite big testcase @ i686)Uros Bizjak1-0/+5
2016-01-13i386.h (TARGET_FLT_EVAL_METHOD): Return -1 for TARGET_SSE_MATH without TARGET...Uros Bizjak1-2/+5
2016-01-11Set FLT_EVAL_METHOD to 2 only if 387 FPU is usedH.J. Lu1-1/+1
2016-01-11re PR rtl-optimization/68920 (Undesirable if-conversion for a rarely taken br...Yuri Rumyantsev1-0/+2
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
2015-12-24Introduce support for PKU instructions.Kirill Yukhin1-0/+3
2015-11-26re PR target/68416 ([MPX] GCC emits a lot of redundant bndmov instructions)Ilya Enkovich1-1/+1
2015-11-17re PR target/68263 (Vector "*mov<mode>_internal" fails to handle misaligned l...Uros Bizjak1-1/+1
2015-11-15always define TARGET_PECOFFTrevor Saunders1-3/+0
2015-11-09i386: Add address spaces for fs/gs segments and tlsRichard Henderson1-1/+2
2015-10-20Properly handle -miamcu and -march=lakemontH.J. Lu1-2/+6
2015-10-13i386.c (classify_argument): Use CEIL where applicable.Uros Bizjak1-18/+20
2015-10-07re PR target/66697 (Feature request: -mstackrealign and force_align_arg_point...Uros Bizjak1-1/+1
2015-10-07Define x86 CALL_USED_REGISTERS_MASKH.J. Lu1-0/+3
2015-10-06AMD znver1 enablement.Venkataramanan Kumar1-0/+4
2015-10-02system.h (ROUND_UP): New macro definition.Uros Bizjak1-2/+1
2015-09-25Rename IA MCU processor lakemount to lakemontH.J. Lu1-1/+1
2015-09-24Change IA MCU processor from iamcu to lakemountH.J. Lu1-1/+1
2015-09-22AVX-512. Introduce SKylake server CPU.Kirill Yukhin1-0/+2
2015-07-25re PR target/67004 (valgrind error in recog_memoized & shorten_branches)Uros Bizjak1-5/+6
2015-07-24re PR target/64003 (valgrind complains about get_attr_length_nobnd in insn-at...Uros Bizjak1-0/+8
2015-07-17re PR target/66824 (-miamcu doesn't load FP constant into register directly)Uros Bizjak1-0/+4
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