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2023-04-20Re-arrange sections of i386 cpuidMo, Zewei1-29/+32
gcc/ChangeLog: * config/i386/cpuid.h: Open a new section for Extended Features Leaf (%eax == 7, %ecx == 0) and Extended Features Sub-leaf (%eax == 7, %ecx == 1).
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang1-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_COMPLEX. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-complex. * config.gcc: Add amxcomplexintrin.h. * config/i386/cpuid.h (bit_AMX_COMPLEX): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_COMPLEX__. * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-complex. * config/i386/i386.opt: Add option -mamx-complex. * config/i386/immintrin.h: Include amxcomplexintrin.h. * doc/extend.texi: Document amx-complex. * doc/invoke.texi: Document -mamx-complex. * doc/sourcebuild.texi: Document target amx-complex. * config/i386/amxcomplexintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-complex. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX. * gcc.target/i386/amx-helper.h: Add amx-complex support. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-complex. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-complex. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_complex): New. * gcc.target/i386/amxcomplex-asmatt-1.c: New test. * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto. * gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto.
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-11-07Support Intel RAO-INTkonglin11-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect raoint. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET, OPTION_MASK_ISA2_RAOINT_UNSET): New. (ix86_handle_option): Handle -mraoint. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_RAOINT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for raoint. * config.gcc: Add raointintrin.h * config/i386/cpuid.h (bit_RAOINT): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __RAOINT__. * config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Add -mraoint. * config/i386/sync.md (rao_a<raointop><mode>): New define insn. * config/i386/i386.opt: Add option -mraoint. * config/i386/x86gprintrin.h: Include raointintrin.h. * doc/extend.texi: Document raoint. * doc/invoke.texi: Document -mraoint. * doc/sourcebuild.texi: Document target raoint. * config/i386/raointintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mraoint. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mraoint. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add raoint target. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: Add check_effective_target_raoint. * gcc.target/i386/rao-helper.h: New test. * gcc.target/i386/raoint-1.c: Ditto. * gcc.target/i386/raoint-aadd-2.c: Ditto. * gcc.target/i386/raoint-aand-2.c: Ditto. * gcc.target/i386/raoint-aor-2.c: Ditto. * gcc.target/i386/raoint-axor-2.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2022-11-07Support Intel prefetchit0/t1Haochen Jiang1-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect PREFETCHI. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_PREFETCHI_SET, OPTION_MASK_ISA2_PREFETCHI_UNSET): New. (ix86_handle_option): Handle -mprefetchi. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_PREFETCHI. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for prefetchi. * config.gcc: Add prfchiintrin.h. * config/i386/cpuid.h (bit_PREFETCHI): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (VOID, PCVOID, INT) and DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __PREFETCHI__. * config/i386/i386-expand.cc: Handle new builtins. * config/i386/i386-isa.def (PREFETCHI): Add DEF_PTA(PREFETCHI). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle prefetchi. * config/i386/i386.md (prefetchi): New define_insn. * config/i386/i386.opt: Add option -mprefetchi. * config/i386/predicates.md (local_func_symbolic_operand): New predicates. * config/i386/x86gprintrin.h: Include prfchiintrin.h. * config/i386/xmmintrin.h (enum _mm_hint): New enum for prefetchi. (_mm_prefetch): Handle the highest bit of enum. * doc/extend.texi: Document prefetchi. * doc/invoke.texi: Document -mprefetchi. * doc/sourcebuild.texi: Document target prefetchi. * config/i386/prfchiintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mprefetchi. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-13.c: Add -mprefetchi. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto. * gcc.target/i386/prefetchi-1.c: New test. * gcc.target/i386/prefetchi-2.c: Ditto. * gcc.target/i386/prefetchi-3.c: Ditto. * gcc.target/i386/prefetchi-4.c: Ditto. Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
2022-11-04Support Intel AMX-FP16 ISAHongyu Wang1-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect amx-fp16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET, OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros. (ix86_handle_option): Handle -mamx-fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_FP16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-fp16. * config.gcc: Add amxfp16intrin.h. * config/i386/cpuid.h (bit_AMX_FP16): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_FP16__. * config/i386/i386-isa.def: Add DEF_PTA for AMX_FP16. * config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16. (ix86_valid_target_attribute_inner_p): Add new ATTR. (ix86_option_override_internal): Handle AMX-FP16. * config/i386/i386.opt: Add -mamx-fp16. * config/i386/immintrin.h: Include amxfp16intrin.h. * doc/extend.texi: Document -mamx-fp16. * doc/invoke.texi: Document amx-fp16. * doc/sourcebuild.texi: Document amx_fp16. * config/i386/amxfp16intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-fp16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_amx_fp16): New proc. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: Add AMX_FP16. * gcc.target/i386/amx-helper.h: New file to support amx-fp16. * gcc.target/i386/amxfp16-asmatt-1.c: New test. * gcc.target/i386/amxfp16-asmintel-1.c: Ditto. * gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-04Support Intel CMPccXADDHaochen Jiang1-0/+1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_CMPCCXADD_SET, OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. (ix86_handle_option): Handle -mcmpccxadd. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_CMPCCXADD. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for cmpccxadd. * config.gcc: Add cmpccxaddintrin.h. * config/i386/cpuid.h (bit_CMPCCXADD): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT) and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __CMPCCXADD__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Add new parameter to indicate constant position. Handle INT_FTYPE_PINT_INT_INT_INT and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT. * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD). * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd. (ix86_valid_target_attribute_inner_p): Handle cmpccxadd. * config/i386/i386.opt: Add option -mcmpccxadd. * config/i386/sync.md (cmpccxadd_<mode>): New define insn. * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h. * doc/extend.texi: Document cmpccxadd. * doc/invoke.texi: Document -mcmpccxadd. * doc/sourcebuild.texi: Document target cmpccxadd. * config/i386/cmpccxaddintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mcmpccxadd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-13.c: Add -mcmpccxadd. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Ditto. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Ditto. * gcc.target/i386/x86gprintrin-5.c: Ditto. * lib/target-supports.exp (check_effective_target_cmpccxadd): New. * gcc.target/i386/cmpccxadd-1.c: New test. * gcc.target/i386/cmpccxadd-2.c: Ditto.
2022-10-31Support Intel AVX-NE-CONVERTkonglin11-0/+1
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXNECONVERT_SET, OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New. (ix86_handle_option): Handle -mavxneconvert, unset avxneconvert when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXNECONVERT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxneconvert. * common/config/i386/cpuinfo.h (get_available_features): Detect avxneconvert. * config.gcc: Add avxneconvertintrin.h * config/i386/avxneconvertintrin.h: New. * config/i386/avx512bf16vlintrin.h (_mm256_cvtneps_pbh): Unified builtin with avxneconvert. (_mm_cvtneps_pbh): Ditto. * config/i386/cpuid.h (bit_AVXNECONVERT): New. * config/i386/i386-builtin-types.def: Add DEF_POINTER_TYPE (PCV8HF, V8HF, CONST), DEF_POINTER_TYPE (PCV8BF, V8BF, CONST), DEF_POINTER_TYPE (PCV16HF, V16HF, CONST), DEF_POINTER_TYPE (PCV16BF, V16BF, CONST), DEF_FUNCTION_TYPE (V4SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCBFLOAT16), DEF_FUNCTION_TYPE (V8SF, PCFLOAT16), DEF_FUNCTION_TYPE (V4SF, PCV8BF), DEF_FUNCTION_TYPE (V4SF, PCV8HF), DEF_FUNCTION_TYPE (V8SF, PCV16HF), DEF_FUNCTION_TYPE (V8SF, PCV16BF), * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXNECONVERT__. * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Handle V4SF_FTYPE_PCBFLOAT16,V8SF_FTYPE_PCBFLOAT16, V4SF_FTYPE_PCFLOAT16, V8SF_FTYPE_PCFLOAT16,V4SF_FTYPE_PCV8BF, V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF. * config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New. * config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert. (ix86_valid_target_attribute_inner_p): Handle avxneconvert. * config/i386/i386.md: Add attr avx512bf16vl and avxneconvert. * config/i386/i386.opt: Add option -mavxneconvert. * config/i386/immintrin.h: Inculde avxneconvertintrin.h. * config/i386/sse.md (vbcstnebf162ps_<mode>): New define_insn. (vbcstnesh2ps_<mode>): Ditto. (vcvtnee<bf16_ph>2ps_<mode>):Ditto. (vcvtneo<bf16_ph>2ps_<mode>):Ditto. (vcvtneps2bf16_v4sf): Ditto. (*vcvtneps2bf16_v4sf): Ditto. (vcvtneps2bf16_v8sf): Ditto. * doc/invoke.texi: Document -mavxneconvert. * doc/extend.texi: Document avxneconvert. * doc/sourcebuild.texi: Document target avxneconvert. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-check.h: Add avxneconvert check. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxneconvert. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp:add check_effective_target_avxneconvert. * gcc.target/i386/avx-ne-convert-1.c: New test. * gcc.target/i386/avx-ne-convert-vbcstnebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vbcstnesh2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneebf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneeph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneobf162ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneoph2ps-2.c: Ditto. * gcc.target/i386/avx-ne-convert-vcvtneps2bf16-2.c: Ditto. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Rename.. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: To this. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: New test.
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling1-0/+1
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint8. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT8. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint8. * config.gcc: Add avxvnniint8intrin.h. * config/i386/avxvnniint8intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT8): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT8__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8. (ix86_valid_target_attribute_inner_p): Handle avxvnniint8. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New.. * config/i386/i386.opt: Add option -mavxvnniint8. * config/i386/immintrin.h: Include avxvnniint8intrin.h. * config/i386/sse.md (UNSPEC_VPMADDUBSWACCD UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD, UNSPEC_VPMADDWDACCSSD): Rename according to new style. (vpdp<vpdotprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint8. * doc/invoke.texi: Document -mavxvnniint8. * doc/sourcebuild.texi: Document target avxvnniint8. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint8. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint8 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint8. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint8): New. * gcc.target/i386/avxvnniint8-1.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-21Support Intel AVX-IFMAHongyu Wang1-0/+1
gcc/ * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, OPTION_MASK_ISA2_AVX2_UNSET): New macro. (ix86_handle_option): Handle -mavxifma. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXIFMA. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxifma. * common/config/i386/cpuinfo.h (get_available_features): Detect avxifma. * config.gcc: Add avxifmaintrin.h * config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change to macro. (_mm_madd52hi_epu64): Likewise. (_mm256_madd52lo_epu64): Likewise. (_mm256_madd52hi_epu64): Likewise. * config/i386/avxifmaintrin.h: New header. * config/i386/cpuid.h (bit_AVXIFMA): New. * config/i386/i386-builtin.def: Add new builtins, and correct pattern names for AVX512IFMA. * config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA builtins like AVX-VNNI. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXIFMA__. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Relax ISA masks for AVXIFMA. * config/i386/i386-isa.def: Add AVXIFMA. * config/i386/i386-options.cc (isa2_opts): Add -mavxifma. (ix86_valid_target_attribute_inner_p): Handle avxifma. * config/i386/i386.md (isa): Add attr avxifma and avxifmavl. * config/i386/i386.opt: Add option -mavxifma. * config/i386/immintrin.h: Inculde avxifmaintrin.h. * config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>): Remove. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove. (vpamdd52huq<mode>_maskz): Rename to ... (vpmadd52huq<mode>_maskz): ... this. (vpamdd52luq<mode>_maskz): Rename to ... (vpmadd52luq<mode>_maskz): ... this. (vpmadd52<vpmadd52type><mode>): New define_insn. (vpmadd52<vpmadd52type>v8di): Likewise. (vpmadd52<vpmadd52type><mode>_maskz_1): Likewise. (vpamdd52<vpmadd52type><mode>_mask): Rename to ... (vpmadd52<vpmadd52type><mode>_mask): ... this. * doc/invoke.texi: Document -mavxifma. * doc/extend.texi: Document avxifma. * doc/sourcebuild.texi: Document target avxifma. gcc/testsuite/ * gcc.target/i386/avx-check.h: Add avxifma check. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane.. * gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test. * gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto. * gcc.target/i386/avx-ifma-1.c: Ditto. * gcc.target/i386/avx-ifma-2.c: Ditto. * gcc.target/i386/avx-ifma-3.c: Ditto. * gcc.target/i386/avx-ifma-4.c: Ditto. * gcc.target/i386/avx-ifma-5.c: Ditto. * gcc.target/i386/avx-ifma-6.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/sse-12.c: Add -mavxifma. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxifma): New.
2022-05-23[x86_64]: Zhaoxin lujiazui enablementMayshao1-0/+4
This patch fix Zhaoxin CPU vendor ID detection problem and add zhaoxin "lujiazui" processor support. Currently gcc can't recognize Zhaoxin CPU (vendor ID "CentaurHauls" and "Shanghai") if user use -march=native option, which is confusing for users. This patch enables -march=native in zhaoxin family 7th processor and -march/-mtune=lujiazui, costs and tunning are set according to the characteristics of the processor. We add a new md file to describe lujiazui pipeline. Testing: Bootstrap is ok, and no regressions for i386/x86-64 testsuite. Background: Related Zhaoxin linux kernel patch can be found at: https://lore.kernel.org/lkml/01042674b2f741b2aed1f797359bdffb@zhaoxin.com/ Related Zhaoxin glibc patch can be found at: https://sourceware.org/git/?p=glibc.git;a=commit;h=32ac0b988466785d6e3cc1dffc364bb26fc63193 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Detect the specific type of Zhaoxin CPU, and return Zhaoxin CPU name. (cpu_indicator_init): Handle Zhaoxin processors. * common/config/i386/i386-common.cc: Add lujiazui. * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add VENDOR_ZHAOXIN. (enum processor_types): Add ZHAOXIN_FAM7H. (enum processor_subtypes): Add ZHAOXIN_FAM7H_LUJIAZUI. * config.gcc: Add lujiazui. * config/i386/cpuid.h (signature_SHANGHAI_ebx): Add Signatures for zhaoxin (signature_SHANGHAI_ecx): Ditto. (signature_SHANGHAI_edx): Ditto. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize lujiazui processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add lujiazui. * config/i386/i386-options.cc (m_LUJIAZUI): New_definition. * config/i386/i386.h (enum processor_type): Ditto. * config/i386/i386.md: Add lujiazui. * config/i386/x86-tune-costs.h (struct processor_costs): Add lujiazui costs. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add lujiazui. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Add lujiazui Tunnings. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_MOVX): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_LCP_STALL): Ditto. (X86_TUNE_USE_INCDEC): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_OPT_AGU): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_EXPAND_ABS): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_USE_FFREEP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. * doc/extend.texi: Add details about lujiazui. * doc/invoke.texi: Add details about lujiazui. * config/i386/lujiazui.md: Introduce lujiazui cpu and include new md file. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Test -arch=lujiauzi and -tune=lujiazui. * g++.target/i386/mv32.C: Ditto. Signed-off-by: mayshao <mayshao-oc@zhaoxin.com>
2022-02-17Clean up MPX-related bit_{MPX,BNDREGS,BNDCSR}.liuhongt1-5/+0
gcc/ChangeLog: * config/i386/cpuid.h (bit_MPX): Removed. (bit_BNDREGS): Ditto. (bit_BNDCSR): Ditto.
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-09-08AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 ↵Guo, Xuepeng1-0/+1
instructions. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect FEATURE_AVX512FP16. * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512FP16_SET, OPTION_MASK_ISA_AVX512FP16_UNSET, OPTION_MASK_ISA2_AVX512FP16_SET, OPTION_MASK_ISA2_AVX512FP16_UNSET): New. (OPTION_MASK_ISA2_AVX512BW_UNSET, OPTION_MASK_ISA2_AVX512BF16_UNSET): Add AVX512FP16. (ix86_handle_option): Handle -mavx512fp16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX512FP16. * common/config/i386/i386-isas.h: Add entry for AVX512FP16. * config.gcc: Add avx512fp16intrin.h. * config/i386/avx512fp16intrin.h: New intrinsic header. * config/i386/cpuid.h: Add bit_AVX512FP16. * config/i386/i386-builtin-types.def: (FLOAT16): New primitive type. * config/i386/i386-builtins.c: Support _Float16 type for i386 backend. (ix86_register_float16_builtin_type): New function. (ix86_float16_type_node): New. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512FP16__. * config/i386/i386-expand.c (ix86_expand_branch): Support HFmode. (ix86_prepare_fp_compare_args): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_expand_fp_movcc): Ditto. * config/i386/i386-isa.def: Add PTA define for AVX512FP16. * config/i386/i386-options.c (isa2_opts): Add -mavx512fp16. (ix86_valid_target_attribute_inner_p): Add avx512fp16 attribute. * config/i386/i386.c (ix86_get_ssemov): Use vmovdqu16/vmovw/vmovsh for HFmode/HImode scalar or vector. (ix86_get_excess_precision): Use FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 when TARGET_AVX512FP16 existed. (sse_store_index): Use SFmode cost for HFmode cost. (inline_memory_move_cost): Add HFmode, and perfer SSE cost over GPR cost for HFmode. (ix86_hard_regno_mode_ok): Allow HImode in sse register. (ix86_mangle_type): Add manlging for _Float16 type. (inline_secondary_memory_needed): No memory is needed for 16bit movement between gpr and sse reg under TARGET_AVX512FP16. (ix86_multiplication_cost): Adjust TARGET_SSE_MATH && SSE_FLOAT_MODE_P to SSE_FLOAT_MODE_SSEMATH_OR_HF_P. (ix86_division_cost): Ditto. (ix86_rtx_costs): Ditto. (ix86_add_stmt_cost): Ditto. (ix86_optab_supported_p): Ditto. * config/i386/i386.h (VALID_AVX512F_SCALAR_MODE): Add HFmode. (SSE_FLOAT_MODE_SSEMATH_OR_HF_P): Add HFmode. (PTA_SAPPHIRERAPIDS): Add PTA_AVX512FP16. * config/i386/i386.md (mode): Add HFmode. (MODE_SIZE): Add HFmode. (isa): Add avx512fp16. (enabled): Handle avx512fp16. (ssemodesuffix): Add sh suffix for HFmode. (comm): Add mult, div. (plusminusmultdiv): New code iterator. (insn): Add mult, div. (*movhf_internal): Adjust for avx512fp16 instruction. (*movhi_internal): Ditto. (*cmpi<unord>hf): New define_insn for HFmode. (*ieee_s<ieee_maxmin>hf3): Likewise. (extendhf<mode>2): Likewise. (trunc<mode>hf2): Likewise. (float<floatunssuffix><mode>hf2): Likewise. (*<insn>hf): Likewise. (cbranchhf4): New expander. (movhfcc): Likewise. (<insn>hf3): Likewise. (mulhf3): Likewise. (divhf3): Likewise. * config/i386/i386.opt: Add mavx512fp16. * config/i386/immintrin.h: Include avx512fp16intrin.h. * doc/invoke.texi: Add mavx512fp16. * doc/extend.texi: Add avx512fp16 Usage Notes. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add -mavx512fp16 in dg-options. * gcc.target/i386/avx-2.c: Ditto. * gcc.target/i386/avx512-check.h: Check cpuid for AVX512FP16. * gcc.target/i386/funcspec-56.inc: Add new target attribute check. * gcc.target/i386/sse-13.c: Add -mavx512fp16. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp: (check_effective_target_avx512fp16): New. * g++.target/i386/float16-1.C: New test. * g++.target/i386/float16-2.C: Ditto. * g++.target/i386/float16-3.C: Ditto. * gcc.target/i386/avx512fp16-12a.c: Ditto. * gcc.target/i386/avx512fp16-12b.c: Ditto. * gcc.target/i386/float16-3a.c: Ditto. * gcc.target/i386/float16-3b.c: Ditto. * gcc.target/i386/float16-4a.c: Ditto. * gcc.target/i386/float16-4b.c: Ditto. * gcc.target/i386/pr54855-12.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com> Co-Authored-By: Liu Hongtao <hongtao.liu@intel.com> Co-Authored-By: Wang Hongyu <hongyu.wang@intel.com> Co-Authored-By: Xu Dianhong <dianhong.xu@intel.com>
2021-03-23x86: Add __volatile__ to __cpuid and __cpuid_countH.J. Lu1-18/+18
Since CPUID instruction may return different values on hybrid core. volatile is needed on asm statements in <cpuid.h>. PR target/99704 * config/i386/cpuid.h (__cpuid): Add __volatile__. (__cpuid_count): Likewise.
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-11-11Support Intel AVX VNNIliuhongt1-0/+1
2020-10-13 Hongtao Liu <hongtao.liu@intel.com> Hongyu Wang <hongyu.wang@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect AVXVNNI. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AVXVNNI_SET, OPTION_MASK_ISA2_AVXVNNI_UNSET): New. (OPTION_MASK_ISA2_AVX2_UNSET): Add AVXVNNI. (ix86_hanlde_option): Handle -mavxvnni, unset avxvnni when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNI. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avxvnni. * config.gcc: Add avxvnniintrin.h. * config/i386/avx512vnnivlintrin.h: Reimplement 128/256 bit non-mask intrinsics with macros to support unified interface. * config/i386/avxvnniintrin.h: New header file. * config/i386/cpuid.h (bit_AVXVNNI): New. * config/i386/i386-builtins.c (def_builtin): Handle AVXVNNI mask for unified builtin. * config/i386/i386-builtin.def (BDESC): Adjust AVX512VNNI builtins for AVXVNNI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVXVNNI__. * config/i386/i386-expand.c (ix86_expand_builtin): Handle bisa for AVXVNNI to support unified intrinsic name, since there is no dependency between AVX512VNNI and AVXVNNI. * config/i386/i386-options.c (isa2_opts): Add -mavxvnni. (ix86_valid_target_attribute_inner_p): Handle avxnnni. (ix86_option_override_internal): Ditto. * config/i386/i386.h (TARGET_AVXVNNI, TARGET_AVXVNNI_P, TARGET_AVXVNNI_P, PTA_AVXVNNI): New. (PTA_SAPPHIRERAPIDS): Add AVX_VNNI. (PTA_ALDERLAKE): Likewise. * config/i386/i386.md ("isa"): Add avxvnni, avx512vnnivl. ("enabled"): Adjust for avxvnni and avx512vnnivl. * config/i386/i386.opt: Add option -mavxvnni. * config/i386/immintrin.h: Include avxvnniintrin.h. * config/i386/sse.md (vpdpbusd_<mode>): Adjust for AVXVNNI. (vpdpbusds_<mode>): Likewise. (vpdpwssd_<mode>): Likewise. (vpdpwssds_<mode>): Likewise. (vpdpbusd_v16si): New. (vpdpbusds_v16si): Likewise. (vpdpwssd_v16si): Likewise. (vpdpwssds_v16si): Likewise. * doc/invoke.texi: Document -mavxvnni. * doc/extend.texi: Document avxvnni. * doc/sourcebuild.texi: Document target avxvnni. gcc/testsuite/ * gcc.target/i386/avx512vl-vnni-1.c: Rename.. * gcc.target/i386/avx512vl-vnni-1a.c: To This. * gcc.target/i386/avx512vl-vnni-1b.c: New test. * gcc.target/i386/avx512vl-vnni-2.c: Ditto. * gcc.target/i386/avx512vl-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-1.c: Ditto. * gcc.target/i386/avx-vnni-2.c: Ditto. * gcc.target/i386/avx-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-4.c: Ditto. * gcc.target/i386/avx-vnni-5.c: Ditto. * gcc.target/i386/avx-vnni-6.c: Ditto. * gcc.target/i386/avx-vpdpbusd-2.c: Ditto. * gcc.target/i386/avx-vpdpbusds-2.c: Ditto. * gcc.target/i386/avx-vpdpwssd-2.c: Ditto. * gcc.target/i386/avx-vpdpwssds-2.c: Ditto. * gcc.target/i386/vnni_inline_error.c: Ditto. * gcc.target/i386/avx512vnnivl-builtin.c: Ditto. * gcc.target/i386/avxvnni-builtin.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxvnni. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp (check_effective_target_avxvnni): New proc.
2020-10-29Enable GCC to support Intel Key Locker ISAliuhongt1-0/+7
gcc/ChangeLog 2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com> Hongyu Wang <hongyu.wang@intel.com> Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/cpuinfo.h (get_available_features): Detect KL, AESKLE and WIDEKL features. * common/config/i386/i386-common.c (OPTION_MASK_ISA_KL_SET): New. (OPTION_MASK_ISA_WIDEKL_SET): Likewise. (OPTION_MASK_ISA_KL_UNSET): Likewise. (OPTION_MASK_ISA_WIDEKL_UNSET): Likewise. (OPTION_MASK_ISA2_AVX2_UNSET): Likewise. (OPTION_MASK_ISA2_AVX_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_UNSET): Likewise. (OPTION_MASK_ISA2_SSSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE_UNSET): Likewise. (ix86_handle_option): Handle kl and widekl, add dependency chain for KL and SSE2. * common/config/i386/i386-cpuinfo.h (enum processor_features): (FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for KL, AESKLE and WIDEKL. * config.gcc: Add keylockerintrin.h. * doc/invoke.texi: Document new option -mkl and -mwidekl. * doc/extend.texi: Document kl and widekl. * config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New. * config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID), (UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT), (UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New function types. * config/i386/i386-builtin.def: Add __builtin_ia32_loadiwkey, __builtin_ia32_aesdec128kl_u8, __builtin_ia32_aesdec256kl_u8, __builtin_ia32_aesenc128kl_u8, __builtin_ia32_aesenc256kl_u8, __builtin_ia32_aesdecwide128kl_u8, __builtin_ia32_aesdecwide256kl_u8, __builtin_ia32_aesencwide128kl_u8, __builtin_ia32_aesencwide256kl_u8, __builtin_ia32_encodekey128_u32, __builtin_ia32_encodekey256_u32. * config/i386/i386-c.c (ix86_target_macros_internal): Handle kl and widekl. * config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl. (ix86_option_override_internal): Handle KL and WIDEKL. (ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl. * config/i386/i386-expand.c (ix86_expand_builtin): Expand Keylocker Builtins. * config/i386/i386.h (TARGET_KL): New. (TARGET_KL_P): Likewise. (TARGET_WIDEKL): Likewise. (TARGET_WIDEKL_P): Likewise. (PTA_KL): Likewise. (PTA_WIDEKL): Likewise. (PTA_TIGERLAKE): Add PTA_KL, PTA_WIDEKL. (PTA_ALDERLAKE): Likewise. * config/i386/i386.opt: Add new option mkl and mwidekl. * config/i386/keylockerintrin.h: New header file for Keylocker. * config/i386/immintrin.h: Include keylockerintrin.h. * config/i386/predicates.md (encodekey128_operation): New predicate. (encodekey256_operation): Likewise. (aeswidekl_operation): Likewise. * config/i386/sse.md (UNSPECV_LOADIWKEY): New. (UNSPECV_AESDEC128KLU8): Likewise. (UNSPECV_AESENC128KLU8): Likewise. (UNSPECV_AESDEC256KLU8): Likewise. (UNSPECV_AESENC256KLU8): Likewise. (UNSPECV_AESDECWIDE128KLU8): Likewise. (UNSPECV_AESENCWIDE128KLU8): Likewise. (UNSPECV_AESDECWIDE256KLU8): Likewise. (UNSPECV_AESENCWIDE256KLU8): Likewise. (UNSPECV_ENCODEKEY128U32): Likewise. (UNSPECV_ENCODEKEY256U32): Likewise. (encodekey128u32): New expander. (encodekey256u32): Likewise. (aes<aeswideklvariant>u8): Likewise. (loadiwkey): New insn pattern. (*encodekey128u32): Likewise. (*encodekey256u32): Likewise. (aes<aesklvariant>u8): Likewise. (*aes<aeswideklvariant>u8): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/keylocker-aesdec128kl.c: New test. * gcc.target/i386/keylocker-aesdec256kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise. * gcc.target/i386/keylocker-aesenc128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide256kl.c: Likewise. * gcc.target/i386/keylocker-encodekey128.c: Likewise. * gcc.target/i386/keylocker-encodekey256.c: Likewise. * gcc.target/i386/keylocker-loadiwkey.c: Likewise. * g++.dg/other/i386-2.C: Add -mkl and -mwidekl. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Add kl and widekl. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/funcspec-56.inc: Add new target attribute test.
2020-10-15Enable Intel HRESET InstructionHongyu Wang1-0/+1
gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -mhreset. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add mhreset. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-10-15Enable gcc support for UINTRliuhongt1-0/+1
2020-05-20 Hongtao Liu <hongtao.liu@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect UINTR. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR_UNSET): New. (ix86_handle_option): Handle -muintr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_UINTR. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for uintr. * config.gcc: Add uintrintrin.h to extra_headers. * config/i386/uintrintrin.h: New. * config/i386/cpuid.h (bit_UINTR): New. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Add __builtin_ia32_testui. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_TESTUI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __UINTR__. * config/i386/i386-expand.c (ix86_expand_special_args_builtin): Handle UINT8_FTYPE_VOID. (ix86_expand_builtin): Handle IX86_BUILTIN_TESTUI. * config/i386/i386-options.c (isa2_opts): Add -muintr. (ix86_valid_target_attribute_inner_p): Handle UINTR. (ix86_option_override_internal): Add TARGET_64BIT check for UINTR. * config/i386/i386.h (TARGET_UINTR, TARGET_UINTR_P, PTA_UINTR): New. (PTA_SAPPHIRRAPIDS): Add PTA_UINTR. * config/i386/i386.opt: Add -muintr. * config/i386/i386.md (define_int_iterator UINTR_UNSPECV): New. (define_int_attr uintr_unspecv): New. (uintr_<uintr_unspecv>, uintr_senduipi, testui): New define_insn patterns. * config/i386/x86gprintrin.h: Include uintrintrin.h * doc/invoke.texi: Document -muintr. * doc/extend.texi: Document uintr. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/uintr-1.c: New test. * gcc.target/i386/uintr-2.c: Ditto. * gcc.target/i386/uintr-3.c: Ditto. * gcc.target/i386/uintr-4.c: Ditto. * gcc.target/i386/uintr-5.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Add -muintr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add muintr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt1-0/+3
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto.
2020-07-19x86: Add __cpuidex and include guard to <cpuid.h>H.J. Lu1-0/+12
Add void __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf); as well as include guard to <cpuid.h>. gcc/ PR target/95973 PR target/96238 * config/i386/cpuid.h: Add include guard. (__cpuidex): New. gcc/testsuite/ PR target/95973 PR target/96238 * gcc.target/i386/pr95973.c: New test.
2020-05-21config/i386/cpuid.h: Use hexadecimal in commentsH.J. Lu1-3/+3
Since Intel SDM uses hexadecimal, use hexadecimal in comments. PR target/95260 * config/i386/cpuid.h: Use hexadecimal in comments.
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt1-0/+2
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET, OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros. * config.gcc: Add tsxldtrkintrin.h to extra_headers. * config/i386/driver-i386.c (host_detect_local_cpu): Detect TSXLDTRK. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __TSXLDTRK__. * config/i386/i386-options.c (ix86_target_string): Add -mtsxldtrk. (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk. * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P): New. * config/i386/i386.md (define_c_enum "unspec"): Add UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK. (TSXLDTRK): New define_int_iterator. ("<tsxldtrk>"): New define_insn. * config/i386/i386.opt: Add -mtsxldtrk. * config/i386/immintrin.h: Include tsxldtrkintrin.h. * config/i386/tsxldtrkintrin.h: New. * doc/invoke.texi: Document -mtsxldtrk. gcc/testsuite/ * g++.dg/other/i386-2.c: Add -mtsxldtrk. * g++.dg/other/i386-3.c: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewsie. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/tsxldtrk-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add target attribute tests for tsxldtrk.
2020-05-06Enable GCC support for SERIALIZEliuhongt1-0/+1
2020-03-04 Hongtao Liu <hongtao.liu@intel.com> 2020-03-04 Wei Xiao <wei3.xiao@intel.com> gcc/Changelog: * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET, OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros. (ix86_handle_option): Handle -mserialize. * gcc/config.gcc (serializeintrin.h): New header file. * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit. * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect -mserialize. * gcc/config/i386/i386-builtin.def: Add new builtin. * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro. * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts): Add -mserialize. * (ix86_valid_target_attribute_inner_p): Add target attribute * for serialize. * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P): New macros. * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec. (serialize): New define_insn. * gcc/config/i386/i386.opt (mserialize): New option * gcc/config/i386/immintrin.h: Include serailizeintrin.h. * gcc/config/i386/serializeintrin.h: New header file. * gcc/doc/invoke.texi: Add documents for -mserialize. gcc/testsuite/Changelog * gcc/testsuite/gcc.target/i386/serialize-1.c: New test. * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize. * gcc/testsuite/g++.dg/other/i386-3.C: Ditto. * gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto. * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r279813
2019-06-26Enable GCC support for AVX512_VP2INTERSECT which will be in tigerlaker.Hongtao Liu1-0/+1
There are two instructions for AVX512_VP2INTERSECT: VP2INTERSECTD and VP2INTERSECTQ. gcc/ 2019-06-05 Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VP2INTERSECT_SET, OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET): New macros. (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET. (ix86_handle_option): Handle -mavx512vp2intersect. * config/i386/avx512vp2intersectintrin.h: New. * config/i386/avx512vp2intersectvlintrin.h: New. * config/i386/cpuid.h (bit_AVX512VP2INTERSECT): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX512VP2INTERSECT. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-builtins.c: (enum processor_features): Add F_AVX512VP2INTERSECT. (static const _isa_names_table isa_names_table): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512VP2INTERSECT__. * config/i386/i386-expand.c (ix86_expand_builtin): Expand IX86_BUILTIN_2INTERSECTD512, IX86_BUILTIN_2INTERSECTQ512, IX86_BUILTIN_2INTERSECTD256, IX86_BUILTIN_2INTERSECTQ256, IX86_BUILTIN_2INTERSECTD128, IX86_BUILTIN_2INTERSECTQ128. * config/i386/i386-modes.def (P2QI, P2HI): New modes. * config/i386/i386-options.c (ix86_target_string): Add -mavx512vp2intersect. (ix86_option_override_internal): Handle AVX512VP2INTERSECT. * config/i386/i386.c (ix86_hard_regno_nregs): Allocate two regs for P2HImode and P2QImode. (ix86_hard_regno_mode_ok): Register pair only starts at even hardreg number for P2QImode and P2HImode. (ix86_regmode_natural_size): New function. * config/i386/i386.h (TARGET_AVX512VP2INTERSECT, TARGET_AVX512VP2INTERSECT_P, PTA_AVX512VP2INTERSECT REGMODE_NATURAL_SIZE, MASK_PAIR_REGNO_P): New. * config/i386/i386-protos.h (ix86_regmode_natural_size): Declare * config/i386/i386.opt: Add -mavx512vp2intersect. * config/i386/immintrin.h: Include avx512vp2intersectintrin.h and avx512vp2intersectvlintrin.h. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_VP2INTERSECT. (define_mode_iterator VI48_AVX512VP2VL): New. (avx512vp2intersect_2intersect<mode>, avx512vp2intersect_2intersectv16si): New define_insn patterns. * config.gcc: Add avx512vp2intersectvlintrin.h and avx512vp2intersectintrin.h to extra_headers. * doc/invoke.texi: Document -mavx512vp2intersect. gcc/testsuite 2019-06-06 Hongtao Liu <hongtao.liu@intel.com> Olga Makhotina <olga.makhotina@intel.com> * gcc.target/i386/avx512-check.h: Handle bit_AVX512VP2INTERSECT. * gcc.target/i386/avx512vp2intersect-2intersect-1a.c: New test. * gcc.target/i386/avx512vp2intersect-2intersect-1b.c: Likewise. * gcc.target/i386/avx512vp2intersect-2intersectvl-1a.c: Likewise. * gcc.target/i386/avx512vp2intersect-2intersectvl-1b.c: Likewise. * gcc.target/i386/sse-12.c: Add -mavx512vp2intersect. * gcc.target/i386/sse-13.c: Likewsie. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. * g++.dg/other/i386-2.C: Likewise. * g++.dg/other/i386-3.C: Likewise. Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com> Co-Authored-By: Olga Makhotina <olga.makhotina@intel.com> From-SVN: r272668
2019-05-28Add GCC support to ENQCMD.Xuepeng Guo1-0/+1
gcc/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_ENQCMD_SET, OPTION_MASK_ISA_ENQCMD_UNSET): New macros. (ix86_handle_option): Handle -menqcmd. * config.gcc (enqcmdintrin.h): New header file. * config/i386/cpuid.h (bit_ENQCMD): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -menqcmd. * config/i386/i386-builtin-types.def ((INT, PVOID, PCVOID)): New function type. * config/i386/i386-builtin.def (__builtin_ia32_enqcmd, __builtin_ia32_enqcmds): New builtins. * config/i386/i386-c.c (__ENQCMD__): New macro. * config/i386/i386-option.c (ix86_target_string): Add -menqcmd. (ix86_valid_target_attribute_inner_p): Likewise. * config/i386/i386-expand.c (ix86_expand_builtin): Expand IX86_BUILTIN_ENQCMD and IX86_BUILTIN_ENQCMDS. * config/i386/i386.h (TARGET_ENQCMD): New. * config/i386/i386.md (UNSPECV_ENQCMD, UNSPECV_ENQCMDS): New. (@enqcmd<enqcmd_sfx>_<mode>): New insn pattern. (movdir64b_<mode>): Parameterize to enable share expansion code with ENQCMD in function ix86_expand_builtin. * config/i386/i386.opt: Add -menqcmd. * config/i386/immintrin.h: Include enqcmdintrin.h. * config/i386/enqcmdintrin.h: New intrinsic file. * doc/invoke.texi: Add -menqcmd. gcc/testsuite/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * gcc.target/i386/enqcmd.c: New test. * gcc.target/i386/enqcmds.c: Likewise. * g++.dg/other/i386-2.C: Add -menqcmd. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. From-SVN: r271678
2019-05-21cpuid.h (__cpuid): For 32bit targets...Uros Bizjak1-0/+17
* config/i386/cpuid.h (__cpuid): For 32bit targets, zero %ebx and %ecx bafore calling cpuid with leaf 1 or non-constant leaf argument. From-SVN: r271469
2019-05-08Enable support for bfloat16 which will be in Future Cooper Lake.Hongtao Liu1-0/+3
There are 3 instructions for AVX512BF16: VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting: - VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data. - VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data. - VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision. 2019-05-07 Wei Xiao <wei3.xiao@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BF16_SET OPTION_MASK_ISA_AVX512BF16_UNSET, OPTION_MASK_ISA2_AVX512BW_UNSET): New. (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA_AVX512BF16_UNSET. (ix86_handle_option): Handle -mavx512bf16. * config.gcc: Add avx512bf16vlintrin.h and avx512bf16intrin.h to extra_headers. * config/i386/avx512bf16vlintrin.h: New. * config/i386/avx512bf16intrin.h: New. * config/i386/cpuid.h (bit_AVX512BF16): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect BF16. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVX512BF16__. * config/i386/i386-option.c (ix86_target_string): Add -mavx512bf16. (ix86_option_override_internal): Handle BF16. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386-expand.c (ix86_expand_args_builtin): Ditto. * config/i386/i386-builtin.c (enum processor_features): Add F_AVX512BF16. (static const _isa_names_table isa_names_table): Ditto. * config/i386/i386.h (TARGET_AVX512BF16, TARGET_AVX512BF16_P): New. (PTA_AVX512BF16): Ditto. * config/i386/i386.opt: Add -mavx512bf16. * config/i386/immintrin.h: Include avx512bf16intrin.h and avx512bf16vlintrin.h. * config/i386/sse.md (avx512f_cvtne2ps2bf16_<mode><mask_name>, avx512f_cvtneps2bf16_<mode><mask_name>, avx512f_dpbf16ps_<mode><mask_half_name>): New define_insn patterns. * config/i386/subst.md (mask_half): Add new subst. * doc/invoke.texi: Document -mavx512bf16. 2019-05-07 Wei Xiao <wei3.xiao@intel.com> * gcc.target/i386/avx512bf16-vcvtne2ps2bf16-1.c: New test. * gcc.target/i386/avx512bf16-vcvtneps2bf16-1.c: New test. * gcc.target/i386/avx512bf16-vdpbf16ps-1.c: New test. * gcc.target/i386/avx512bf16vl-vcvtne2ps2bf16-1.c: New test. * gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: New test. * gcc.target/i386/avx512bf16vl-vdpbf16ps-1.c: New test. * gcc.target/i386/builtin_target.c: Handle avx512bf16. * gcc.target/i386/sse-12.c: Add -mavx512bf16. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. 2019-05-07 Hongtao Liu <hongtao.liu@intel.com> * config/i386/cpuinfo.c (get_available_features): Detect BF16. * config/i386/cpuinfo.h (enum processor_features): Add FEATURE_AVX512BF16. From-SVN: r271006
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r267494
2018-11-09Add PTWRITE builtins for x86Andi Kleen1-0/+4
Add builtins/intrinsics for PTWRITE. PTWRITE is a new instruction on Intel Gemini Lake/ Goldmont Plus that allows to write values into the Processor Trace log. This allows very light weight instrumentation of programs. The intrinsics are compatible to icc. Automatically enabled for Goldmont Plus. gcc/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_PTWRITE_SET): New. (OPTION_MASK_ISA_PTWRITE_UNSET): New. (ix86_handle_option): Handle OPT_mptwrite. * config/i386/cpuid.h (bit_PTWRITE): Add. * config/i386/driver-i386.c (host_detect_local_cpu): Detect ptwrite. * config/i386/i386-builtin.def (BDESC): Add ptwrite32/64. * config/i386/i386-c.c (ix86_target_macros_internal): Define __PTWRITE__. * config/i386/i386.c (ix86_target_string): Handle ptwrite. (ix86_option_override_internal): Handle PTA_PTWRITE. (ix86_valid_target_attribute_inner_p): Define ptwrite. (def_builtin2): Force UINT64 to be 64bit only. * config/i386/i386.h (TARGET_PTWRITE): Add. (TARGET_PTWRITE_P): Add. (PTA_PTWRITE): Add. * config/i386/i386.md: Define ptwrite. * config/i386/i386.opt: Add -mptwrite. * config/i386/immintrin.h (_ptwrite64): Add. (_ptwrite32): Add * doc/extend.texi: Document __builtin_ia32_ptwrite*. * doc/invoke.texi: Document -mptwrite. gcc/testsuite/: 2018-11-08 Andi Kleen <ak@linux.intel.com> * gcc.target/i386/ptwrite1.c: New test. * gcc.target/i386/ptwrite2.c: New test. From-SVN: r265947
2018-05-14i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, [...]): New defines.Sebastian Peryt1-0/+1
2018-05-14 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, OPTION_MASK_ISA_CLDEMOTE_UNSET): New defines. (ix86_handle_option): Handle -mcldemote. * config.gcc: New header. * config/i386/cldemoteintrin.h: New file. * config/i386/cpuid.h (bit_CLDEMOTE): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mcldemote. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_CLDEMOTE. * config/i386/i386.c (ix86_target_string): Add -mcldemote. (ix86_valid_target_attribute_inner_p): Ditto. (enum ix86_builtins): Add IX86_BUILTIN_CLDEMOTE. (ix86_init_mmx_sse_builtins): Define __builtin_ia32_cldemote. (ix86_expand_builtin): Expand IX86_BUILTIN_CLDEMOTE. * config/i386/i386.h (TARGET_CLDEMOTE, TARGET_CLDEMOTE_P): New. * config/i386/i386.md (UNSPECV_CLDEMOTE): New. (cldemote): New. * config/i386/i386.opt: Add -mcldemote. * config/i386/x86intrin.h: New header. * doc/invoke.texi: Add -mcldemote. gcc/testsuite/ * gcc.target/i386/cldemote-1.c: New test. From-SVN: r260224
2018-05-11i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, [...]): New defines.Sebastian Peryt1-0/+1
2018-05-11 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, OPTION_MASK_ISA_WAITPKG_UNSET): New defines. (ix86_handle_option): Handle -mwaitpkg. * config.gcc: New header. * config/i386/cpuid.h (bit_WAITPKG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mwaitpkg. * config/i386/i386-builtin-types.def ((UINT8, UNSIGNED, UINT64)): New function type. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_WAITPKG. * config/i386/i386.c (ix86_target_string): Add -mwaitpkg. (ix86_option_override_internal): Add PTA_WAITPKG. (ix86_valid_target_attribute_inner_p): Add -mwaitpkg. (enum ix86_builtins): Add IX86_BUILTIN_UMONITOR, IX86_BUILTIN_UMWAIT, IX86_BUILTIN_TPAUSE. (ix86_init_mmx_sse_builtins): Define __builtin_ia32_umonitor, __builtin_ia32_umwait and __builtin_ia32_tpause. (ix86_expand_builtin): Expand IX86_BUILTIN_UMONITOR, IX86_BUILTIN_UMWAIT, IX86_BUILTIN_TPAUSE. * config/i386/i386.h (TARGET_WAITPKG, TARGET_WAITPKG_P): New. * config/i386/i386.md (UNSPECV_UMWAIT, UNSPECV_UMONITOR, UNSPECV_TPAUSE): New. (umwait, umwait_rex64, umonitor_<mode>, tpause, tpause_rex64): New. * config/i386/i386.opt: Add -mwaitpkg. * config/i386/waitpkgintrin.h: New file. * config/i386/x86intrin.h: New header. * doc/invoke.texi: Add -mwaitpkg. gcc/testsuite/ * gcc.target/i386/tpause-1.c: New test. * gcc.target/i386/umonitor-1.c: New test. From-SVN: r260161
2018-04-19i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, [...]): New defines.Sebastian Peryt1-0/+2
2018-04-19 Sebastian Peryt <sebastian.peryt@intel.com> gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_MOVDIRI_SET, OPTION_MASK_ISA_MOVDIR64B_SET, OPTION_MASK_ISA_MOVDIRI_UNSET, OPTION_MASK_ISA_MOVDIR64B_UNSET): New defines. (ix86_handle_option): Handle -mmovdiri and -mmovdir64b. * config.gcc (movdirintrin.h): New header. * config/i386/cpuid.h (bit_MOVDIRI, bit_MOVDIR64B): New bits. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mmovdiri and -mmvodir64b. * config/i386/i386-builtin-types.def ((VOID, PUNSIGNED, UNSIGNED), (VOID, PVOID, PCVOID)): New function types. * config/i386/i386-builtin.def (__builtin_ia32_directstoreu_u32, __builtin_ia32_directstoreu_u64, __builtin_ia32_movdir64b): New builtins. * config/i386/i386-c.c (__MOVDIRI__, __MOVDIR64B__): New. * config/i386/i386.c (ix86_target_string): Added -mmovdir64b and -mmovdiri. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_special_args_builtin): Added VOID_FTYPE_PUNSIGNED_UNSIGNED and VOID_FTYPE_PUNSIGNED_UNSIGNED. (ix86_expand_builtin): Expand IX86_BUILTIN_MOVDIR64B. * config/i386/i386.h (TARGET_MOVDIRI, TARGET_MOVDIRI_P, TARGET_MOVDIR64B, TARGET_MOVDIR64B_P): New. * config/i386/i386.md (UNSPECV_MOVDIRI, UNSPECV_MOVDIR64B): New. (movdiri<mode>, movdir64b_<mode>): New. * config/i386/i386.opt: Add -mmovdiri and -mmovdir64b. * config/i386/immintrin.h: Include movdirintrin.h. * config/i386/movdirintrin.h: New file. * doc/invoke.texi: Added -mmovdiri and -mmovdir64b. gcc/testsuite/ * gcc.target/i386/movdir-1.c: New test. From-SVN: r259495
2018-03-05Enable WBOINVD and PCONFIG instructions.Olga Makhotina1-1/+2
2018-03-05 Olga Makhotina <olga.makhotina@intel.com> Enable WBOINVD and PCONFIG instructions. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig and -mwbnoinvd. * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, __builtin_ia32_wbinvd): New builtins. (SPECIAL_ARGS2): New. * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. (SPECIAL_ARGS2): New. * config/i386/i386.c (ix86_target_string): Add -mpconfig and -mwbnoinvd. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_init_mmx_sse_builtins): Add special_args2. * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, TARGET_WBNOINVD, TARGET_WBNOINVD_P): New. * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. (define_insn "wbinvd", define_insn "wbnoinvd"): New. * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. * config/i386/immintrin.h (_wbinvd): New intrinsic. * config/i386/pconfigintrin.h: New file. * config/i386/wbnoinvdintrin.h: Ditto. * config/i386/x86intrin.h: Add headers pconfigintrin.h and wbnoinvdintrin.h. * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. * gcc.target/i386/wbinvd-1.c: New test. * gcc.target/i386/wbnoinvd-1.c: Ditto. * gcc.target/i386/pconfig-1.c: Ditto. From-SVN: r258247
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-12-22Enable AVX512BITALGJulia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET, OPTION_MASK_ISA_AVX512BITALG_UNSET): New. (ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting. * config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16, _mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16, _mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8, _mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8, _mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16, _mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask, _mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8, _mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8, _mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics. * config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64, _mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32, _mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64, _mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64, _mm256_maskz_popcnt_epi64): New intrinsics. * config/i386/cpuid.h (bit_AVX512BITALG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI, V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI, V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types. * config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di, __builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di, __builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si, __builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si, __builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi, __builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi, __builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi, __builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi, __builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi, __builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask, __builtin_ia32_vpshufbitqmb256_mask, __builtin_ia32_vpshufbitqmb512_mask): New builtins. * config/i386/i386-c.c (__AVX512BITALG__): New. * config/i386/i386.c (isa2_opts): Add -mavx512bitalg. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_args_builtin): Handle new types. * config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New. * config/i386/i386.opt: Add -mavx512bitalg. * config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/sse.md (VI48_AVX512VLBW): New iterator. (vpopcount<mode><mask_name>): Add more types. (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New. * doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq. gcc/testsuite/ * g++.dg/other/i386-2.C: Add new options. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG. * gcc.target/i386/avx512bitalg-vpopcntb-1.c: New. * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New. * gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types. * gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics. * gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto. * gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto. Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com> From-SVN: r255975
2017-12-20Enable VPCLMULQDQ supportJulia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET, OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New. (ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2. * config.gcc: Include vpclmulqdqintrin.h. * config/i386/cpuid.h: Handle bit_VPCLMULQDQ. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -mvpclmulqdq. * config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di, __builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New. * config/i386/i386-c.c (__VPCLMULQDQ__): New. * config/i386/i386.c (isa2_opts): Add -mcx16. (isa_opts): Add -mpclmulqdq, remove -mcx16. (ix86_option_override_internal): Move mcx16 to flags2. (ix86_valid_target_attribute_inner_p): Add vpclmulqdq. (ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ. * config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New. * config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2. * config/i386/immintrin.h: Include vpclmulqdqintrin.h. * config/i386/sse.md (vpclmulqdq_<mode>): New pattern. * config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128, _mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics. * doc/invoke.texi: Add -mvpclmulqdq. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_VPCLMULQDQ. * gcc.target/i386/avx512f-vpclmulqdq-2.c: New test. * gcc.target/i386/avx512vl-vpclmulqdq-2.c: Ditto. * gcc.target/i386/vpclmulqdq.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_vpclmulqdq): New. From-SVN: r255850
2017-12-12Enable VAES support [1/5]Julia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET, OPTION_MASK_ISA_VAES_UNSET): New. (ix86_handle_option): Handle -mvaes. * config/i386/cpuid.h: Define bit_VAES. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mvaes. * config/i386/i386-c.c (__VAES__): New. * config/i386/i386.c (ix86_target_string): Add -mvaes. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386.h (TARGET_VAES, TARGET_VAES_P): New. * config/i386/i386.opt: Add -mvaes. * doc/invoke.texi: Ditto. From-SVN: r255571
2017-12-05Enable VNNI support [1/5]Julia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET, OPTION_MASK_ISA_AVX512VNNI_UNSET): New. (ix86_handle_option): Handle -mavx512vnni. * config/i386/cpuid.h (bit_AVX512VNNI): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit. * config/i386/i386-c (__AVX512VNNI__): New. * config/i386/i386.c (ix86_target_string): Handle new option. (ix86_valid_target_attribute_inner_p): Handle new option. * config/i386/i386.h (TARGET_AVX512VNNI, TARGET_AVX512VNNI_P): New. * config/i386/i386.opt (mavx512vnni): New option. From-SVN: r255401
2017-11-16Enable VBMI2 support [1/7]Julia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET, OPTION_MASK_ISA_AVX512VBMI2_UNSET): New. (ix86_handle_option): Handle -mavx512vbmi2. * config/i386/cpuid.h: Add bit_AVX512VBMI2. * config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit. * config/i386/i386-c.c (__AVX512VBMI2__): New. * config/i386/i386.c (ix86_target_string): Handle -mavx512vbmi2. (ix86_valid_target_attribute_inner_p): Ditto. * config/i386/i386.h (TARGET_AVX512VBMI2, TARGET_AVX512VBMI2_P): New. * config/i386/i386.opt (mavx512vbmi2): New option. * doc/invoke.texi: Add new option. From-SVN: r254796
2017-10-21Update x86 backend to enable Intel CET.Igor Tsimbalist1-0/+2
All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977
2017-10-20Add GFNI command line options and macrosJulia Koval1-0/+1
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_GFNI_SET, (OPTION_MASK_ISA_GFNI_UNSET): New. (ix86_handle_option): Handle OPT_mgfni. * config/i386/cpuid.h (bit_GFNI): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect gfni. * config/i386/i386-c.c (ix86_target_macros_internal): Define __GFNI__. * config/i386/i386.c (ix86_target_string): Add -mgfni. (ix86_valid_target_attribute_inner_p): Add OPT_mgfni. * config/i386/i386.h (TARGET_GFNI, TARGET_GFNI_P): New. * config/i386/i386.opt: Add mgfni. From-SVN: r253922
2017-05-31Fix typo in a comment in cpuid.h (PR target/79155).Martin Liska1-1/+1
2017-05-31 Martin Liska <mliska@suse.cz> PR target/79155 * config/i386/cpuid.h: Fix typo in a comment in cpuid.h. From-SVN: r248729
2017-05-01re PR target/68491 (libgcc calls __get_cpuid with 0 level breaks on early 486)Uros Bizjak1-2/+4
PR target/68491 * config/i386/cpuid.h (__get_cpuid): Always return 0 when __get_cpuid_max returns 0. (__get_cpuid_count): Ditto. From-SVN: r247439
2017-02-23re PR target/71017 (libgcc/config/i386/cpuinfo.c:346:17: runtime error: left ↵Dominique d'Humieres1-1/+1
shift of 1 by 31 places cannot be represented in type 'int') 2017-01-23 Dominique d'Humieres <dominiq@lps.ens.fr> PR target/71017 * config/i386/cpuid.h: Fix another undefined behavior. From-SVN: r245680
2017-02-17i386-common.c (OPTION_MASK_ISA_RDPID_SET): New.Julia Koval1-0/+1
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RDPID_SET): New. (OPTION_MASK_ISA_PKU_UNSET): New. (ix86_handle_option): Handle -mrdpid. * config/i386/cpuid.h (bit_RDPID): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect RDPID feature. * config/i386/i386-builtin.def (__builtin_ia32_rdpid): New. * config/i386/i386-c.c (ix86_target_macros_internal): Handle RDPID flag. * config/i386/i386.c (ix86_target_string): Add -mrdpid to isa2_opts. (ix86_valid_target_attribute_inner_p): Add "rdpid". (ix86_expand_builtin): Handle IX86_BUILTIN_RDPID. * config/i386/i386.h (TARGET_RDPID, TARGET_RDPID_P): New. * config/i386/i386.md (define_insn "rdpid"): New. * config/i386/i386.opt Add -mrdpid. * config/i386/immintrin.h (_rdpid_u32): New. testsuite/ChangeLog: * gcc.target/i386/rdpid.c New test. * gcc.target/i386/sse-12.c: Add -mrdpid. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r245540
2017-01-12builtin_target.c (check_features): Check all supported ↵Uros Bizjak1-5/+7
__builtin_cpu_supports options. * gcc.target/i386/builtin_target.c (check_features): Check all supported __builtin_cpu_supports options. From-SVN: r244375
2017-01-11i386-common.c (OPTION_MASK_ISA_SGX_UNSET): New.Julia Koval1-0/+1
* common/config/i386/i386-common.c (OPTION_MASK_ISA_SGX_UNSET): New. (OPTION_MASK_ISA_SGX_SET): New. (ix86_handle_option): Handle OPT_msgx. * config.gcc: Added sgxintrin.h. * config/i386/driver-i386.c (host_detect_local_cpu): Detect sgx. * config/i386/i386-c.c (ix86_target_macros_internal): Define __SGX__. * config/i386/i386.c (ix86_target_string): Add -msgx. (PTA_SGX): New. (ix86_option_override_internal): Handle new options. (ix86_valid_target_attribute_inner_p): Add sgx. * config/i386/i386.h (TARGET_SGX, TARGET_SGX_P): New. * config/i386/i386.opt: Add msgx. * config/i386/sgxintrin.h: New file. * config/i386/x86intrin.h: Add sgxintrin.h. testsuite/ChangeLog: * gcc.target/i386/sgx.c New test. * gcc.target/i386/sse-12.c: Add -msgx. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. Co-Authored-By: Uros Bizjak <ubizjak@gmail.com> From-SVN: r244339
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