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2024-09-13AVR: avr.cc - Reorder functions to require less forward decls.Georg-Johann Lay1-407/+394
gcc/ * config/avr/avr.cc (avr_init_machine_status): Move code to... (avr_option_override) <init_machine_status>: ...lambda. (avr_insn_has_reg_unused_note_p): Move up. (_reg_unused_after, reg_unused_after): Move up. (output_reload_in_const): Move up. (avr_c_mode_for_floating_type): Move down.
2024-09-06AVR: Remove "Atmel" from header comment.Georg-Johann Lay22-27/+27
gcc/ * config/avr/avr.h: Remove "Atmel" from header comment. * config/avr/avr.cc: Same. * config/avr/avr.md: Same. * config/avr/avr.opt: Same. * config/avr/avr-dimode.md: Same. * config/avr/avr-fixed.md: Same. * config/avr/constraints.md: Same. * config/avr/predicates.md: Same. * config/avr/avr-log.cc: Same. * config/avr/avrlibc.h: Same. * config/avr/specs.h: Same. * common/config/avr/avr-common.cc: Same. * doc/install.texi: Same. * config/avr/avr-arch.h: Adjust header comment. * config/avr/avr-c.cc: Same. * config/avr/avr-mcus.def: Same. * config/avr/avr-modes.def: Same. * config/avr/avr-passes.cc: Same. * config/avr/avr-passes.def: Same. * config/avr/avr-protos.h: Same. * config/avr/driver-avr.cc: Same. * config/avr/elf.h: Same. * config/avr/gen-avr-mmcu-specs.cc: Same. * config/avr/gen-avr-mmcu-texi.cc: Same.
2024-08-31AVR: Run pass avr-fuse-add a second time after pass_cprop_hardreg.Georg-Johann Lay2-0/+28
gcc/ * config/avr/avr-passes.cc (avr_pass_fuse_add) <clone>: Override. * config/avr/avr-passes.def (avr_pass_fuse_add): Run again after pass_cprop_hardreg.
2024-08-31AVR: Tidy pass avr-fuse-add.Georg-Johann Lay4-43/+12
gcc/ * config/avr/avr-protos.h (avr_split_tiny_move): Rename to avr_split_fake_addressing_move. * config/avr/avr-passes.def: Same. * config/avr/avr-passes.cc: Same. (avr_pass_data_fuse_add) <tv_id>: Set to TV_MACH_DEP. * config/avr/avr.md (split-lpmx): Remove a define_split. Such splits are performed by avr_split_fake_addressing_move.
2024-08-31AVR: Don't print a space after , when printing instructions.Georg-Johann Lay1-12/+12
gcc/ * config/avr/avr.cc: Follow the convention to not add a space after comma when printing instructions.
2024-08-29AVR: target/115830 - Make better use of SREG.N and SREG.Z.Georg-Johann Lay5-260/+810
This patch adds new CC modes CCN and CCZN for operations that set SREG.N, resp. SREG.Z and SREG.N. Add peephole2 patterns to generate new compute + branch insns that make use of the Z and N flags. Most of these patterns need their own asm output routines that don't do all the micro-optimizations that the ordinary outputs may perform, as the latter have no requirement to set CC in a usable way. We don't use cmpelim because it cannot provide scratch regs (which peephole2 can), and some of the patterns require a scratch reg, whereas the same operations that don't set REG_CC don't require a scratch. See the comments in avr.md for details. The existing add.for.cc* patterns are simplified as they no more cover QImode, which is handled in a separate QImode case. Apart from that, it adds 3 patterns for subtractions and one pattern for shift left, all for multi-byte cases (HI, PSI, SI). The add.for.cc* patterns now use CC[Z]Nmode, instead of the formerly abuse of CCmode. PR target/115830 gcc/ * config/avr/avr-modes.def (CCN, CCZN): New CC_MODEs. * config/avr/avr-protos.h (avr_cond_branch): New from ret_cond_branch. (avr_out_plus_set_N, avr_op8_ZN_operator, avr_cmp0_code) (avr_out_op8_set_ZN, avr_len_op8_set_ZN): New protos. (ccn_reg_rtx, cczn_reg_rtx): New declarations. * config/avr/avr.cc (avr_cond_branch): New from ret_cond_branch. (avr_cond_string): Add bool cc_overflow_unusable argument. (avr_print_operand) ['L']: Like 'j' but overflow unusable. ['K']: Like 'k' but overflow unusable. (avr_out_plus_set_ZN): Remove handling of QImode. (avr_out_plus_set_N, avr_op8_ZN_operator, avr_cmp0_code) (avr_out_op8_set_ZN, avr_len_op8_set_ZN): New functions. (avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_N]: Hande case. (avr_class_max_nregs): All MODE_CCs occupy one hard reg. (avr_hard_regno_nregs): Same. (avr_hard_regno_mode_ok) [REG_CC]: Allow all MODE_CC. (pass_manager.h, context.h, tree-pass.h): Include them. (ccn_reg_rtx, cczn_reg_rtx): New GTY variables. (avr_init_expanders): Initialize them. (avr_option_override): Run peephole2 a second time. * config/avr/avr.md (adjust_len) [add_set_N]: New attr value. (ALLCC, HI_SI): New mode iterators. (CCname): New mode attribute. (eqnegtle, cmp_signed, op8_ZN): New code iterators. (swap, SWAP): New code attributes. (branch): Handle CCNmode and CCZNmode. Assimilate... (difficult_branch): ...this insn. (p1m1): Remove. (gen_add_for_<code>_<mode>): Adjust to CCNmode and CCZNmode. Use HISI as mode iterator. Extend peephole2s that produce them. (*add.for.eqne.<mode>): Extend to *add.for.cc[z]n.<mode>. (*ashift.for.ccn.<mode>): New insn and peephole2 to make them. (*sub.for.cczn.<mode>, *sub-extend<mode>.for.cczn.<mode>): New insns and peephole2s to make them. (*op8.for.cczn.<code>): New insn and peephole2 to make them. * config/avr/predicates.md (const_1_to_3_operand) (abs1_abs2_operand, signed_comparison_operator) (op8_ZN_operator): New predicates. gcc/testsuite/ * gcc.target/avr/pr115830-add.c: New test. * gcc.target/avr/pr115830-add-c.c: New test. * gcc.target/avr/pr115830-add-i.c: New test. * gcc.target/avr/pr115830-and.c: New test. * gcc.target/avr/pr115830-asl.c: New test. * gcc.target/avr/pr115830-asr.c: New test. * gcc.target/avr/pr115830-ior.c: New test. * gcc.target/avr/pr115830-lsr.c: New test. * gcc.target/avr/pr115830-asl32.c: New test. * gcc.target/avr/pr115830-sub.c: New test. * gcc.target/avr/pr115830-sub-ext.c: New test.
2024-08-29AVR: Outsource code for avr-specific passes to new avr-passes.cc.Georg-Johann Lay5-2119/+2221
gcc/ * config.gcc (extra_objs) [target=avr]: Add avr-passes.o. * config/avr/t-avr (avr-passes.o): New rule to make it. * config/avr/avr.cc (#define INCLUDE_VECTOR): Remove. (cfganal.h, cfgrtl.h, context.h, tree-pass.h, print-rtl.h): Don't include them. (avr_strict_signed_p, avr_strict_unsigned_p, avr_2comparisons_rhs) (make_avr_pass_recompute_notes, make_avr_pass_casesi) (make_avr_pass_ifelse, make_avr_pass_pre_proep, avr_split_tiny_move) (emit_move_ccc, emit_move_ccc_after, reg_seen_between_p) (avr_maybe_adjust_cfa, avr_redundant_compare_regs) (avr_parallel_insn_from_insns, avr_is_casesi_sequence) (avr_optimize_casesi, avr_redundant_compare, make_avr_pass_fuse_add) (avr_optimize_2ifelse, avr_rest_of_handle_ifelse) (avr_casei_sequence_check_operands) Move functions... (avr_pass_data_fuse_add, avr_pass_data_ifelse) (avr_pass_data_casesi, avr_pass_data_recompute_notes) (avr_pass_data_pre_proep): Move objects... (avr_pass_fuse_add, avr_pass_pre_proep, avr_pass_recompute_notes) (avr_pass_ifelse, avr_pass_casesi, AVR_LdSt_Props): Move classes... * config/avr/avr-passes.cc: ... to this new C++ module. (struct Ranges): Move to... * config/avr/ranges.h: ...this new file. * config/avr/avr-protos.h: Adjust comments.
2024-08-28AVR: Overhaul the avr-ifelse RTL optimization pass.Georg-Johann Lay1-229/+758
Mini-pass avr-ifelse realizes optimizations that replace two cbranch insns with one comparison and two branches. This patch adds the following improvements: - The right operand of the comparisons may also be REGs. Formerly only CONST_INT was handled. - The RTX code of the first comparison in no more restricted to (effectively) EQ. - When the second cbranch is located in the fallthrough path of the first cbranch, then difficult (expensive) comparisons can always be avoided. This may require to swap the branch targets. (When the second cbranch is located after the target label of the first one, then getting rid of difficult branches would require to reorder blocks.) - The code has been cleaned up: avr_rest_of_handle_ifelse() now just scans the insn stream for optimization candidates. The code that actually performs the transformation has been outsourced to the new function avr_optimize_2ifelse(). - The code to find a better representation for reg-const_int comparisons has been split into two parts: First try to find codes such that the right-hand sides of the comparisons are the same (avr_2comparisons_rhs). When this succeeds then one comparison can serve two branches, and that function tries to get rid of difficult branches. This is always possible when the second cbranch is located in the fallthrough path of the first one. Some final notes on why we don't use compare-elim: 1) The two cbranch insns may come with different scratch operands depending on the chosen constraint alternatives. There are cases where the outgoing comparison requires a scratch but only one incoming cbranch has one. 2) Avoiding difficult branches can be achieved by rewiring basic blocks. compare-elim doesn't do that; it doesn't even know the costs of the branch codes. 3) avr_2comparisons_rhs() may de-canonicalize a comparison to achieve its goal. compare-elim doesn't know how to do that. 4) There are more reasons, see for example the commit message and discussion for PR115830. avr_2comparisons_rhs tries to decompose the interval as given by some [u]intN_t into three intervals using the new Ranges struct that implemens set operations on finite unions of intervals. Sadly, value-range.h is not well suited for that, and writing a wrapper around it that avoids all corner case ICEs would be more laborious than struct Ranges. gcc/ * config/avr/avr.cc (INCLUDE_VECTOR): Define it. (cfganal.h): Include it. (Ranges): New struct. (avr_2comparisons_rhs, avr_redundant_compare_regs) (avr_strict_signed_p, avr_strict_unsigned_p): New static functions. (avr_redundant_compare): Overhaul: Allow more cases. (avr_optimize_2ifelse): New static function, outsourced from... (avr_rest_of_handle_ifelse): ...this method. gcc/testsuite/ * gcc.target/avr/torture/ifelse-c.h: New file. * gcc.target/avr/torture/ifelse-d.h: New file. * gcc.target/avr/torture/ifelse-q.h: New file. * gcc.target/avr/torture/ifelse-r.h: New file. * gcc.target/avr/torture/ifelse-c-i8.c: New test. * gcc.target/avr/torture/ifelse-d-i8.c: New test. * gcc.target/avr/torture/ifelse-q-i8.c: New test. * gcc.target/avr/torture/ifelse-r-i8.c: New test. * gcc.target/avr/torture/ifelse-c-i16.c: New test. * gcc.target/avr/torture/ifelse-d-i16.c: New test. * gcc.target/avr/torture/ifelse-q-i16.c: New test. * gcc.target/avr/torture/ifelse-r-i16.c: New test. * gcc.target/avr/torture/ifelse-c-u16.c: New test. * gcc.target/avr/torture/ifelse-d-u16.c: New test. * gcc.target/avr/torture/ifelse-q-u16.c: New test. * gcc.target/avr/torture/ifelse-r-u16.c: New test.
2024-08-18AVR: Tweak 16-bit addition with const that didn't get a LD_REGS register.Georg-Johann Lay1-2/+18
The 16-bit additions like addhi3 have two forms: One with a scratch:QI and one without, where the latter is required because reload cannot deal with a scratch when spill code pops a 16-bit addition. Passes like combine and fwprop1 may come up with the non-scratch version, which is sub-optimal in the case when the addition is performed in a NO_LD_REGS register because the operands will be spilled to LD_REGS. Having a scratch:QI at disposal can lead to better code with less spills. gcc/ * config/avr/avr.md (*add<mode>3_split) [!reload_completed]: Add a scratch:QI to 16-bit additions with constant.
2024-08-18AVR: ad target/116407 - Fix linker error "relocation truncated to fit".Georg-Johann Lay1-1/+1
PR target/116407 gcc/ * config/avr/avr.md (*dec-and-branchhi!=-1.l.clobber): Increase the additional jump offset to 2 words.
2024-08-18AVR: target/116407 - Fix linker error "relocation truncated to fit".Georg-Johann Lay3-9/+12
Some text peepholes output extra instructions prior to a branch instruction and that increase the jump offset of backward branches. PR target/116407 gcc/ * config/avr/avr-protos.h (avr_jump_mode): Add an int argument. * config/avr/avr.cc (avr_jump_mode): Add an int argument to increase the computed jump offset of backwards branches. * config/avr/avr.md (*dec-and-branchhi!=-1, *dec-and-branchsi!=-1): Increase the jump offset used by avr_jump_mode() as needed. gcc/testsuite/ * gcc.target/avr/torture/pr116407-2.c: New test. * gcc.target/avr/torture/pr116407-4.c: New test.
2024-08-17AVR: target/116390 - Fix an avrtiny asm out template.Georg-Johann Lay1-15/+15
PR target/116390 gcc/ * config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix output templates for the reg_base == reg_src and reg_src == reg_base - 2 cases. gcc/testsuite/ * gcc.target/avr/torture/pr116390.c: New test.
2024-08-16AVR: target/85624 - Use HImode for clrmemqi alignment.Georg-Johann Lay1-4/+2
gcc/ PR target/85624 * config/avr/avr.md (*clrmemqi*): Use HImode for alignment operand. (cherry picked from commit 507b4e147588c0fafe952b7226dd764ebeebb103)
2024-08-13Regenerate avr.opt.urlsMark Wielaard1-0/+2
avr added an -mlra option, but the avr.opt.url file wasn't regenerated. Note that commit 149a23ee2568 ("AVR: -mlra is not documeted in TEXI.") did add the Undocumented flag, but that still needs the avr.op.urls file to be updated. Fixes: 09a87ea666b2 ("AVR: ad target/113934 - Add option -mlra to enable LRA.") gcc/ChangeLog: * config/avr/avr.opt.urls: Regenerate.
2024-08-12AVR: target/85624 - Fix non-matching alignment in clrmem* insns.Georg-Johann Lay1-0/+2
The clrmem* patterns don't use the provided alignment information, hence the setmemhi expander can just pass down 0 as alignment to the clrmem* insns. PR target/85624 gcc/ * config/avr/avr.md (setmemhi): Set alignment to 0. gcc/testsuite/ * gcc.target/avr/torture/pr85624.c: New test.
2024-08-11AVR: -mlra is not documeted in TEXI.Georg-Johann Lay1-1/+1
gcc/ * config/avr/avr.opt (mlra): Set Undocumented flag.
2024-08-11AVR: Add function avr.cc::ra_in_progress().Georg-Johann Lay1-6/+13
It returns lra_in_progress resp. reload_in_progress depending on avr_lra_p. Currently, direct use of ra_in_progress() is only made with -mlog=. gcc/ * config/avr/avr.cc (ra_in_progress): New static function. (avr_legitimate_address_p, avr_addr_space_legitimate_address_p) (extra_constraint_Q): Use it with -mlog=.
2024-08-10AVR: ad target/113934 - Add option -mlra to enable LRA.Georg-Johann Lay2-2/+17
PR target/113934 gcc/ * config/avr/avr.opt (-mlra): New target option. * config/avr/avr.cc (avr_use_lra_p): New function. (TARGET_LRA_P): Use it. (avr_hard_regno_mode_ok) [lra]: Don't disallow 4-byte modes for X.
2024-08-09AVR: Tidy up code for __[x]load insns.Georg-Johann Lay1-21/+9
gcc/ * config/avr/avr.md (*load_<mode>_libgcc, *xload_<mode>_libgcc): Tidy up code.
2024-08-08AVR: target/116295 - Fix unrecognizable insn with __flash read.Georg-Johann Lay1-0/+4
Some loads from non-generic address-spaces are performed by libgcc calls, and they don't have a POST_INC form. Don't consider such insns when running -mfuse-add. PR target/116295 gcc/ * config/avr/avr.cc (Mem_Insn::Mem_Insn): Don't consider MEMs that are avr_mem_memx_p or avr_load_libgcc_p. gcc/testsuite/ * gcc.target/avr/torture/pr116295.c: New test.
2024-08-08AVR: Improve POST_INC output in some rare cases.Georg-Johann Lay1-1/+31
gcc/ * config/avr/avr.cc (avr_insn_has_reg_unused_note_p): New function. (_reg_unused_after): Use it to recognize more cases. (avr_out_lpm_no_lpmx) [POST_INC]: Use reg_unused_after.
2024-08-01AVR: Tweak unsigned comparisons against 256 resp. 65536.Georg-Johann Lay1-2/+34
u16 >= 256 can be performed by testing the hi8 part against 0. u32 >= 65536 can be performed by testing the high word against 0. The optimization is performed in split2 after register allocation because the register allocator likely spills for subregs. gcc/ * config/avr/avr.md (cbranch<mode>4_insn): Split to a test of the high part against 0 if possible.
2024-08-01AVR: Tweak register pressure for const_fixed compares against "M".Georg-Johann Lay2-14/+21
When comparing a 16-bit or 32-bit integer against a constant in the range 0...0xff, constraint M is used because no scratch reg is needed in that case. Same can be done for fixed-point compares. gcc/ * config/avr/constraints.md (YMM): New constraint. * config/avr/avr.md (cmp<mode>3, *cmp<mode>3) (cbranch<mode>4_insn): Allow YMM where M is allowed.
2024-07-29AVR: avr.cc - Fix a typo in a diagnostic.Georg-Johann Lay1-1/+1
gcc/ * config/avr/avr.cc (avr_set_current_function): Fix typo in error message.
2024-07-28AVR target 116056 - Support attribute signal(n), interrupt(n) and noblock.Georg-Johann Lay5-32/+221
This patch adds support for arguments to the signal and interrupt function attributes. It allows to specify the ISR by means of the associated IRQ number, in extension to the current attributes that require to specify the ISR name like "__vector_1" as (assembly) name for the function. The new feature is more convenient, e.g. when the ISR is implemented by a class method or in a namespace. There is no requirement that the ISR is externally visible. The syntax is like: __attribute__((signal(1, 2, ...), signal(3, 4, ...))) [static] void isr_function (void) { // Code } Moreover, this patch adds support for the "noblock" function attribute to let an ISR start with a SEI instruction. Attribute "signal" together with "noblock" behaves like "interrupt" but without imposing a specific function name or visibility like "interrupt" does. PR target/116056 gcc/ * config/avr/avr.h (machine_function) <is_noblock>: New field. * config/avr/avr-c.cc (avr_cpu_cpp_builtins) <__HAVE_SIGNAL_N__>: New built-in macro. * config/avr/avr.cc (avr_declare_function_name): New function. (avr_attribute_table) <noblock>: New function attribute>. <signal, interrupt>: Allow any number of args. (avr_insert_attributes): Check validity of "signal" and "interrupt" arguments. (avr_foreach_function_attribute, avr_interrupt_signal_function) (avr_isr_number, avr_asm_isr_alias, avr_handle_isr_attribute) (avr_noblock_function_p): New static functions. (avr_interrupt_function): New from avr_interrupt_function_p. Adjust callers. (avr_signal_function): New from avr_signal_function_p. Adjust callers. (avr_set_current_function): Only diagnose non-__vector ISR names when "signal" or "interrupt" attribute has no args. Set cfun->machine->is_noblock. Warn about "noblock" in non-ISR functions. (struct avr_fun_cookie): New. (avr_expand_prologue, avr_asm_function_end_prologue): Handle "noblock". * config/avr/elf.h (ASM_DECLARE_FUNCTION_NAME): New define. * config/avr/avr-protos.h (avr_declare_function_name): New proto. * doc/extend.texi (AVR Function Attributes): Document signal(num) and interrupt(num). * doc/invoke.texi (AVR Built-in Macros) <__HAVE_SIGNAL_N__>: Document. gcc/testsuite/ * gcc.target/avr/torture/signal_n-1.c: New test. * gcc.target/avr/torture/signal_n-2.c: New test. * gcc.target/avr/torture/signal_n-3.c: New test. * gcc.target/avr/torture/signal_n-4.cpp: New test.
2024-07-19AVR: Support new built-in function __builtin_avr_mask1.Georg-Johann Lay3-0/+201
gcc/ * config/avr/builtins.def (MASK1): New DEF_BUILTIN. * config/avr/avr.cc (avr_rtx_costs_1): Handle rtx costs for expressions like __builtin_avr_mask1. (avr_init_builtins) <uintQI_ftype_uintQI_uintQI>: New tree type. (avr_expand_builtin) [AVR_BUILTIN_MASK1]: Diagnose unexpected forms. (avr_fold_builtin) [AVR_BUILTIN_MASK1]: Handle case. * config/avr/avr.md (gen_mask1): New expand helper. (mask1_0x01_split, mask1_0x80_split, mask1_0xfe_split): New insn-and-split. (*mask1_0x01, *mask1_0x80, *mask1_0xfe): New insns. * doc/extend.texi (AVR Built-in Functions) <__builtin_avr_mask1>: Document new built-in function. gcc/testsuite/ * gcc.target/avr/torture/builtin-mask1.c: New test.
2024-07-17AVR: target/90616 - Improve adding constants that are 0 mod 256.Georg-Johann Lay4-0/+47
This patch introduces a new insn that works as an insn combine pattern for (plus:HI (zero_extend:HI (reg:QI)) (const_0mod256_operannd:HI)) which requires at most 2 instructions. When the input register operand is already in HImode, the addhi3 printer only adds the hi8 part when it sees a SYMBOL_REF or CONST aligned to at least 256 bytes. (The CONST_INT case was already handled). gcc/ PR target/90616 * config/avr/predicates.md (const_0mod256_operand): New predicate. * config/avr/constraints.md (Cp8): New constraint. * config/avr/avr.md (*aligned_add_symbol): New insn. * config/avr/avr.cc (avr_out_plus_symbol) [HImode]: When op2 is a multiple of 256, there is no need to add / subtract the lo8 part. (avr_rtx_costs_1) [PLUS && HImode]: Return expected costs for new insn *aligned_add_symbol as it applies.
2024-07-16AVR: Overhaul add and sub insns that extend one operand.Georg-Johann Lay3-214/+159
These are insns of the forms (set (regA:M) (plus:M (extend:M (regB:L)) (regA:M))) and (set (regA:M) (minus:M (regA:M) (extend:M (regB:L)))) where "extend" may be a sign-extend or zero-extend, and the integer modes are SImode >= M > L >= QImode. The existing patterns are now represented in terms of insns with mode iterators and a code iterator over any_extend, and these new insn support all valid combinations of M and L (which previously was not the case). gcc/ * config/avr/avr.cc (avr_out_minus): Assimilate into... (avr_out_plus_ext): ...this new function. (avr_adjust_insn_length) [ADJUST_LEN_PLUS_EXT]: Handle case. (avr_rtx_costs_1) [PLUS, MINUS]: Adjust RTX costs. * config/avr/avr.md (adjust_len) <plus_ext>: Add new attribute value. (*addpsi3_zero_extend.hi_split): Assimilate... (*addpsi3_zero_extend.qi_split): Assimilate... (*addsi3_zero_extend_split): Assimilate... (*addsi3_zero_extend.hi_split): Assimilate... (*addpsi3_sign_extend.hi_split): Assimilate... (*addhi3.sign_extend1_split): Assimilate... (*add<PSISI:mode>3.<code>.<QIPSI:mode>_split): ...into this new insn-and-split. (*addpsi3_zero_extend.hi): Assimilate... (*addpsi3_zero_extend.qi): Assimilate... (*addsi3_zero_extend): Assimilate... (*addsi3_zero_extend.hi): Assimilate... (*addpsi3_sign_extend.hi): Assimilate... (*addhi3.sign_extend1): Assimilate... (*add<PSISI:mode>3.<code>.<QIPSI:mode>): ...into this new insn. (*subpsi3_sign_extend.hi_split): Assimilate... (*subhi3.sign_extend2_split): Assimilate... (*sub<HISI:mode>3.zero_extend.<QIPSI:mode>_split): Assimilate... (*sub<HISI:mode>3.<code><QIPSI:mode>_split): ...into this new insn-and-split. (*subpsi3_sign_extend.hi): Assimilate... (*subhi3.sign_extend2): Assimilate... (*sub<HISI:mode>3.zero_extend.<QIPSI:mode>): Assimilate... (*sub<HISI:mode>3.<code>.<QIPSI:mode>): ...into this new insn. (*sub<HISI:mode>3.zero_extend.<QIPSI:mode>): Use avr_out_plus_ext for asm out. * config/avr/avr-protos.h (avr_out_minus): Remove. (avr_out_plus_ext): New proto. gcc/testsuite/ * gcc.target/avr/torture/add-extend.c: New test. * gcc.target/avr/torture/sub-extend.c: New test.
2024-07-16AVR: Allow more combinations of XOR / IOR with byte-shifts.Georg-Johann Lay3-27/+104
This patch takes some existing patterns that have QImode as one input and uses a mode iterator to allow for more modes to match. These insns are split after reload into *xorqi3 resp. *iorqi3 insn(s). gcc/ * config/avr/avr-protos.h (avr_emit_xior_with_shift): New proto. * config/avr/avr.cc (avr_emit_xior_with_shift): New function. * config/avr/avr.md (any_lshift): New code iterator. (*<xior:code><mode>.<any_lshift:code>): New insn-and-split. (<code><HISI:mode><QIPSI:mode>.0): Replaces... (*<code_stdname><mode>qi.byte0): ...this one. (*<xior:code><HISI:mode><QIPSI:mode>.<any_lshift:code>): Replaces... (*<code_stdname><mode>qi.byte1-3): ...this one.
2024-07-15AVR: avr-md - Simplify GET_MODE and GET_MODE_BITSIZE.Georg-Johann Lay2-22/+22
gcc/ * config/avr/avr.md: Simplify mode usage. (GET_MODE_SIZE (<MODE>mode)): Use <SIZE> instead. (GET_MODE_BITSIZE (<MODE>mode) - 1): Use <MSB> instead. (GET_MODE_MASK (QImode)): Use 0xff instead. * config/avr/avr-fixed.md: Same.
2024-07-11AVR: Tidy up subtract-and-zero_extend insns.Georg-Johann Lay3-97/+58
There are these insns that subtract and zero-extend where the subtrahend is zero-extended to the mode of the minuend. This patch uses one insn (and split) with mode iterators instead of spelling out each variant individually. This has the additional benefit that u32 - u24 is also supported, which previously wasn't. gcc/ * config/avr/avr-protos.h (avr_out_minus): New prototype. * config/avr/avr.cc (avr_out_minus): New function. * config/avr/avr.md (*sub<HISI:mode>3.zero_extend.<QIPSI:mode>) (*sub<HISI:mode>3.zero_extend.<QIPSI:mode>_split): New insns. (*subpsi3_zero_extend.qi_split): Remove isns_and_split. (*subpsi3_zero_extend.hi_split): Remove insn_and_split. (*subhi3_zero_extend1_split): Remove insn_and_split. (*subsi3_zero_extend_split): Remove insn_and_split. (*subsi3_zero_extend.hi_split): Remove insn_and_split. (*subpsi3_zero_extend.qi): Remove insn. (*subpsi3_zero_extend.hi): Remove insn. (*subhi3_zero_extend1): Remove insn. (*subsi3_zero_extend): Remove insn. (*subsi3_zero_extend.hi): Remove insn. gcc/testsuite/ * gcc.target/avr/torture/sub-zerox.c: New test.
2024-07-06AVR: Create more opportunities for -mfuse-add optimization.Georg-Johann Lay2-21/+21
avr_split_tiny_move() was only run for AVR_TINY because it has no PLUS addressing modes. Same applies to the X register on ordinary cores, and also to the Z register when used with [E]LPM. For example, without this patch long long addLL (long long *a, long long *b) { return *a + *b; } compiles with "-mmcu=atmgea128 -Os -dp" to: ... movw r26,r24 ; 80 [c=4 l=1] *movhi/0 movw r30,r22 ; 81 [c=4 l=1] *movhi/0 ld r18,X ; 82 [c=4 l=1] movqi_insn/3 adiw r26,1 ; 83 [c=4 l=3] movqi_insn/3 ld r19,X sbiw r26,1 adiw r26,2 ; 84 [c=4 l=3] movqi_insn/3 ld r20,X sbiw r26,2 adiw r26,3 ; 85 [c=4 l=3] movqi_insn/3 ld r21,X sbiw r26,3 adiw r26,4 ; 86 [c=4 l=3] movqi_insn/3 ld r22,X sbiw r26,4 adiw r26,5 ; 87 [c=4 l=3] movqi_insn/3 ld r23,X sbiw r26,5 adiw r26,6 ; 88 [c=4 l=3] movqi_insn/3 ld r24,X sbiw r26,6 adiw r26,7 ; 89 [c=4 l=2] movqi_insn/3 ld r25,X ld r10,Z ; 90 [c=4 l=1] movqi_insn/3 ... whereas with this patch it becomes: ... movw r26,r24 ; 80 [c=4 l=1] *movhi/0 movw r30,r22 ; 81 [c=4 l=1] *movhi/0 ld r18,X+ ; 140 [c=4 l=1] movqi_insn/3 ld r19,X+ ; 142 [c=4 l=1] movqi_insn/3 ld r20,X+ ; 144 [c=4 l=1] movqi_insn/3 ld r21,X+ ; 146 [c=4 l=1] movqi_insn/3 ld r22,X+ ; 148 [c=4 l=1] movqi_insn/3 ld r23,X+ ; 150 [c=4 l=1] movqi_insn/3 ld r24,X+ ; 152 [c=4 l=1] movqi_insn/3 ld r25,X ; 109 [c=4 l=1] movqi_insn/3 ld r10,Z ; 111 [c=4 l=1] movqi_insn/3 ... gcc/ * config/avr/avr.md: Also split with avr_split_tiny_move() for non-AVR_TINY. * config/avr/avr.cc (avr_split_tiny_move): Don't change memory references with base regs that can do PLUS addressing. (avr_out_lpm_no_lpmx) [POST_INC]: Don't output final ADIW when the address register is unused after. gcc/testsuite/ * gcc.target/avr/torture/fuse-add.c: New test.
2024-07-05AVR: target/87376 - Use nop_general_operand for DImode inputs.Georg-Johann Lay1-13/+13
The avr-dimode.md expanders have code like emit_move_insn(acc_a, operands[1]) where acc_a is a hard register and operands[1] might be a non-generic address-space memory reference. Such loads may clobber hard regs since some of them are implemented as libgcc calls /and/ 64-moves are expanded as eight byte-moves, so that acc_a or acc_b might be clobbered by such a load. This patch simply denies non-generic address-space references by using nop_general_operand for all avr-dimode.md input predicates. With the patch, all memory loads that require library calls are issued before the expander codes from avr-dimode.md are run. PR target/87376 gcc/ * config/avr/avr-dimode.md: Use "nop_general_operand" instead of "general_operand" as predicate for all input operands. gcc/testsuite/ * gcc.target/avr/torture/pr87376.c: New test.
2024-07-03AVR: target/98762 - Handle partial clobber in movqi output.Georg-Johann Lay1-5/+22
PR target/98762 gcc/ * config/avr/avr.cc (avr_out_movqi_r_mr_reg_disp_tiny): Properly restore the base register when it is partially clobbered. gcc/testsuite/ * gcc.target/avr/torture/pr98762.c: New test.
2024-07-01AVR: target/88236, target/115726 - Fix __memx code generation.Georg-Johann Lay2-3/+23
PR target/88236 PR target/115726 gcc/ * config/avr/avr.md (mov<mode>) [avr_mem_memx_p]: Expand in such a way that the destination does not overlap with any hard register clobbered / used by xload8qi_A resp. xload<mode>_A. * config/avr/avr.cc (avr_out_xload): Avoid early-clobber situation for Z by executing just one load when the output register overlaps with Z. gcc/testsuite/ * gcc.target/avr/torture/pr88236-pr115726.c: New test.
2024-06-25Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_typeKewen Lin2-3/+17
Currently how we determine which mode will be used for a floating point type is that for a given type precision (size) call mode_for_size to get the first mode which has this size in the specified class. On Powerpc, we have three modes (TF/KF/IF) having the same mode precision 128 (see[1]), so the processing forces us to have to place TF at the first place, it would require us to make more adjustment in some generic code to avoid some unexpected mode conversions and it would be even worse if we get rid of TF eventually one day. And as Joseph pointed out in [2], "floating types should have their mode, not a poorly defined precision value", as Joseph and Richi suggested, this patch is to introduce one hook mode_for_floating_type which returns the corresponding mode for type float, double or long double. The default implementation returns SFmode for float and DFmode for double or long double. For ports which need special treatment, there are some other patches for their own port specific implementation (referring to how {,LONG_}DOUBLE_TYPE_SIZE get used there). For all generic uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, depending on the context, some of them are replaced with TYPE_PRECISION of the according type node, some other are replaced with GET_MODE_PRECISION on the mode from mode_for_floating_type. This patch also poisons {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE, so most defines of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE in port specific are removed, but there are still some which are good to be kept for readability then they get renamed with port specific prefix. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651017.html [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html gcc/jit/ChangeLog: * jit-recording.cc (recording::memento_of_get_type::get_size): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. gcc/ChangeLog: * coretypes.h (enum tree_index): Forward declaration. * defaults.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * doc/rtl.texi: Update document by replacing {FLOAT,DOUBLE}_TYPE_SIZE with C type {float,double}. * doc/tm.texi.in: Document new hook mode_for_floating_type, remove document entries for {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE and update document for WIDEST_HARDWARE_FP_SIZE. * doc/tm.texi: Regenerate. * emit-rtl.cc (init_emit_once): Replace DOUBLE_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_DOUBLE_TYPE. * real.h (REAL_VALUE_TO_TARGET_LONG_DOUBLE): Use TYPE_PRECISION of long_double_type_node to replace LONG_DOUBLE_TYPE_SIZE. * system.h (FLOAT_TYPE_SIZE): Poison. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * target.def (mode_for_floating_type): New hook. * targhooks.cc (default_mode_for_floating_type): New function. (default_scalar_mode_supported_p): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE. * targhooks.h (default_mode_for_floating_type): New declaration. * tree-core.h (enum tree_index): Specify underlying type unsigned to sync with forward declaration in coretypes.h. (NUM_FLOATN_TYPES): Explicitly convert to int. (NUM_FLOATNX_TYPES): Likewise. (NUM_FLOATN_NX_TYPES): Likewise. * tree.cc (build_common_tree_nodes): Update macros {FLOAT,DOUBLE,LONG_DOUBLE}_TYPE_SIZE by calling targetm.c.mode_for_floating_type with TI_{FLOAT,DOUBLE,LONG_DOUBLE}_TYPE and set type mode accordingly. * config/arc/arc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/bpf/bpf.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/epiphany/epiphany.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/fr30/fr30.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/frv/frv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ft32/ft32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/gcn/gcn.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/iq2000/iq2000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/lm32/lm32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32c/m32c.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/m32r/m32r.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/microblaze/microblaze.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/mmix/mmix.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/moxie/moxie.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/msp430/msp430.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nds32/nds32.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nios2/nios2.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/nvptx/nvptx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/or1k/or1k.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pdp11/pdp11.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pru/pru.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/stormy16/stormy16.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/visium/visium.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/xtensa/xtensa.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rs6000/rs6000.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rs6000_c_mode_for_floating_type): New function. * config/rs6000/rs6000.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/aarch64/aarch64.cc (aarch64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/aarch64/aarch64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/alpha/alpha.cc (alpha_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/alpha/alpha.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/avr/avr.cc (avr_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/avr/avr.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/i386/i386.cc (ix86_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/i386/i386.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/ia64/ia64.cc (ia64_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/ia64/ia64.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/riscv/riscv.cc (riscv_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/riscv/riscv.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rl78/rl78.cc (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (rl78_c_mode_for_floating_type): New function. * config/rl78/rl78.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/rx/rx.cc (rx_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/rx/rx.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/s390/s390.cc (s390_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/s390/s390.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. * config/sh/sh.cc (sh_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Remove. * config/h8300/h8300.cc (h8300_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/h8300/h8300.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/h8300/linux.h (DOUBLE_TYPE_SIZE): Remove. (DOUBLE_TYPE_MODE): New macro. * config/loongarch/loongarch.cc (loongarch_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/loongarch/loongarch.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (LA_LONG_DOUBLE_TYPE_SIZE): ... this. (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with LA_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. * config/m68k/m68k.cc (m68k_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/m68k/m68k.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/m68k/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_MODE): New macro. * config/mips/mips.cc (mips_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. * config/mips/mips.h (UNITS_PER_FPVALUE): Replace LONG_DOUBLE_TYPE_SIZE with MIPS_LONG_DOUBLE_TYPE_SIZE. (MAX_FIXED_MODE_SIZE): Likewise. (STRUCTURE_SIZE_BOUNDARY): Likewise. (BIGGEST_ALIGNMENT): Likewise. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/mips/n32-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (MIPS_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa.cc (pa_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (pa_scalar_mode_supported_p): Rename FLOAT_TYPE_SIZE to PA_FLOAT_TYPE_SIZE, rename DOUBLE_TYPE_SIZE to PA_DOUBLE_TYPE_SIZE and rename LONG_DOUBLE_TYPE_SIZE to PA_LONG_DOUBLE_TYPE_SIZE. * config/pa/pa.h (PA_FLOAT_TYPE_SIZE): New macro. (PA_DOUBLE_TYPE_SIZE): Likewise. (PA_LONG_DOUBLE_TYPE_SIZE): Likewise. * config/pa/pa-64.h (FLOAT_TYPE_SIZE): Rename to ... (PA_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (PA_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/pa/pa-hpux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (PA_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sparc.cc (sparc_c_mode_for_floating_type): New function. (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Likewise. (LONG_DOUBLE_TYPE_SIZE): Likewise. (sparc_type_code): Replace FLOAT_TYPE_SIZE with TYPE_PRECISION of float_type_node. * config/sparc/sparc.h (FLOAT_TYPE_SIZE): Remove. (DOUBLE_TYPE_SIZE): Remove. * config/sparc/freebsd.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/linux64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/netbsd-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/openbsd64.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sol2.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/sparc/sp64-elf.h (LONG_DOUBLE_TYPE_SIZE): Rename to ... (SPARC_LONG_DOUBLE_TYPE_SIZE): ... this. * config/bfin/bfin.h (FLOAT_TYPE_SIZE): Rename to ... (BFIN_FLOAT_TYPE_SIZE): ... this. (DOUBLE_TYPE_SIZE): Rename to ... (BFIN_DOUBLE_TYPE_SIZE): ... this. (LONG_DOUBLE_TYPE_SIZE): Remove. (UNITS_PER_FLOAT): Replace FLOAT_TYPE_SIZE with BFIN_FLOAT_TYPE_SIZE. (UNITS_PER_DOUBLE): Replace DOUBLE_TYPE_SIZE with BFIN_DOUBLE_TYPE_SIZE.
2024-06-01AVR: tree-optimization/115307 - Work around isinf bloat from early passes.Georg-Johann Lay1-0/+16
PR tree-optimization/115307 gcc/ * config/avr/avr.md (SFDF): New mode iterator. (isinf<mode>2) [sf, df]: New expanders. gcc/testsuite/ * gcc.target/avr/torture/pr115307-isinf.c: New test.
2024-05-08AVR: target/114975 - Add combine-pattern for __parityqi2.Georg-Johann Lay1-1/+16
PR target/114975 gcc/ * config/avr/avr.md: Add combine pattern for 8-bit parity detection. gcc/testsuite/ * gcc.target/avr/pr114975-parity.c: New test.
2024-05-08AVR: target/114975 - Add combine-pattern for __popcountqi2.Georg-Johann Lay1-0/+13
PR target/114975 gcc/ * config/avr/avr.md: Add combine pattern for 8-bit popcount detection. gcc/testsuite/ * gcc.target/avr/pr114975-popcount.c: New test.
2024-05-06AVR: ipa/92606 - Don't optimize PROGMEM data against non-PROGMEM.Georg-Johann Lay1-0/+6
ipa/92606: Inter-procedural analysis optimizes data across address-spaces and PROGMEM. As of v14, the PROGMEM part is still not fixed (and there is still no target hook as proposed in PR92932). Just disable respective bogus optimization. PR ipa/92606 gcc/ * config/avr/avr.cc (avr_option_override): Set flag_ipa_icf_variables = 0. gcc/testsuite/ * gcc.target/avr/torture/pr92606.c: New test.
2024-04-17AVR: target/114752 - Fix ICE on inline asm const 64-bit float operandGeorg-Johann Lay1-4/+13
gcc/ PR target/114752 * config/avr/avr.cc (avr_print_operand) [CONST_DOUBLE_P]: Handle DFmode.
2024-04-15AVR: Add 8 more avrxmega3 MCUs.Georg-Johann Lay1-0/+8
gcc/ * config/avr/avr-mcus.def: Add: avr16du14, avr16du20, avr16du28, avr16du32, avr32du14, avr32du20, avr32du28, avr32du32. * doc/avr-mmcu.texi: Rebuild.
2024-03-22AVR: Adjust message for SIGNAL and INTERRUPT usageGeorg-Johann Lay1-3/+9
gcc/ * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic for deprecated SIGNAL and INTERRUPT usage without respective header.
2024-03-18avr.md - Tweak xor insn constraints.Georg-Johann Lay4-31/+72
xor insn can handle some more values without the requirement of a scratch register. This patch adds a new constraint alternative for such values. The output function avr_out_bitop already handles these cases, so no change is needed there. gcc/ * config/avr/constraints.md (CX2, CX3, CX4): New constraints. * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto. * config/avr/avr.cc (avr_xor_noclobber_dconst): New function. * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative. (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative. (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
2024-03-09AVR: Fix typos in comment, indentation glitches in avr.md.Georg-Johann Lay1-44/+43
gcc/ * config/avr/avr.md: Fix typos in comment, indentation glitches and some other nits.
2024-03-09AVR: Add cost computation for some insn combine patterns.Georg-Johann Lay2-11/+49
gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for usum_widenqihi and add_zero_extend1. [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend, sub+sign_extend. * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2): Compute exact insn lengths. (*usum_widenqihi3): Allow input operands to commute.
2024-03-08AVR: Add an insn combine pattern for offset computation.Georg-Johann Lay2-0/+44
Computing uint16_t += 2 * uint8_t can occur when an offset into a 16-bit array is computed. Without this pattern is costs six instructions: A move (1), a zero-extend (1), a shift (2) and an addition (2). With this pattern it costs 4. gcc/ * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern. * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
2024-03-06AVR: Adjust rtx cost of plus + zero_extend.Georg-Johann Lay1-0/+7
gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust rtx cost.
2024-03-05AVR: Add two RTL peepholes.Georg-Johann Lay1-3/+58
Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST because 1) the first insn may use MOVW for "X = Y", and 2) the operation may be more efficient when performed with a constant, for example when ADIW or SBIW can be used, or some bytes of the constant are 0x00 or 0xff. gcc/ * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND in HI, PSI, SI that swap operation order from "X = CST, X o= Y" to "X = Y, X o= CST".
2024-03-05AVR: Improve output of insn "*insv.any_shift.<mode>_split".Roger Sayle4-51/+244
The instructions printed by insn "*insv.any_shift.<mode>_split" were sub-optimal. The code to print the improved output is lengthy and performed by new function avr_out_insv. As it turns out, the function can also handle shift-offsets of zero, which is "*andhi3", "*andpsi3" and "*andsi3". Thus, these tree insns get a new 3-operand alternative where the 3rd operand is an exact power of 2. gcc/ * config/avr/avr-protos.h (avr_out_insv): New proto. * config/avr/avr.cc (avr_out_insv): New function. (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case. (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs. * config/avr/avr.md (define_attr "adjust_len") Add insv. (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3): Add constraint alternative where the 3rd operand is a power of 2, and the source register may differ from the destination. (*insv.any_shift.<mode>_split): Call avr_out_insv to output instructions. Set attr "length" to "insv". * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints. gcc/testsuite/ * gcc.target/avr/torture/insv-anyshift-hi.c: New test. * gcc.target/avr/torture/insv-anyshift-si.c: New test.
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