| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-12-22 | arm&aarch64: subdivide the type attribute "alu_shfit_imm" | Qian Jianhua | 1 | -2/+4 |
| 2020-09-18 | [PATCH 4/5][Arm] New pattern for CSNEG instructions | Sudi Das | 1 | -1/+15 |
| 2020-09-18 | [PATCH 3/5][Arm] New pattern for CSINC instructions | Sudi Das | 1 | -0/+19 |
| 2020-09-18 | [PATCH 2/5][Arm] New pattern for CSINV instructions | Sudi Das | 1 | -1/+15 |
| 2020-07-10 | arm: Implement Armv8.1-M low overhead loops | Andrea Corallo | 1 | -4/+45 |
| 2020-03-16 | [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. | Srinath Parvathaneni | 1 | -1/+1 |
| 2020-01-17 | [GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instruction... | Mihail Ionescu | 1 | -2/+10 |
| 2020-01-17 | [GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8... | Mihail Ionescu | 1 | -0/+16 |
| 2020-01-16 | [PATCH, GCC/ARM, 9/10] Call nscall function with blxns | Mihail Ionescu | 1 | -8/+18 |
| 2020-01-16 | [PATCH, GCC/ARM, 4/10] Clear GPR with CLRM | Mihail Ionescu | 1 | -0/+40 |
| 2020-01-01 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2019-11-14 | arm: Rename CC_NOOVmode to CC_NZmode | Richard Henderson | 1 | -17/+17 |
| 2019-10-21 | [arm] clean up alu+shift patterns | Richard Earnshaw | 1 | -27/+0 |
| 2019-10-18 | [arm] Implement negscc using SBC when appropriate. | Richard Earnshaw | 1 | -2/+6 |
| 2019-08-22 | [ARM] Cleanup logical DImode operations | Wilco Dijkstra | 1 | -97/+0 |
| 2019-07-30 | Adjust literal pool offset in Thumb-2 movsi patterns | Wilco Dijkstra | 1 | -1/+1 |
| 2019-07-25 | Fix low reg issue in Thumb-2 movsi patterns | Wilco Dijkstra | 1 | -10/+8 |
| 2019-03-02 | re PR target/89506 (ICE: in decompose, at rtl.h:2266 with -Og -g) | Jakub Jelinek | 1 | -1/+2 |
| 2019-02-27 | re PR target/70341 (cost model for addresses is incorrect, slsr is using reg ... | Jakub Jelinek | 1 | -8/+49 |
| 2019-01-01 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2018-12-14 | ARM] Improve robustness of -mslow-flash-data | Thomas Preud'homme | 1 | -10/+20 |
| 2018-02-06 | 2018-02-06 Michael Collison <michael.collison@arm.com> | Michael Collison | 1 | -2/+2 |
| 2018-01-19 | [arm] Fix gcc.target/arm/negdi-[12].c | Kyrylo Tkachov | 1 | -1/+1 |
| 2018-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2017-11-20 | [ARM] Do no clobber r4 in Armv8-M nonsecure call | Thomas Preud'homme | 1 | -10/+8 |
| 2017-11-09 | [ARM] Fix cmse_nonsecure_entry return insn size | Thomas Preud'homme | 1 | -1/+1 |
| 2017-11-06 | [Arm] Cleanup IT attributes | Wilco Dijkstra | 1 | -16/+8 |
| 2017-09-12 | [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to enco... | James Greenhalgh | 1 | -4/+4 |
| 2017-01-01 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2016-12-16 | The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn'... | Wilco Dijkstra | 1 | -26/+0 |
| 2016-12-02 | ARMv8-M Security Extension's cmse_nonsecure_call: use __gnu_cmse_nonsecure_call | Andre Vieira | 1 | -0/+28 |
| 2016-12-02 | ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers | Andre Vieira | 1 | -1/+20 |
| 2016-10-13 | [ARM] Remove redundant TARGET_VFP | Richard Earnshaw | 1 | -2/+1 |
| 2016-04-08 | [ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsl... | Kyrylo Tkachov | 1 | -2/+4 |
| 2016-02-17 | [ARM] PR target/69161: Don't ignore mode when matching comparison operator in... | Kyrylo Tkachov | 1 | -5/+5 |
| 2016-01-22 | [ARM] Fix PR target/69403: Bug in thumb2_ior_scc_strict_it pattern | Kyrylo Tkachov | 1 | -6/+18 |
| 2016-01-04 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2015-11-06 | [Patch ARM] Unified assembler in ARM state. | Ramana Radhakrishnan | 1 | -6/+6 |
| 2015-05-07 | rtl.h (always_void_p): New function. | Richard Sandiford | 1 | -41/+27 |
| 2015-04-29 | re PR target/65924 (ICE const_int_operand failed on arm-none-eabi) | Yvan Roux | 1 | -1/+1 |
| 2015-04-28 | arm.md (*arm_movt): Fix type attribute. | Yvan Roux | 1 | -17/+52 |
| 2015-01-14 | arm.c (arm_compute_save_reg_mask): Do not save lr in case of tail call. | Joey Ye | 1 | -0/+11 |
| 2015-01-05 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2014-10-29 | decl.c, [...]: Remove redundant enum from machine_mode. | Richard Sandiford | 1 | -5/+5 |
| 2014-08-07 | thumb1.md (*thumb1_movhi_insn): Handle stack pointer. | Marat Zakirov | 1 | -1/+1 |
| 2014-07-17 | types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg. | Terry Guo | 1 | -6/+6 |
| 2014-05-30 | [ARM] Use mov_imm type for movw operations consistently | Kyrylo Tkachov | 1 | -1/+1 |
| 2014-04-22 | Optimise NotDI AND/OR ZeroExtendSI for ARMv7A | Ian Bolton | 1 | -0/+24 |
| 2014-04-22 | AArch32 Support ORN for DIMode | Ian Bolton | 1 | -0/+73 |
| 2014-02-11 | [ARM] Adjust thumb2_movhi_insn pattern for -mrestrict-it. | Kyrylo Tkachov | 1 | -5/+9 |
