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AgeCommit message (Expand)AuthorFilesLines
2023-06-13arm: Extend -mtp= argumentsKyrylo Tkachov1-2/+2
2023-05-25arm: Implement ACLE Data IntrinsicsChris Sidebottom1-4/+16
2023-05-25arm: Fix ICE due to infinite splitting [PR109800]Alex Coplan1-1/+1
2023-01-23arm: Add support for dwarf debug directives and pseudo hard-register for PAC ...Srinath Parvathaneni1-0/+1
2023-01-23[PATCH 12/15] arm: implement bti injectionAndrea Corallo1-0/+7
2023-01-23[PATCH 10/15] arm: Implement cortex-M return signing address codegenAndrea Corallo1-0/+23
2023-01-13[PR40457] [arm] expand SI-aligned movdi into pair of movsiAlexandre Oliva1-2/+10
2023-01-02Update copyright years.Jakub Jelinek1-1/+1
2022-06-07arm: Improve code generation for BFI and BFC [PR105090]Richard Earnshaw1-9/+97
2022-01-21[ARM] Add support for TLS register based stack protector canary accessArd Biesheuvel1-2/+69
2022-01-17Change references of .c files to .cc filesMartin Liska1-1/+1
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-09-13arm: expand handling of movmisalign for DImode [PR102125]Richard Earnshaw1-0/+16
2021-08-24arm: fix vlldm erratum for Armv8.1-m [PR102035]Richard Earnshaw1-2/+9
2021-05-19arm: Fix ICE with CMSE nonsecure calls on Armv8.1-M [PR100333]Alex Coplan1-8/+11
2021-02-19arm: Fix ICE with -fstack-protector -mpure-code [PR98998]Jakub Jelinek1-0/+10
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-22arm&aarch64: subdivide the type attribute "alu_shfit_imm"Qian Jianhua1-13/+18
2020-09-30arm: Fix ICEs in no-literal-pool.c on MVE [PR97251]Alex Coplan1-2/+2
2020-09-25arm: Fix fp16 move patterns for base MVERichard Sandiford1-1/+3
2020-09-24arm: Fix canary address calculation for non-PICRichard Sandiford1-2/+2
2020-09-18[PATCH 4/5][Arm] New pattern for CSNEG instructionsSudi Das1-1/+1
2020-08-06arm: Clear canary value after stack_protect_test [PR96191]Richard Sandiford1-2/+4
2020-04-15[Arm] Disallow arm_movdi when targetting MVEMatthew Malcomson1-0/+1
2020-04-08[Arm] Implement scalar Custom Datapath Extension intrinsicsMatthew Malcomson1-0/+70
2020-04-07arm: MVE Don't use lsll for 32-bit shifts scalarAndre Simoes Dias Vieira1-1/+2
2020-03-24arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286]Jakub Jelinek1-3/+4
2020-03-20gcc, Arm: Fix no_cond issue introduced by MVEAndre Simoes Dias Vieira1-4/+4
2020-03-16[ARM][GCC][2/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni1-2/+6
2020-03-16[ARM][GCC][1/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni1-8/+13
2020-02-25[ARM] Fix -mpure-code for v6mChristophe Lyon1-0/+9
2020-02-21[PATCH, GCC/ARM] Fix MVE scalar shift testsMihail Ionescu1-3/+3
2020-02-10arm: correct constraints on movsi_compare0 [PR91913]Richard Earnshaw1-3/+8
2020-02-03This patch is for PR target/91816Stam Markianos-Wright1-22/+82
2020-01-30arm: Fix uaddvdi4 expander [PR93494]Jakub Jelinek1-1/+1
2020-01-17[GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instruction...Mihail Ionescu1-3/+15
2020-01-17[GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8...Mihail Ionescu1-0/+26
2020-01-16[GCC][PATCH][ARM] Add Bfloat16_t scalar type, vector types and machine modes ...Stam Markianos-Wright1-19/+19
2020-01-16[PATCH, GCC/ARM, 9/10] Call nscall function with blxnsMihail Ionescu1-6/+12
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-14arm: Rename CC_NOOVmode to CC_NZmodeRichard Henderson1-93/+93
2019-11-07[arm][6/X] Add support for __[us]sat16 intrinsicsKyrylo Tkachov1-0/+27
2019-11-07[arm][5/X] Implement Q-bit-setting SIMD32 intrinsicsKyrylo Tkachov1-0/+56
2019-11-07[arm][4/X] Add initial support for GE-setting SIMD32 intrinsicsKyrylo Tkachov1-2/+26
2019-11-07[arm][3/X] Implement __smla* intrinsics (Q-setting)Kyrylo Tkachov1-2/+134
2019-11-07[arm][2/X] Implement __qadd, __qsub, __qdbl intrinsicsKyrylo Tkachov1-0/+26
2019-11-07[arm][1/X] Add initial support for saturation intrinsicsKyrylo Tkachov1-7/+145
2019-10-31[arm] Pattern match insns for a + ~b + CarryRichard Earnshaw1-0/+35
2019-10-22[arm] Match subtraction from carry_operationRichard Earnshaw1-0/+13
2019-10-21[arm] clean up alu+shift patternsRichard Earnshaw1-87/+79