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AgeCommit message (Expand)AuthorFilesLines
2014-09-03aarch64: Improve epilogue unwind infoRichard Henderson1-182/+78
2014-09-02[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.Kyrylo Tkachov4-51/+69
2014-08-28NEXT_INSN and PREV_INSN take a const rtx_insnDavid Malcolm1-1/+1
2014-08-27re PR target/62262 (aarch64 gcc generates invalid assembler)Guozhi Wei1-1/+2
2014-08-26aarch64.c (generic_addrcost_table): Delete qi cost; add di cost.Evandro Menezes1-2/+2
2014-08-25config/aarch64/aarch64.c: Use rtx_insnDavid Malcolm1-10/+13
2014-08-15[AArch64] Move one_match > zero_match case to just before simple_sequence.Kyrylo Tkachov1-18/+18
2014-08-07remove pointer-set.[ch]Trevor Saunders2-2/+0
2014-08-07[AArch64] Restrict usage of FP/SIMD registers for TImode reload and absdi2 pa...Kyrylo Tkachov1-10/+21
2014-08-07[AArch64] Use MOVN to generate 64-bit negative immediates where sensibleIan Bolton1-13/+32
2014-08-06[PATCH AArch64] Prefer dup to zip for vec_perm_const; enable dup for bigendia...Alan Lawrence1-7/+3
2014-08-06[AArch64] Use REG_P and CONST_INT_P instead of GET_CODE + comparison.Kyrylo Tkachov1-15/+15
2014-08-05[AArch64] Fix types for vqdmlals_lane_s32 and vqdmlsls_lane_s32 intrinsics.Kyrylo Tkachov1-7/+6
2014-08-05[AArch64] Implement some saturating math NEON intrinsics.Kyrylo Tkachov3-6/+69
2014-08-05[AArch64] Implement some vmul*_lane*_f* intrinsics in arm_neon.h.Kyrylo Tkachov1-26/+42
2014-08-05[AArch64] Some aarch64-builtins.c cleanup.James Greenhalgh1-70/+29
2014-08-01Removed unused get_lane and dup_lane builtins.Alan Lawrence1-3/+0
2014-08-01[AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hookJiong Wang1-0/+15
2014-08-01[AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insnsJiong Wang4-10/+15
2014-08-01[AArch64][1/2] Fix offset glitch in load reg pair patternJiong Wang2-12/+10
2014-07-31[AArch64] arm_neon.h - add vpaddd_f64, vpaddd_s64, vpaddd_u64 intrinsicsJames Greenhalgh1-56/+59
2014-07-31[AArch64_be] Don't fold reduction intrinsics.James Greenhalgh1-0/+14
2014-07-31[AArch64_be] Fix vec_select hi/lo mask confusions.James Greenhalgh4-54/+67
2014-07-26aarch64.md (*extr_insv_lower_reg<mode>): Remove + from the read only register.Andrew Pinski1-1/+1
2014-07-24AArch64: emit .note.GNU-stackKyle McMartin1-0/+2
2014-07-24[AArch64] Optimize epilogue when there is no frame pointer.Jiong Wang1-10/+45
2014-07-24[AArch64] Optimize prologue when there is no frame pointer.Jiong Wang1-14/+44
2014-07-24[AArch64] Infrastructure to allow optional use of write back.Jiong Wang1-15/+32
2014-07-24[AArch64] Extend frame state to track WB candidates.Jiong Wang2-0/+17
2014-07-24[AArch64] Optimize epilogue in the presence of an outgoing args area.Jiong Wang1-17/+7
2014-07-23[AArch64] Simplify epilogue expansion using new helper functions.Jiong Wang2-48/+67
2014-07-23[AArch64] Simplify prologue expand using new helper functions.Jiong Wang2-35/+59
2014-07-23[AArch64] Split save restore path.Jiong Wang1-35/+69
2014-07-23[AArch64] Unify vector and core register save/restore code.Jiong Wang1-76/+24
2014-07-23[AArch64] Use helper functions to handle multiple modes.Jiong Wang1-4/+38
2014-07-23[AArch64] Refactor code out into aarch64_next_callee_saveJiong Wang1-99/+89
2014-07-23[AArch64] Hoist calculation of register rtx.Jiong Wang1-36/+18
2014-07-23[AArch64] Remove useless variable 'increment'Jiong Wang1-5/+2
2014-07-23[AArch64] Use register offset in cfun->machine->frame.reg_offsetJiong Wang1-27/+22
2014-07-23[AArch64] Remove useless parameter base_rtx.Jiong Wang1-7/+6
2014-07-23[AArch64] Remove useless local variable.Jiong Wang1-2/+1
2014-07-23[AArch64] Consistent parameter types in prologue/epilogue generation.Jiong Wang1-1/+1
2014-07-23[AArch64] GNU-Stylize some un-formatted code.Jiong Wang1-23/+27
2014-07-22[AArch64][2/2] Add rtx cost function handling of clz, clrsb, rbit.Kyrylo Tkachov1-0/+15
2014-07-22[AArch64][1/2] Remove UNSPEC_CLS and use clrsb RTL code in its' place.Kyrylo Tkachov1-2/+1
2014-07-22[AArch64] Implement vbsl_f64 arm_neon.h intrinsic.Kyrylo Tkachov1-0/+7
2014-07-17[AArch64] Implement vfma_f64, vmla_f64, vfms_f64, vmls_f64 intrinsics.Kyrylo Tkachov1-0/+28
2014-07-17[AArch64] Handle fcvta[su] and frint in RTX cost function.Kyrylo Tkachov1-7/+61
2014-07-17[AArch64] Fix argument types for some high_lane* intrinsics implemented in as...Kyrylo Tkachov1-8/+8
2014-07-17types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg.Terry Guo1-19/+19
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