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AgeCommit message (Expand)AuthorFilesLines
2018-11-07[AArch64] Add -mcpu/-mtune support for Arm AresKyrylo Tkachov2-1/+2
2018-11-06aarch64 - Set the mode for the unspec in speculation_tracker insn.Richard Earnshaw1-1/+1
2018-11-02Although there's no fundamental reason why shrink wrapping and speculation tr...Richard Earnshaw1-0/+6
2018-10-31aarch64: Remove early clobber from ATOMIC_LDOP scratchRichard Henderson1-1/+13
2018-10-31Provide extension hint for aarch64 target (PR driver/83193).Martin Liska2-17/+57
2018-10-31aarch64: Force TImode values into even registersRichard Henderson1-4/+8
2018-10-31aarch64: Improve atomic-op lse generationRichard Henderson4-272/+108
2018-10-31aarch64: Improve swp generationRichard Henderson2-47/+15
2018-10-31aarch64: Improve cas generationRichard Henderson3-44/+75
2018-10-31aarch64: Simplify LSE cas generationRichard Henderson3-119/+49
2018-10-31Add pipeline description for Qualcomm Saphira core.Sameera Deshpande3-1/+562
2018-10-30Fixes bug 87330 by invoking df_note_add_problem to recompute REG_DEAD and RE...Sameera Deshpande1-0/+1
2018-10-28Add D front-end, libphobos library, and D2 testsuite.Iain Buclaw5-0/+43
2018-10-16[AArch64] Use @ pattern to eliminate switch statement in one more placeKyrylo Tkachov2-21/+2
2018-10-12[AArch64] Support zero-extended move to FP registerWilco Dijkstra1-11/+20
2018-10-11[AArch64] Fix PR87511Wilco Dijkstra1-1/+2
2018-10-01Validate and set default parameters for stack-clash.Tamar Christina1-4/+0
2018-10-01Set default values for stack-clash and do basic validation in back-end.Tamar Christina1-0/+31
2018-10-01Ensure that outgoing argument size is at least 8 bytes when alloca and stack-...Tamar Christina2-0/+35
2018-10-01Add support for SVE stack clash probing.Tamar Christina3-5/+170
2018-10-01stack-clash: Add LR assert to layout_frame.Tamar Christina1-0/+5
2018-10-01Updated stack-clash implementation supporting 64k probes.Jeff Law3-15/+268
2018-09-24aarch64.c (aarch_macro_fusion_pair_p): Don't access prev before checking it f...Andrew Pinski1-2/+2
2018-09-21[aarch64] Add HiSilicon tsv110 CPU supportShaokun Zhang4-1/+190
2018-09-19[AARCH64] Use STLUR for atomic_storeMatthew Malcomson7-14/+59
2018-09-14[Aarch64] Added pattern to match zero extended bfxilSam Tebbs1-0/+27
2018-09-13[Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bi...Sam Tebbs4-0/+41
2018-09-13[AArch64] Add support for TARGET_COMPUTE_FRAME_LAYOUTVlad Lazar2-14/+4
2018-09-05[aarch64] Avoid tag collisions for loads falkorSiddhesh Poyarekar6-45/+946
2018-08-31[AArch64] Implement new intrinsics vabsd_s64 and vnegd_s64.Vlad Lazar1-0/+31
2018-08-30Limit movmem copies to TImode on AArch64Tamar Christina1-4/+8
2018-08-27aarch64-speculation.cc: Replace include of cfg.h with include of backend.h.Steve Ellcey1-1/+1
2018-08-27Print default options selection for -march,-mcpu and -mtune for aarch64 (PR d...Martin Liska2-6/+13
2018-08-23[AARCH64] use "arch_enabled" attribute for aarch64.Matthew Malcomson2-94/+83
2018-08-23[AArch64] Improve SVE handling of single-vector permutesRichard Sandiford1-2/+6
2018-08-23Fix aarch64_evpc_tbl guard (PR 85910)Richard Sandiford1-1/+1
2018-08-16[aarch64] Make common aarch64 options target-dependentSam Tebbs1-4/+4
2018-08-15PR tree-optimization/71625 - missing strlen optimization on different arrayMartin Sebor1-0/+4
2018-08-09aarch64 - PR target/86887 Fix missing register constraints in carryin patternsRichard Earnshaw1-4/+4
2018-08-08[AArch64] Add HXT Phecda core supportHongbo Zhang2-1/+4
2018-08-08[AArch64, Falkor] Switch to using Falkor-specific vector costs.Luis Machado1-1/+21
2018-08-08[aarch64] Adjust Falkor's sign extend reg+reg address costLuis Machado1-1/+1
2018-08-07[AArch64] Fix -mlow-precision-div (PR 86838)Richard Sandiford3-13/+8
2018-08-06Enable clobber high for tls descs on Aarch64Alan Hayward1-12/+57
2018-08-03[aarch64] Fix falkor pipeline description for dup<q>Siddhesh Poyarekar1-1/+7
2018-08-02[gen/AArch64] Generate helpers for substituting iterator values into pattern ...Richard Sandiford4-392/+53
2018-08-02[AArch64] Add support for 16-bit FMOV immediatesRichard Sandiford1-2/+2
2018-08-02re PR target/86014 ([AArch64] missed LDP optimization)Jackson Woodruff1-19/+20
2018-08-01[PATCH][AArch64] Stop redundant zero-extension after UMOV when in DI modeSam Tebbs1-15/+16
2018-07-31AArch64 - use CSDB based sequences if speculation tracking is enabledRichard Earnshaw3-0/+148
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