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path: root/gcc/config/aarch64/constraints.md
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2025-01-02Update copyright years.Jakub Jelinek1-1/+1
2024-10-25AArch64: Add more accurate constraint [PR117292]Wilco Dijkstra1-0/+6
2024-10-23AArch64: Improve SIMD immediate generation (1/3)Wilco Dijkstra1-6/+4
2024-08-12aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for Advanced SIMDKyrylo Tkachov1-0/+6
2024-08-09aarch64: Check CONSTM1_RTX in definition of Dm constraintKyrylo Tkachov1-1/+1
2024-07-31aarch64: Add support for moving fpm system registerClaudio Bantaloukas1-0/+3
2024-01-25aarch64: Fix undefinedness while testing the J constraint [PR100204]Andrew Pinski1-1/+1
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+8
2023-12-05aarch64: Add support for SME2 intrinsicsRichard Sandiford1-6/+20
2023-12-05aarch64: Add svboolx2_tRichard Sandiford1-0/+4
2023-12-05aarch64: Add support for <arm_sme.h>Richard Sandiford1-0/+9
2023-12-05aarch64: Add support for SME ZA attributesRichard Sandiford1-0/+6
2023-12-05aarch64: Use SVE's RDVL instructionRichard Sandiford1-0/+6
2023-11-09AArch64: Add special patterns for creating DI scalar and vector constant 1 <<...Tamar Christina1-0/+8
2023-08-04AArch64: Undo vec_widen_<sur>shiftl optabs [PR106346]Tamar Christina1-0/+14
2023-04-25aarch64: Leveraging the use of STP instruction for vec_duplicateVictor Do Nascimento1-1/+1
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-06AArch64: Cleanup move immediate codeWilco Dijkstra1-0/+5
2022-11-14aarch64: Add support for +csscKyrylo Tkachov1-0/+10
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-05AArch64: Fix PR103085Wilco Dijkstra1-1/+2
2021-11-03AArch64: Improve GOT addressingWilco Dijkstra1-0/+7
2021-10-20AArch64: Add pattern for sshr to cmltTamar Christina1-0/+8
2021-04-28aarch64: Fix address mode for vec_concat pattern [PR100305]Richard Sandiford1-0/+2
2021-03-23[PR99581] Use relaxed memory for more aarch64 memory constraintsVladimir N. Makarov1-6/+6
2021-03-22[PR99581] Define relaxed memory and use it for aarch64Vladimir N. Makarov1-1/+1
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-07-09aarch64: Mitigate SLS for BLR instructionMatthew Malcomson1-0/+9
2020-03-31aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]Jakub Jelinek1-0/+7
2020-01-17[AArch64] [SVE] Implement svld1ro intrinsic.Matthew Malcomson1-0/+25
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-14aarch64: Add "c" constraintRichard Henderson1-0/+4
2019-10-29[AArch64] Add support for arm_sve.hRichard Sandiford1-0/+68
2019-08-19[AArch64] Use scvtf fbits option where appropriateJoel Hutton1-0/+7
2019-08-15[AArch64] Rework SVE INC/DEC handlingRichard Sandiford1-1/+7
2019-08-15[AArch64] Use SVE binary immediate instructions for conditional arithmeticRichard Sandiford1-1/+1
2019-08-14[AArch64] Make more use of SVE conditional constant movesRichard Sandiford1-1/+7
2019-08-14[AArch64] Add support for SVE F{MAX,MIN}NM immediateRichard Sandiford1-1/+8
2019-08-14[AArch64] Add support for SVE [SU]{MAX,MIN} immediateRichard Sandiford1-3/+9
2019-08-13[AArch64] Improve SVE constant movesRichard Sandiford1-0/+6
2019-08-13[AArch64] Add a "y" constraint for V0-V7Richard Sandiford1-0/+3
2019-08-07[AArch64] Fix INSR for zero floatsRichard Sandiford1-2/+2
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-09-19[AARCH64] Use STLUR for atomic_storeMatthew Malcomson1-0/+5
2018-09-13[Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bi...Sam Tebbs1-0/+7
2018-07-19[AArch64][PATCH 1/2] Fix addressing printing of LDP/STPAndre Vieira1-13/+7
2018-04-27[AArch64] PR target/85512: Tighten SIMD right shift immediate constraints pt2Kyrylo Tkachov1-2/+2
2018-04-24[AArch64] PR target/85512: Tighten SIMD right shift immediate constraintsKyrylo Tkachov1-0/+14
2018-02-01[PR83370][AARCH64]Use tighter register constraint for sibcall patterns.Renlin Li1-2/+2
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