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path: root/gcc/config/aarch64/aarch64.md
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2021-03-31aarch64: Fix up *add<mode>3_poly_1 [PR99813]Jakub Jelinek1-2/+2
2021-03-30aarch64: PR target/99822 Don't allow zero register in first operand of SUBS/A...Kyrylo Tkachov1-1/+1
2021-03-30aarch64: Tweak post-RA handling of CONST_INT moves [PR98136]Richard Sandiford1-4/+13
2021-03-30aarch64: Prevent use of SIMD fcvtz[su] instruction variant with "nosimd"Mihailo Stojanovic1-1/+2
2021-02-25aarch64 : Mark rotate immediates with '#' as per DDI0487iFc.Iain Sandoe1-2/+2
2021-02-22aarch64: Add internal tune flag to minimise VL-based scalar opsKyrylo Tkachov1-0/+8
2021-02-01aarch64: Reimplement vrshrn* intrinsics using builtinsKyrylo Tkachov1-0/+1
2021-02-01aarch64: Reimplement vabdl_* intrinsics using builtinsKyrylo Tkachov1-0/+2
2021-01-29aarch64: Re-implement vabal_high* intrinsics using builtinsKyrylo Tkachov1-0/+2
2021-01-27aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]Jakub Jelinek1-2/+2
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-22arm&aarch64: subdivide the type attribute "alu_shfit_imm"Qian Jianhua1-6/+6
2020-12-09aarch64: Add +pauth to -marchPrzemyslaw Wirkus1-1/+1
2020-11-13aarch64: Add backend support for expanding __builtin_memsetSudakshina Das1-0/+18
2020-11-05Move and adjust PROBE_STACK reg definitions for aarch64Olivier Hainque1-0/+7
2020-09-30aarch64: Tweak movti and movtf patternsRichard Sandiford1-8/+9
2020-09-23aarch64: Prevent canary address being spilled to stackRichard Sandiford1-49/+36
2020-09-07aarch64: Remove redundant mult patternsAlex Coplan1-271/+0
2020-09-07aarch64: Don't emit invalid zero/sign-extend syntaxAlex Coplan1-12/+12
2020-08-05aarch64: Clear canary value after stack_protect_test [PR96191]Richard Sandiford1-19/+15
2020-08-05aarch64: Add missing %z prefixes to LDP/STP patternsRichard Sandiford1-13/+13
2020-08-04aarch64: Add missing clobber for fjcvtzsAndrea Corallo1-1/+2
2020-07-09aarch64: Mitigate SLS for BLR instructionMatthew Malcomson1-6/+5
2020-07-09aarch64: Introduce SLS mitigation for RET and BR instructionsMatthew Malcomson1-18/+58
2020-07-01aarch64: Add 64 bit setter getter fpsr fpcrAndrea Corallo1-25/+9
2020-05-11aarch64: Fix ICE when expanding scalar floating move with -mgeneral-regs-only...Fei Yang1-1/+5
2020-05-11[PATCH] aarch64: prefer using csinv, csneg in zero extend contextsAlex Coplan1-0/+38
2020-05-05aarch64: eliminate redundant zero extend after bitwise negationAlex Coplan1-0/+9
2020-04-28aarch64: Add TX3 machine modelAnton Youdkevitch1-0/+1
2020-03-18aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201]Duan bo1-6/+16
2020-02-12[AArch64] Improve popcount expansionWilco Dijkstra1-3/+1
2020-02-06aarch64: Add a type attribute to aarch64_movk<mode>Richard Sandiford1-0/+1
2020-02-06aarch64: Add an and/ior-based movk pattern [PR87763]Richard Sandiford1-0/+17
2020-02-06aarch64: Add an extra sbfiz pattern [PR87763]Richard Sandiford1-0/+15
2020-01-23aarch64: Fix -mtrack-speculation for irreversible conditions [PR93341]Richard Sandiford1-0/+15
2020-01-22Fix target/93119 (aarch64): ICE with traditional TLS support on ILP32Andrew Pinski1-4/+4
2020-01-17[AArch64] [SVE] Implement svld1ro intrinsic.Matthew Malcomson1-0/+1
2020-01-17aarch64: Don't raise FE_INVALID for -__builtin_isgreater [PR93133]Richard Sandiford1-19/+45
2020-01-10config.gcc: Add arm_bf16.h.Stam Markianos-Wright1-7/+7
2020-01-09[AArch64] Add support for the SVE2 ACLERichard Sandiford1-0/+6
2020-01-09[AArch64] Rename UNSPEC_WHILE* to match instruction mnemonicsRichard Sandiford1-4/+4
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-19[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsicsDennis Zhang1-0/+90
2019-11-18Add optabs for accelerating RAW and WAR alias checksRichard Sandiford1-0/+2
2019-10-29[AArch64] Add support for the SVE PCSRichard Sandiford1-1/+1
2019-10-29[AArch64] Add support for arm_sve.hRichard Sandiford1-0/+20
2019-10-29[AArch64] Add FFR and FFRT registersRichard Sandiford1-0/+4
2019-10-21[AArch64] Implement __rndr, __rndrrs intrinsicsKyrylo Tkachov1-0/+22
2019-10-01[AArch64] Use calls for SVE TLSDESCRichard Sandiford1-58/+16
2019-10-01[AArch64] Make call insns record the callee's arm_pcsRichard Sandiford1-26/+39
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