aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/aarch64.c
AgeCommit message (Expand)AuthorFilesLines
2020-04-29diagnostics: Add %{...%} pretty-format support for URLs and use it in -Wpsabi...Jakub Jelinek1-2/+6
2020-04-29aarch64: Fix parameter passing for [[no_unique_address]]Richard Sandiford1-53/+106
2020-04-28aarch64: Add TX3 machine modelAnton Youdkevitch1-0/+83
2020-04-23[AArch64] (PR94383) Avoid C++17 empty base field checking for HVA/HFAMatthew Malcomson1-7/+46
2020-04-21aarch64: Add an error message in large code model for ilp32 [PR94577]XieZhiheng1-23/+28
2020-04-20aarch64: Fix vector builds used by SVE vec_init [PR94668]Richard Sandiford1-7/+19
2020-04-17aarch64: Tweak SVE load/store costsRichard Sandiford1-4/+73
2020-04-16aarch64: Fix mismatched SVE predicate modes [PR94606]Richard Sandiford1-0/+1
2020-04-09aarch64: Add support for arm_sve_vector_bitsRichard Sandiford1-168/+661
2020-04-09aarch64: Add a separate "SVE sizeless type" attributeRichard Sandiford1-0/+1
2020-04-02aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]Jakub Jelinek1-1/+4
2020-03-18aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201]Duan bo1-2/+15
2020-03-18aarch64: Treat p12-p15 as call-preserved in SVE PCS functionsRichard Sandiford1-7/+24
2020-03-17Fix up duplicated duplicated words mostly in commentsJakub Jelinek1-1/+1
2020-03-13aarch64: Fix another bug in aarch64_add_offset_1 [PR94121]Jakub Jelinek1-1/+2
2020-03-13aarch64: Add --params to control the number of recip steps [PR94154]Bu Le1-3/+5
2020-03-11aarch64: Fix ICE in aarch64_add_offset_1 [PR94121]Jakub Jelinek1-1/+1
2020-02-28Fix misleading aarch64 mcpu/march warning stringJoel Hutton1-2/+2
2020-02-25Fix typo: paramter -> parameter [PR93864]Jakub Jelinek1-1/+1
2020-02-21aarch64: Add SVE support for -mlow-precision-sqrtRichard Sandiford1-17/+41
2020-02-21aarch64: Add SVE support for -mlow-precision-divRichard Sandiford1-3/+26
2020-02-21aarch64: Avoid creating an unused registerRichard Sandiford1-7/+10
2020-02-21aarch64: Fix inverted approx_sqrt conditionRichard Sandiford1-1/+1
2020-02-12[AArch64] Set ctz rtx_cost (PR93565)Wilco Dijkstra1-0/+7
2020-02-06aarch64: Add an and/ior-based movk pattern [PR87763]Richard Sandiford1-0/+24
2020-01-31aarch64: Add svbfloat16_t support to arm_sve.hRichard Sandiford1-1/+7
2020-01-27aarch64: Fix failure in cmpimm_branch_1.cRichard Sandiford1-2/+13
2020-01-22aarch64: Fix aarch64_expand_subvti constant handling [PR93335]Jakub Jelinek1-6/+7
2020-01-22Fix target/93119 (aarch64): ICE with traditional TLS support on ILP32Andrew Pinski1-4/+13
2020-01-21[AArch64] PR92424: Fix -fpatchable-function-entry=N,M with BTISzabolcs Nagy1-0/+31
2020-01-20[AArch64] Set jump-align=4 for neoversen1Wilco Dijkstra1-1/+1
2020-01-17[AArch64] [SVE] Implement svld1ro intrinsic.Matthew Malcomson1-4/+22
2020-01-17[AArch64] Enable compare branch fusionWilco Dijkstra1-2/+2
2020-01-17[AArch64] Fix shrinkwrapping interactions with atomics (PR92692)Wilco Dijkstra1-0/+6
2020-01-17aarch64: Don't raise FE_INVALID for -__builtin_isgreater [PR93133]Richard Sandiford1-10/+20
2020-01-16aarch64: Fix BE SVE mode punning involving floatsRichard Sandiford1-2/+2
2020-01-10aarch64.c (aarch64_invalid_conversion): New function for target hook.Stam Markianos-Wright1-0/+58
2020-01-10config.gcc: Add arm_bf16.h.Stam Markianos-Wright1-2/+17
2020-01-10[AArch64] Make -msve-vector-bits=128 generate VL-specific codeRichard Sandiford1-6/+14
2020-01-10[AArch64] Fix reversed vcond_mask invocation in aarch64_evpc_selRichard Sandiford1-1/+3
2020-01-09[AArch64] Pass a mode to some SVE immediate queriesRichard Sandiford1-17/+11
2020-01-09[AArch64] Rename UNSPEC_WHILE* to match instruction mnemonicsRichard Sandiford1-1/+1
2020-01-09Add a compatible_vector_types_p target hookRichard Sandiford1-0/+12
2020-01-07[AArch64] Use type attributes to mark types that use the SVE PCSRichard Sandiford1-29/+7
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-12-19[AArch64] Fix handling of npatterns>1 constants for partial SVE modesRichard Sandiford1-3/+19
2019-12-19[AArch64] Reject invalid subregs involving partial SVE modesRichard Sandiford1-3/+22
2019-12-19[AArch64] Handle arguments and return types with partial SVE modesRichard Sandiford1-20/+75
2019-12-10[AArch64] Don't allow partial SVE modes in GPRsRichard Sandiford1-1/+3
2019-12-04[AArch64] Add support for fused compare and branchWilco Dijkstra1-7/+17
generated by cgit v1.1 at 2025-03-04 17:33:43 +0000