aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/aarch64.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-17Rename .c files to .cc files.Martin Liska1-26861/+0
2022-01-12Fix -Wformat-diag for aarch64 target.Martin Liska1-13/+13
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-15aarch64: Don't classify vector pairs as short vectors [PR103094]Richard Sandiford1-2/+17
2021-12-14aarch64: Add LS64 extension and intrinsicsPrzemyslaw Wirkus1-0/+4
2021-12-13aarch64: Use +mops to inline memset operationsKyrylo Tkachov1-19/+74
2021-12-13aarch64: Add support for Armv8.8-a memory operations and memcpy expansionKyrylo Tkachov1-9/+53
2021-12-02AArch64: Optimize right shift rounding narrowingTamar Christina1-0/+12
2021-11-17aarch64: Add new vector mode V8DIPrzemyslaw Wirkus1-0/+4
2021-11-12aarch64: Remove redundant costing codeRichard Sandiford1-112/+30
2021-11-12aarch64: Use new hooks for vector comparisonsRichard Sandiford1-146/+145
2021-11-12aarch64: Add vf_factor to aarch64_vec_op_countRichard Sandiford1-6/+24
2021-11-12aarch64: Move cycle estimation into aarch64_vec_op_countRichard Sandiford1-98/+105
2021-11-12aarch64: Use an array of aarch64_vec_op_countsRichard Sandiford1-55/+60
2021-11-12aarch64: Use real scalar op countsRichard Sandiford1-94/+88
2021-11-12aarch64: Get floatness from stmt_infoRichard Sandiford1-2/+12
2021-11-12aarch64: Remove vectype from latency testsRichard Sandiford1-20/+13
2021-11-12aarch64: Fold aarch64_sve_op_count into aarch64_vec_op_countRichard Sandiford1-57/+96
2021-11-12aarch64: Detect more consecutive MEMsRichard Sandiford1-52/+104
2021-11-11[aarch64] PR102376 - Emit better diagnostic for arch extensions in target attr.Prathamesh Kulkarni1-1/+12
2021-11-10vect: Pass scalar_costs to finish_costRichard Sandiford1-3/+3
2021-11-10aarch64: [PR101529] Fix vector shuffle insertion expansionAndrew Pinski1-2/+1
2021-11-08aarch64: LD3/LD4 post-modify costs for struct modesRichard Sandiford1-2/+20
2021-11-05AArch64: Fix PR103085Wilco Dijkstra1-1/+3
2021-11-04aarch64: Pass and return Neon vector-tuple types without a parallelJonathan Wright1-0/+12
2021-11-04aarch64: Add machine modes for Neon vector-tuple typesJonathan Wright1-36/+168
2021-11-04aarch64: Move Neon vector-tuple type declaration into the compilerJonathan Wright1-1/+1
2021-11-04aarch64: Move more code into aarch64_vector_costsRichard Sandiford1-184/+155
2021-11-04vect: Convert cost hooks to classesRichard Sandiford1-85/+52
2021-11-03aarch64: enable Ampere-1 CPUPhilipp Tomsich1-0/+78
2021-11-03AArch64: Improve GOT addressingWilco Dijkstra1-42/+8
2021-11-01AArch64: Add better costing for vector constants and operationsTamar Christina1-4/+34
2021-11-01aarch64: Fix redundant check in aut insn generationDan Li1-5/+1
2021-10-20Revert "target: Support whitespaces in target attr/pragma."Martin Liska1-1/+0
2021-10-20AArch64: Tune case-values-thresholdWilco Dijkstra1-3/+3
2021-10-20AArch64: Enable fast shifts on Neoverse V1/N2Wilco Dijkstra1-2/+3
2021-10-20[Patch][GCC][AArch64] - Lower store and load neon builtins to gimpleAndre Simoes Dias Vieira1-1/+1
2021-10-19target: Support whitespaces in target attr/pragma.Martin Liska1-0/+1
2021-10-14aarch64: Remove redundant flag_vect_cost_model testRichard Sandiford1-109/+105
2021-09-29aarch64: Improve size heuristic for cpymem expansionKyrylo Tkachov1-11/+25
2021-09-29aarch64: Improve size optimisation heuristic for setmem expansionKyrylo Tkachov1-13/+18
2021-09-13c++: implement C++17 hardware interference sizeJason Merrill1-0/+22
2021-09-13aarch64: PR target/102252 Invalid addressing mode for SVE load predicateKyrylo Tkachov1-4/+5
2021-09-08Support -fexcess-precision=16 which will enable FLT_EVAL_METHOD_PROMOTE_TO_FL...liuhongt1-0/+1
2021-09-01Fix target/101934: aarch64 memset code creates unaligned stores for -mstrict-...Andrew Pinski1-2/+2
2021-08-17aarch64: Replace some uses of GET_CODE with RTL predicate macrosAlistair Lee1-14/+14
2021-08-05vect: Move costing helpers from aarch64 codeRichard Sandiford1-111/+14
2021-08-05aarch64: Don't include vec_select high-half in SIMD subtract costJonathan Wright1-0/+15
2021-08-05aarch64: Don't include vec_select high-half in SIMD add costJonathan Wright1-0/+15
2021-08-04aarch64: Don't include vec_select high-half in SIMD multiply costJonathan Wright1-0/+22
generated by cgit v1.1 at 2024-09-28 02:01:16 +0000