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path: root/gcc/config/aarch64/aarch64-sve.md
AgeCommit message (Expand)AuthorFilesLines
2019-01-09[Aarch64][SVE] Add copysign and xorsign supportAlejandro Martinez1-0/+54
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-12-20[AArch64][SVE] Fix IFN_COND_FMLA movprfx alternativeRichard Sandiford1-1/+1
2018-12-07[AArch64][SVE] Remove unnecessary PTRUEs from integer arithmeticRichard Sandiford1-4/+38
2018-12-07[AArch64][SVE] Remove unnecessary PTRUEs from FP arithmeticRichard Sandiford1-6/+33
2018-07-12Add IFN_COND_FMA functionsRichard Sandiford1-0/+95
2018-07-02aarch64: Add movprfx patterns alternativesRichard Henderson1-131/+349
2018-05-25Add IFN_COND_{MUL,DIV,MOD,RDIV}Richard Sandiford1-0/+41
2018-05-25[AArch64] Add SVE support for integer divisionRichard Sandiford1-0/+30
2018-05-25Fold VEC_COND_EXPRs to IFN_COND_* where possibleRichard Sandiford1-2/+33
2018-05-25Add an "else" argument to IFN_COND_* functionsRichard Sandiford1-8/+46
2018-05-08[AArch64] Predicated SVE comparison foldsRichard Sandiford1-0/+120
2018-05-08[AArch64] Use UNSPEC_MERGE_PTRUE for comparisonsRichard Sandiford1-30/+50
2018-03-13[SLP/AArch64] Fix unpack handling for big-endian SVERichard Sandiford1-40/+76
2018-03-13[AArch64] Add SVE mul_highpart patternsRichard Sandiford1-0/+28
2018-02-01[AArch64] Handle SVE subregs that are effectively REVsRichard Sandiford1-0/+26
2018-02-01[AArch64] Use all SVE LD1RQ variantsRichard Sandiford1-5/+5
2018-01-30[AArch64] Fix sve/extract_[12].c for big-endian SVERichard Sandiford1-3/+37
2018-01-13Add support for SVE scatter storesRichard Sandiford1-0/+57
2018-01-13Add support for SVE gather loadsRichard Sandiford1-0/+57
2018-01-13Add support for in-order addition reduction using SVE FADDARichard Sandiford1-0/+39
2018-01-13Add support for conditional reductions using SVE CLASTBRichard Sandiford1-0/+15
2018-01-13Add support for vectorising live-out values using SVE LASTBRichard Sandiford1-5/+3
2018-01-13Add support for reductions in fully-masked loopsRichard Sandiford1-0/+24
2018-01-13Add support for bitwise reductionsRichard Sandiford1-0/+20
2018-01-13SLP reductions with variable-length vectorsRichard Sandiford1-0/+13
2018-01-13[AArch64] SVE load/store_lanes supportRichard Sandiford1-0/+153
2018-01-13[AArch64] Add SVE supportRichard Sandiford1-0/+1922
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