| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2013-05-23 | [AArch64] Support for CLZ | Vidya Praveen | 1 | -0/+9 |
| 2013-05-23 | [AArch64] Fix possible wrong code generation when comparing DImode values. | James Greenhalgh | 1 | -32/+10 |
| 2013-05-14 | [AArch64] Fix vcond where comparison and result have different types. | James Greenhalgh | 1 | -30/+30 |
| 2013-05-13 | aarch64-simd.md (aarch64_simd_mov<mode>): Group similar switch cases. | Sofiane Naci | 1 | -60/+46 |
| 2013-05-07 | aarch64-simd.md (*aarch64_simd_mov<mode>): call splitter. | Sofiane Naci | 1 | -3/+115 |
| 2013-05-03 | [AArch64] Correct simd_fabd comment text. | Vidya Praveen | 1 | -1/+1 |
| 2013-05-03 | [AArch64] Support scalar FABD | Vidya Praveen | 1 | -0/+11 |
| 2013-05-01 | [AArch64] Refactor reduc_<su>plus patterns. | James Greenhalgh | 1 | -121/+35 |
| 2013-05-01 | [AArch64] Refactor vector max and min RTL and builtins. | James Greenhalgh | 1 | -47/+47 |
| 2013-05-01 | [AArch64] Add combiner patterns for FAC instructions | James Greenhalgh | 1 | -0/+17 |
| 2013-05-01 | [AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}. | James Greenhalgh | 1 | -18/+69 |
| 2013-05-01 | [AArch64] Improve description of <F>CM instructions in RTL | James Greenhalgh | 1 | -26/+159 |
| 2013-04-29 | [AArch64] Add vector fix, fixuns, fix_trunc, fixuns_trunc standard patterns | James Greenhalgh | 1 | -0/+23 |
| 2013-04-29 | [AArch64] Implement vector float->double widening and double->float narrowing. | James Greenhalgh | 1 | -0/+102 |
| 2013-04-29 | [AArch64] Add vector int to float conversions. | James Greenhalgh | 1 | -0/+10 |
| 2013-04-29 | [AArch64] Map fcvt intrinsics to builtin name directly. | James Greenhalgh | 1 | -11/+3 |
| 2013-04-29 | [AArch64] Fix order of modes to lroundmn2 standard names. | James Greenhalgh | 1 | -1/+1 |
| 2013-04-29 | [AArch64] Map frint intrinsics to standard pattern names directly. | James Greenhalgh | 1 | -10/+3 |
| 2013-04-25 | [AArch64] Describe the 'BSL' RTL pattern more accurately. | James Greenhalgh | 1 | -17/+31 |
| 2013-04-25 | [AArch64] Change iterator for neg<mode>2 from VDQM to VDQ. | James Greenhalgh | 1 | -2/+2 |
| 2013-04-25 | [AArch64] Implement TARGET_GIMPLE_FOLD_BUILTIN for aarch64 backend. | James Greenhalgh | 1 | -5/+15 |
| 2013-04-22 | [AArch64] Map standard pattern names to NEON intrinsics directly. | James Greenhalgh | 1 | -67/+0 |
| 2013-04-22 | [AArch64] Support vrecp<esx> neon intrinsics in RTL. | James Greenhalgh | 1 | -8/+30 |
| 2013-04-11 | [PATCH, AARCH64] Fix unrecognizable insn issue with vcond against 0.0f | James Greenhalgh | 1 | -5/+29 |
| 2013-03-21 | aarch64-simd.md (simd_fabd): New Attribute. | Naveen H.S | 1 | -0/+36 |
| 2013-01-25 | aarch64-simd-builtins.def: Separate sq<r>dmulh_lane entries into lane and lan... | Tejas Belagod | 1 | -6/+38 |
| 2013-01-18 | [AArch64] Fix unordered comparisons to floating-point vcond. | James Greenhalgh | 1 | -9/+100 |
| 2013-01-14 | aarch64-simd.md (*aarch64_simd_ld1r<mode>): New. | Tejas Belagod | 1 | -0/+8 |
| 2013-01-10 | Update copyright years in gcc/ | Richard Sandiford | 1 | -1/+1 |
| 2013-01-08 | aarch64-simd.md (vec_init<mode>): New. | Tejas Belagod | 1 | -0/+11 |
| 2013-01-08 | aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>, [...]): Separate instru... | Tejas Belagod | 1 | -2/+2 |
| 2013-01-08 | [AARCH64] Add support for floating-point vcond. | James Greenhalgh | 1 | -18/+85 |
| 2013-01-07 | [AARCH64] Add support for vector and scalar floating-point immediate loads. | James Greenhalgh | 1 | -61/+15 |
| 2012-12-05 | [AARCH64] Add zip{1, 2}, uzp{1, 2}, trn{1, 2} support | James Greenhalgh | 1 | -1/+14 |
| 2012-12-05 | [AARCH64] Implement Vector Permute Support. | James Greenhalgh | 1 | -0/+68 |
| 2012-12-05 | [AARCH64] Add support for vectorizable standard math patterns. | James Greenhalgh | 1 | -0/+40 |
| 2012-10-30 | 2012-10-30 James Greenhalgh <james.greenhalgh@arm.com> | James Greenhalgh | 1 | -0/+144 |
| 2012-10-23 | AArch64 [3/10] | Ian Bolton | 1 | -0/+3264 |
