aboutsummaryrefslogtreecommitdiff
path: root/gcc/config.gcc
AgeCommit message (Collapse)AuthorFilesLines
2018-03-05Enable WBOINVD and PCONFIG instructions.Olga Makhotina1-2/+4
2018-03-05 Olga Makhotina <olga.makhotina@intel.com> Enable WBOINVD and PCONFIG instructions. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_SET, OPTION_MASK_ISA_WBNOINVD_UNSET): New definitions. (ix86_handle_option): Handle -mpconfig and -mwbnoinvd. * config.gcc (pconfigintrin.h, wbnoinvdintrin.h) : Add headers. * config/i386/cpuid.h (bit_PCONFIG, bit_WBNOINVD): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mpconfig and -mwbnoinvd. * config/i386/i386-builtin.def (__builtin_ia32_wbnoinvd, __builtin_ia32_wbinvd): New builtins. (SPECIAL_ARGS2): New. * config/i386/i386-c.c (__WBNOINVD__, __PCONFIG__): New. (SPECIAL_ARGS2): New. * config/i386/i386.c (ix86_target_string): Add -mpconfig and -mwbnoinvd. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_init_mmx_sse_builtins): Add special_args2. * config/i386/i386.h (TARGET_PCONFIG, TARGET_PCONFIG_P, TARGET_WBNOINVD, TARGET_WBNOINVD_P): New. * config/i386/i386.md (UNSPECV_WBINVD, UNSPECV_WBNOINVD): New. (define_insn "wbinvd", define_insn "wbnoinvd"): New. * config/i386/i386.opt: Add -mpconfig and -mwbnoinvd. * config/i386/immintrin.h (_wbinvd): New intrinsic. * config/i386/pconfigintrin.h: New file. * config/i386/wbnoinvdintrin.h: Ditto. * config/i386/x86intrin.h: Add headers pconfigintrin.h and wbnoinvdintrin.h. * doc/invoke.texi (-mpconfig, -mwbnoinvd): New. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpconfig and -mwbnoinvd. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-23.c: Add pconfig and wbnoinvd. * gcc.target/i386/wbinvd-1.c: New test. * gcc.target/i386/wbnoinvd-1.c: Ditto. * gcc.target/i386/pconfig-1.c: Ditto. From-SVN: r258247
2018-02-28config.gcc (powerpc-ibm-aix7.1.*): New stanza.David Edelsohn1-1/+11
* config.gcc (powerpc-ibm-aix7.1.*): New stanza. (powerpc-ibm-aix[789]*): Default to AIX 7.2. * config/rs6000/aix71.h (TARGET_DEFAULT): Revert to Power4 ISA. * config/rs6000/aix72.h: New file. From-SVN: r258082
2018-02-26[NDS32] Basic support for -mcpu= and --with-cpu= options.Kito Cheng1-1/+14
gcc/ * config.gcc: Add --with-cpu support for nds32 target. * config/nds32/nds32-opts.h(nds32_cpu_type): New. * config/nds32/nds32.opt: Add -mcpu= option. From-SVN: r257982
2018-02-02Add -march=icelake.Julia Koval1-1/+1
gcc/ * config.gcc: Add -march=icelake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake. * config/i386/i386.c (processor_costs): Add m_ICELAKE. (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2, PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New. (processor_target_table): Add icelake. (ix86_option_override_internal): Handle new PTAs. (get_builtin_code_for_version): Handle icelake. (M_INTEL_COREI7_ICELAKE): New. (fold_builtin_cpu): Handle icelake. * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New. * doc/invoke.texi: Add -march=icelake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.dg/ext/mv16.C: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE. From-SVN: r257331
2018-01-17config.gcc (powerpc*-linux*-*): Add support for 64-bit little endian Linux ↵Michael Meissner1-0/+10
systems to optionally enable... 2018-01-16 Michael Meissner <meissner@linux.vnet.ibm.com> * config.gcc (powerpc*-linux*-*): Add support for 64-bit little endian Linux systems to optionally enable multilibs for selecting the long double type if the user configured an explicit type. * config/rs6000/rs6000.h (TARGET_IEEEQUAD_MULTILIB): Indicate we have no long double multilibs if not defined. * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not warn if the user used -mabi={ieee,ibm}longdouble and we built multilibs for long double. * config/rs6000/linux64.h (MULTILIB_DEFAULTS_IEEE): Define as the appropriate multilib option. (MULTILIB_DEFAULTS): Add MULTILIB_DEFAULTS_IEEE to the default multilib options. * config/rs6000/t-ldouble-linux64le-ibm: New configuration files for building long double multilibs. * config/rs6000/t-ldouble-linux64le-ieee: Likewise. From-SVN: r256775
2018-01-17config.gcc (hppa*-*-linux*): Change callee copies ABI to caller copies.John David Anglin1-1/+1
* config.gcc (hppa*-*-linux*): Change callee copies ABI to caller copies. From-SVN: r256774
2018-01-14config.gcc (i[34567]86-*-*): Remove one duplicate gfniintrin.h entry from ↵Jakub Jelinek1-6/+4
extra_headers. * config.gcc (i[34567]86-*-*): Remove one duplicate gfniintrin.h entry from extra_headers. (x86_64-*-*): Remove two duplicate gfniintrin.h entries from extra_headers, make the list bitwise identical to the i?86-*-* one. From-SVN: r256667
2018-01-12Set use_gcc_stdint=wrap for nvptxTom de Vries1-0/+1
2018-01-12 Tom de Vries <tom@codesourcery.com> PR target/83737 * config.gcc (nvptx*-*-*): Set use_gcc_stdint=wrap. From-SVN: r256591
2018-01-11configure.ac (--with-long-double-format): Add support for the configuration ↵Michael Meissner1-0/+8
option to change the default long double... 2018-01-11 Michael Meissner <meissner@linux.vnet.ibm.com> * configure.ac (--with-long-double-format): Add support for the configuration option to change the default long double format on PowerPC systems. * config.gcc (powerpc*-linux*-*): Likewise. * configure: Regenerate. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If long double is IEEE, define __KC__ and __KF__ to allow floatn.h to be used without modification. From-SVN: r256558
2018-01-05RTEMS/EPIPHANY: Add RTEMS supportSebastian Huber1-4/+12
gcc/ * config.gcc (epiphany-*-elf*): Add (epiphany-*-rtems*) configuration. * config/epiphany/rtems.h: New file. libgcc/ * config.host (epiphany-*-elf*): Add (epiphany-*-rtems*) configuration. From-SVN: r256273
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
From-SVN: r256169
2017-12-22Enable AVX512BITALGJulia Koval1-2/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET, OPTION_MASK_ISA_AVX512BITALG_UNSET): New. (ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting. * config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16, _mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16, _mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8, _mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8, _mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16, _mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask, _mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8, _mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8, _mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics. * config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64, _mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32, _mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64, _mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64, _mm256_maskz_popcnt_epi64): New intrinsics. * config/i386/cpuid.h (bit_AVX512BITALG): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI, V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI, V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types. * config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di, __builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di, __builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si, __builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si, __builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi, __builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi, __builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi, __builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi, __builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi, __builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask, __builtin_ia32_vpshufbitqmb256_mask, __builtin_ia32_vpshufbitqmb512_mask): New builtins. * config/i386/i386-c.c (__AVX512BITALG__): New. * config/i386/i386.c (isa2_opts): Add -mavx512bitalg. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_expand_args_builtin): Handle new types. * config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New. * config/i386/i386.opt: Add -mavx512bitalg. * config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h. * config/i386/sse.md (VI48_AVX512VLBW): New iterator. (vpopcount<mode><mask_name>): Add more types. (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New. * doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq. gcc/testsuite/ * g++.dg/other/i386-2.C: Add new options. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG. * gcc.target/i386/avx512bitalg-vpopcntb-1.c: New. * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto. * gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New. * gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types. * gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics. * gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto. * gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto. Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com> From-SVN: r255975
2017-12-20[arm] PR target/83105: Minor change of default CPU for arm-linux-gnueabiRichard Earnshaw1-1/+6
When GCC for ARM/linux is configured with --with-float=hard, or --with-float=softfp the compiler will now die when trying to build the support libraries because the baseline architecture is too old to support VFP (older versions of GCC just emitted the VFP instructions anyway, even though they wouldn't run on that version of the architecture; but we're now more prickly about it). This patch fixed the problem by raising the default architecture (actually the default CPU) to ARMv5te (ARM10e) when we need to generate HW floating-point code. PR target/83105 * config.gcc (arm*-*-linux*): When configured with --with-float=hard or --with-float=softfp, set the default CPU to arm10e. From-SVN: r255858
2017-12-20Enable VPCLMULQDQ supportJulia Koval1-2/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET, OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New. (ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2. * config.gcc: Include vpclmulqdqintrin.h. * config/i386/cpuid.h: Handle bit_VPCLMULQDQ. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -mvpclmulqdq. * config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di, __builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New. * config/i386/i386-c.c (__VPCLMULQDQ__): New. * config/i386/i386.c (isa2_opts): Add -mcx16. (isa_opts): Add -mpclmulqdq, remove -mcx16. (ix86_option_override_internal): Move mcx16 to flags2. (ix86_valid_target_attribute_inner_p): Add vpclmulqdq. (ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ. * config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New. * config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2. * config/i386/immintrin.h: Include vpclmulqdqintrin.h. * config/i386/sse.md (vpclmulqdq_<mode>): New pattern. * config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128, _mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics. * doc/invoke.texi: Add -mvpclmulqdq. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx512-check.h: Handle bit_VPCLMULQDQ. * gcc.target/i386/avx512f-vpclmulqdq-2.c: New test. * gcc.target/i386/avx512vl-vpclmulqdq-2.c: Ditto. * gcc.target/i386/vpclmulqdq.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_vpclmulqdq): New. From-SVN: r255850
2017-12-12Enable VAES support [2/5]Julia Koval1-2/+2
gcc/ * config.gcc: Add vaesintrin.h. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type. * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi, __builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins. * config/i386/i386.c (ix86_expand_args_builtin): Handle new type. * config/i386/immintrin.h: Include vaesintrin.h. * config/i386/sse.md (vaesdec_<mode>): New pattern. * config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128, _mm_aesdec_epi128): New intrinsics. gcc/testsuite/ * gcc.target/i386/avx512-check.h: Handle bit_VAES. * gcc.target/i386/avx512f-aesdec-2.c: New test. * gcc.target/i386/avx512fvl-vaes-1.c: Ditto. * gcc.target/i386/avx512vl-aesdec-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New. From-SVN: r255572
2017-12-07Enable VAES support [2/5]Julia Koval1-2/+4
gcc/ * config.gcc: Add vaesintrin.h. * config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type. * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi, __builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins. * config/i386/i386.c (ix86_expand_args_builtin): Handle new type. * config/i386/immintrin.h: Include vaesintrin.h. * config/i386/sse.md (vaesdec_<mode>): New pattern. * config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128, _mm_aesdec_epi128): New intrinsics. gcc/testsuite/ * gcc.target/i386/avx512-check.h: Handle bit_VAES. * gcc.target/i386/avx512f-aesdec-2.c: New test. * gcc.target/i386/avx512fvl-vaes-1.c: Ditto. * gcc.target/i386/avx512vl-aesdec-2.c: Ditto. * gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New. From-SVN: r255461
2017-11-26i386.c (processor_target_table): Add skylake_cost for skylake-avx512.Uros Bizjak1-1/+1
* config/i386/i386.c (processor_target_table): Add skylake_cost for skylake-avx512. * config/i386/x86-tune-costs.h (skylake_memcpy, skylake_memset, skylake_cost): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect skylake-avx512. * config.gcc: Add -march=cannonlake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect cannonlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle cannonlake. * config/i386/i386.c (processor_costs): Add m_CANNONLAKE. (PTA_CANNONLAKE): New. (processor_target_table): Add cannonlake. (ix86_option_override_internal): Ditto. (fold_builtin_cpu): Ditto. (get_builtin_code_for_version): Handle cannonlake. (M_INTEL_COREI7_CANNONLAKE): New. * config/i386/i386.h (TARGET_CANNONLAKE, PROCESSOR_CANNONLAKE): New. * doc/invoke.texi: Add -march=cannonlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.dg/ext/mv16.C: Ditto. libgcc/ * config/i386/cpuinfo.c (get_intel_cpu): Handle cannonlake. * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_CANNONLAKE. From-SVN: r255155
2017-11-24Add missing gcc/config.gcc hunks from r255121.Kirill Yukhin1-2/+4
From-SVN: r255132
2017-11-17Enable building libgcc with CET options.Igor Tsimbalist1-2/+2
Enable building libgcc with CET options by default on Linux/x86 if binutils supports CET v2.0. It can be disabled with --disable-cet. It is an error to configure GCC with --enable-cet if bintuiils doesn't support CET v2.0. ENDBR instruction is added to __morestack_large_model since it is called indirectly. 2017-11-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> config/ * cet.m4: New file. gcc/ * config.gcc (extra_headers): Add cet.h for x86 targets. * config/i386/cet.h: New file. * doc/install.texi: Add --enable-cet/--disable-cet. libgcc/ * Makefile.in (configure_deps): Add $(srcdir)/../config/cet.m4. (CET_FLAGS): New. * config/i386/morestack.S: Include <cet.h>. (__morestack_large_model): Add _CET_ENDBR at function entrance. * config/i386/resms64.h: Include <cet.h>. * config/i386/resms64f.h: Likewise. * config/i386/resms64fx.h: Likewise. * config/i386/resms64x.h: Likewise. * config/i386/savms64.h: Likewise. * config/i386/savms64f.h: Likewise. * config/i386/t-linux (HOST_LIBGCC2_CFLAGS): Add $(CET_FLAGS). (CRTSTUFF_T_CFLAGS): Likewise. * configure.ac: Include ../config/cet.m4. Set and substitute CET_FLAGS. * configure: Regenerated. From-SVN: r254868
2017-11-14Adapt Solaris 12 referencesRainer Orth1-2/+2
libgcc: * config.host (*-*-solaris2*): Adapt comment for Solaris 12 renaming. * config/sol2/crtpg.c (__start_crt_compiler): Likewise. * configure.ac (libgcc_cv_solaris_crts): Likewise. * configure: Regenerate. gcc: * config.gcc (*-*-solaris2*): Enable default_use_cxa_atexit since Solaris 11. Update comment. * configure.ac (gcc_cv_ld_pid): Adapt comment for Solaris 12 renaming. * config/sol2.h (STARTFILE_SPEC): Likewise. * configure: Regenerate. gcc/testsuite: * lib/target-supports.exp (check_effective_target_pie): Adapt comment for Solaris 12 renaming. * gcc.dg/torture/pr60092.c: Remove *-*-solaris2.11* dg-xfail-run-if. From-SVN: r254737
2017-10-31GFNI enabling [2/4]Julia Koval1-2/+4
gcc/ * config.gcc: Add gfniintrin.h. * config/i386/gfniintrin.h: New. * config/i386/i386-builtin-types.def ( __builtin_ia32_vgf2p8affineinvqb_v64qi, __builtin_ia32_vgf2p8affineinvqb_v64qi_mask, __builtin_ia32_vgf2p8affineinvqb_v32qi __builtin_ia32_vgf2p8affineinvqb_v32qi_mask, __builtin_ia32_vgf2p8affineinvqb_v16qi, __builtin_ia32_vgf2p8affineinvqb_v16qi_mask): New builtins. * config/i386/i386-builtin.def (V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI, V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI, V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI, V64QI_FTYPE_V64QI_V64QI_INT): New types. * config/i386/i386.c (ix86_expand_args_builtin): Handle new types. * config/i386/immintrin.h: Include gfniintrin.h. * config/i386/sse.md (vgf2p8affineinvqb_*) New pattern. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/avx512-check.h: Check GFNI bit. * gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/gfni-1.c: New. * gcc.target/i386/gfni-2.c: New. * gcc.target/i386/gfni-3.c: New. * gcc.target/i386/gfni-4.c: New. * gcc.target/i386/i386.exp: (check_effective_target_gfni): New. * gcc.target/i386/sse-12.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r254250
2017-10-30Part 1/2 for contributing PPC64LE support for X86 SSE2 instrisics.Steven Munroe1-1/+1
Part 1/2 for contributing PPC64LE support for X86 SSE2 instrisics. This patch includes the new (for PPC) emmintrin.h, changes x86intrin.h to include xmmintrin.h, and associated config.gcc changes. From-SVN: r254234
2017-10-21Update x86 backend to enable Intel CET.Igor Tsimbalist1-3/+4
All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977
2017-10-16config.gcc (powerpc*-*-*spe*): Pick 8548 as the default with_cpu if we were ↵Olivier Hainque1-4/+11
configured for an e500v2 target... 2017-10-16 Olivier Hainque <hainque@adacore.com> * gcc/config.gcc (powerpc*-*-*spe*): Pick 8548 as the default with_cpu if we were configured for an e500v2 target cpu name. From-SVN: r253789
2017-10-14re PR bootstrap/82548 (After -r 253646 GCC 8.0 can't build cross compiler ↵Jakub Jelinek1-4/+4
for mingw32) PR bootstrap/82548 * config.gcc (*-*-solaris2*, i[34567]86-*-cygwin*, x86_64-*-cygwin*, i[34567]86-*-mingw* | x86_64-*-mingw*): Append objects to extra_objs instead of overwriting it. From-SVN: r253753
2017-10-11config.gcc (i386, x86_64): Add extra objects.Jan Hubicka1-0/+2
* config.gcc (i386, x86_64): Add extra objects. * i386/i386-protos.h (ix86_rip_relative_addr_p): Declare. (ix86_min_insn_size): Declare. (ix86_issue_rate): Declare. (ix86_adjust_cost): Declare. (ia32_multipass_dfa_lookahead): Declare. (ix86_macro_fusion_p): Declare. (ix86_macro_fusion_pair_p): Declare. (ix86_bd_has_dispatch): Declare. (ix86_bd_do_dispatch): Declare. (ix86_core2i7_init_hooks): Declare. (ix86_atom_sched_reorder): Declare. * i386/i386.c Move all CPU cost tables to x86-tune-costs.h. (COSTS_N_BYTES): Move to x86-tune-costs.h. (DUMMY_STRINGOP_ALGS):x86-tune-costs.h. (rip_relative_addr_p): Rename to ... (ix86_rip_relative_addr_p): ... this one; export. (memory_address_length): Update. (ix86_issue_rate): Move to x86-tune-sched.c. (ix86_flags_dependent): Move to x86-tune-sched.c. (ix86_agi_dependent): Move to x86-tune-sched.c. (exact_dependency_1): Move to x86-tune-sched.c. (exact_store_load_dependency): Move to x86-tune-sched.c. (ix86_adjust_cost): Move to x86-tune-sched.c. (ia32_multipass_dfa_lookahead): Move to x86-tune-sched.c. (ix86_macro_fusion_p): Move to x86-tune-sched.c. (ix86_macro_fusion_pair_p): Move to x86-tune-sched.c. (do_reorder_for_imul): Move to x86-tune-sched-atom.c. (swap_top_of_ready_list): Move to x86-tune-sched-atom.c. (ix86_sched_reorder): Move to x86-tune-sched-atom.c. (core2i7_first_cycle_multipass_init): Move to x86-tune-sched-core.c. (core2i7_dfa_post_advance_cycle): Move to x86-tune-sched-core.c. (min_insn_size): Rename to ... (ix86_min_insn_size): ... this one; export. (core2i7_first_cycle_multipass_begin): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_issue): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_backtrack): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_end): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_fini): Move to x86-tune-sched-core.c. (ix86_sched_init_global): Break up logic to ix86_core2i7_init_hooks. (ix86_avoid_jump_mispredicts): Update. (TARGET_SCHED_DISPATCH): Move to ix86-tune-sched-bd.c. (TARGET_SCHED_DISPATCH_DO): Move to ix86-tune-sched-bd.c. (TARGET_SCHED_REORDER): Move to ix86-tune-sched-bd.c. (DISPATCH_WINDOW_SIZE): Move to ix86-tune-sched-bd.c. (MAX_DISPATCH_WINDOWS): Move to ix86-tune-sched-bd.c. (MAX_INSN): Move to ix86-tune-sched-bd.c. (MAX_IMM): Move to ix86-tune-sched-bd.c. (MAX_IMM_SIZE): Move to ix86-tune-sched-bd.c. (MAX_IMM_32): Move to ix86-tune-sched-bd.c. (MAX_IMM_64): Move to ix86-tune-sched-bd.c. (MAX_LOAD): Move to ix86-tune-sched-bd.c. (MAX_STORE): Move to ix86-tune-sched-bd.c. (BIG): Move to ix86-tune-sched-bd.c. (enum dispatch_group): Move to ix86-tune-sched-bd.c. (enum insn_path): Move to ix86-tune-sched-bd.c. (get_mem_group): Move to ix86-tune-sched-bd.c. (is_cmp): Move to ix86-tune-sched-bd.c. (dispatch_violation): Move to ix86-tune-sched-bd.c. (is_branch): Move to ix86-tune-sched-bd.c. (is_prefetch): Move to ix86-tune-sched-bd.c. (init_window): Move to ix86-tune-sched-bd.c. (allocate_window): Move to ix86-tune-sched-bd.c. (init_dispatch_sched): Move to ix86-tune-sched-bd.c. (is_end_basic_block): Move to ix86-tune-sched-bd.c. (process_end_window): Move to ix86-tune-sched-bd.c. (allocate_next_window): Move to ix86-tune-sched-bd.c. (find_constant): Move to ix86-tune-sched-bd.c. (get_num_immediates): Move to ix86-tune-sched-bd.c. (has_immediate): Move to ix86-tune-sched-bd.c. (get_insn_path): Move to ix86-tune-sched-bd.c. (get_insn_group): Move to ix86-tune-sched-bd.c. (count_num_restricted): Move to ix86-tune-sched-bd.c. (fits_dispatch_window): Move to ix86-tune-sched-bd.c. (add_insn_window): Move to ix86-tune-sched-bd.c. (add_to_dispatch_window): Move to ix86-tune-sched-bd.c. (debug_dispatch_window_file): Move to ix86-tune-sched-bd.c. (debug_dispatch_window): Move to ix86-tune-sched-bd.c. (debug_insn_dispatch_info_file): Move to ix86-tune-sched-bd.c. (debug_ready_dispatch): Move to ix86-tune-sched-bd.c. (do_dispatch): Move to ix86-tune-sched-bd.c. (has_dispatch): Move to ix86-tune-sched-bd.c. * i386/t-i386: Add new object files. * i386/x86-tune-costs.h: New file. * i386/x86-tune-sched-atom.c: New file. * i386/x86-tune-sched-bd.c: New file. * i386/x86-tune-sched-core.c: New file. * i386/x86-tune-sched.c: New file. From-SVN: r253646
2017-10-11Enable ifunc attribute by default for ARM GNU/LinuxAdhemerval Zanella1-1/+1
Similar to other architectures with IFUNC binutils/glibc support, this patch enables the ifunc attribute for ARM GNU/Linux. Although not required for build master GLIBC, the intention is to allow refactor its assembly implementation to C. Tested compilation of glibc (in conjunction with a glibc patch to support using the attribute on ARM) with build-many-glibcs.py (with a patch to add a armv7 variant which enables multiarch). I have not run the GCC tests for ARM. * config.gcc (default_gnu_indirect_function): Default to yes for arm*-*-linux* with glibc. From-SVN: r253635
2017-10-10config.gcc (armv7*-*-freebsd*): New target.Andreas Tobler1-1/+4
2017-10-10 Andreas Tobler <andreast@gcc.gnu.org> * config.gcc (armv7*-*-freebsd*): New target. (armv6*-*-freebsd*): Remove obsolete TARGET_FREEBSD_ARMv6 define. From-SVN: r253602
2017-10-09amo.h: New include file to provide ISA 3.0 atomic memory operation ↵Michael Meissner1-1/+2
instruction support. [gcc] 2017-10-09 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/amo.h: New include file to provide ISA 3.0 atomic memory operation instruction support. * config.gcc (powerpc*-*-*): Include amo.h as an extra header. (rs6000-ibm-aix[789]*): Likewise. * doc/extend.texi (PowerPC Atomic Memory Operation Functions): Document new functions. [gcc/testsuite] 2017-10-09 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/amo1.c: New test. * gcc.target/powerpc/amo2.c: Likewise. From-SVN: r253552
2017-09-30config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, ↵Krister Walfridsson1-12/+14
netbsd-stdint.h, and netbsd-elf.h. 2017-09-30 Krister Walfridsson <krister.walfridsson@gmail.com> Maya Rashish <coypu@sdf.org> * config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, netbsd-stdint.h, and netbsd-elf.h. (alpha*-*-netbsd*) Use nbsd_tm_file. (arm*-*-netbsdelf*) Likewise. (i[34567]86-*-netbsdelf*) Likewise. (x86_64-*-netbsd*) Likewise. (mips*-*-netbsd*) Likewise. (powerpc-*-netbsd*) Likewise. (sh*-*-netbsd*) Likewise. (sparc-*-netbsdelf*) Likewise. (sparc64-*-netbsd*) Likewise. (m68k*-*-netbsdelf*) Use nbsd_tm_file and add CHAR_FAST8/SHORT_FAST16 to tm_defines. (vax-*-netbsdelf*) Likewise. * config/netbsd-stdint.h (INT_FAST8_TYPE): Check CHAR_FAST8. (UINT_FAST8_TYPE) Likewise. (INT_FAST16_TYPE) Check CHAR_FAST16. (UINT_FAST16_TYPE) Likewise. Co-Authored-By: Maya Rashish <coypu@sdf.org> From-SVN: r253323
2017-09-28Enable ifunc attribute by default for SPARC GNU/Linux.Joseph Myers1-1/+1
Similar to other architectures with IFUNC binutils/glibc support, this patch enables the ifunc attribute for SPARC GNU/Linux. This is needed for building glibc with the current checks on IFUNC resolver types (and use of the attribute in glibc rather than manually created IFUNCs is beneficial anyway because it results in better debug info). Tested compilation of glibc with build-many-glibcs.py. I have not run the GCC tests for SPARC. * config.gcc (default_gnu_indirect_function): Default to yes for sparc*-*-linux* with glibc. From-SVN: r253253
2017-09-26re PR target/39570 (cabs and cabsf are named differently on NetBSD 5)Krister Walfridsson1-1/+3
2017-09-26 Krister Walfridsson <krister.walfridsson@gmail.com> PR target/39570 * gcc/config/netbsd-protos.h: New file. * gcc/config/netbsd.c: New file. * gcc/config/netbsd.h (SUBTARGET_INIT_BUILTINS): Define. * gcc/config/t-netbsd: New file. * gcc/config.gcc (tm_p_file): Add netbsd-protos.h. (tmake_file) Add t-netbsd. (extra_objs) Add netbsd.o. From-SVN: r253216
2017-09-22config.gcc: Add new case statement to set default_gnu_indirect_function.Steve Ellcey1-27/+14
2017-09-22 Steve Ellcey <sellcey@cavium.com> * config.gcc: Add new case statement to set default_gnu_indirect_function. Remove it from x86_64-*-linux*, i[34567]86-*, powerpc*-*-linux*spe*, powerpc*-*-linux*, s390-*-linux*, s390x-*-linux* case statements. Added aarch64 to the list of supported architectures. From-SVN: r253104
2017-09-22[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-1/+1
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. 2017-09-22 Richard Earnshaw <richard.earnshaw@arm.com> * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (TM_H): Remove. (GTM_H): Add arm-isa.h. (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r253097
2017-09-20config.gcc: Support "knm".Sebastian Peryt1-1/+1
gcc/ * config.gcc: Support "knm". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "knm". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_KNM. * config/i386/i386.c (m_KNM): Define. (processor_target_table): Add "knm". (PTA_KNM): Define. (ix86_option_override_internal): Add "knm". (ix86_issue_rate): Add PROCESSOR_KNM. (ix86_adjust_cost): Ditto. (ia32_multipass_dfa_lookahead): Ditto. (get_builtin_code_for_version): Handle PROCESSOR_KNM. (fold_builtin_cpu): Add M_INTEL_KNM. * config/i386/i386.h (processor_costs): Define TARGET_KNM. (processor_type): Add PROCESSOR_KNM. * config/i386/x86-tune.def: Add m_KNM. * doc/invoke.texi: Add knm as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_KNM. * config/i386/cpuinfo.c (get_intel_cpu): Detect Knights Mill. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test knm. * gcc.target/i386/funcspec-56.inc: Test arch=knm. From-SVN: r253013
2017-09-112017-09-11 Vidya Praveen <vidyapraveen@arm.com>Vidya Praveen1-1/+1
Revert r251800 and r251799. From-SVN: r251980
2017-09-06config.gcc (powerpc-wrs-vxworksspe): Now match as vxworks*spe.Olivier Hainque1-1/+1
2017-09-06 Olivier Hainque <hainque@adacore.com> * config.gcc (powerpc-wrs-vxworksspe): Now match as vxworks*spe. From-SVN: r251809
2017-09-06[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-1/+1
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (OPTIONS_H_EXTRA): Add arm-isa.h (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r251799
2017-08-31config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now match as ↵Olivier Hainque1-1/+1
powerpc-wrs-vxworks*. 2017-08-31 Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now match as powerpc-wrs-vxworks*. libgcc/ * config.host: Likewise. From-SVN: r251573
2017-08-31[ARC] Use -G option to control sdata behaviorClaudiu Zissulescu1-1/+1
gcc/ 2017-04-24 Claudiu Zissulescu <claziss@synopsys.com> * config.gcc: Use g.opt for arc. * config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted, functionality moved to ... (legitimate_scaled_address_p): New function, ...here. (LEGITIMATE_SMALL_DATA_OFFSET_P): New define. (LEGITIMATE_SMALL_DATA_ADDRESS_P): Use the above define. (legitimate_offset_address_p): Delete TARGET_NO_SDATA_SET condition. (arc_override_options): Handle G option. (arc_output_pic_addr_const): Correct function definition. (arc_legitimate_address_p): Use legitimate_scaled_address_p. (arc_decl_anon_ns_mem_p): Delete. (arc_in_small_data_p): Overhaul this function to take into consideration the value given via G option. (arc_rewrite_small_data_1): Renamed and corrected old arc_rewrite_small_data function. (arc_rewrite_small_data): New function. (small_data_pattern): Don't use pic_offset_table_rtx. * config/arc/arc.h (CC1_SPEC): Recognize G option. * config/arc/simdext.md (movmisalignv2hi): Use prepare_move_operands function. (mov*): Likewise. (movmisalign*): Likewise. gcc/testsuite/ 2017-04-24 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/sdata-5.c: New test. * gcc.target/arc/arc700-stld-hazard.c: Update test options. Fix test From-SVN: r251564
2017-08-25Part 2/3 for contributing PPC64LE support for X86 SSE instrisics.Steven Munroe1-0/+1
Part 2/3 for contributing PPC64LE support for X86 SSE instrisics. This patch includes the new (for PPC) xmmintrin.h, changes x86intrin.h to include xmmintrin.h and associated config.gcc changes. From-SVN: r251356
2017-08-22[PowerPC/RTEMS] Enable -mcmodel optionSebastian Huber1-1/+1
gcc/ * config.gcc (powerpc-*-rtems*): Add rs6000/linux64.opt. * config/rs6000/rtems.h (ASM_PREFERRED_EH_DATA_FORMAT): New define. (DOT_SYMBOLS): Likewise. (MINIMAL_TOC_SECTION_ASM_OP): Likewise. (RELOCATABLE_NEEDS_FIXUP): Likewise. (RS6000_ABI_NAME): Likewise. (TARGET_CMODEL): Likewise. (TOC_SECTION_ASM_OP): Likewise. (SET_CMODEL): New macro. (SUBSUBTARGET_OVERRIDE_OPTIONS): Evaluate cmodel options. From-SVN: r251275
2017-08-16Fix building of cross compiler (PR target/81753).Martin Liska1-1/+1
2017-08-16 Martin Liska <mliska@suse.cz> PR target/81753 * config.gcc: Respect previously set extra_objs in case of darwin target. From-SVN: r251118
2017-08-01config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as ↵Jerome Lambourg1-3/+15
arm-wrs-vxworks. 2017-08-01 Jerome Lambourg <lambourg@adacore.com> Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. Update target_cpu_name from arm6 (arch v3) to arm8 (arch v4). * config/arm/vxworks.h (MAYBE_TARGET_BPABI_CPP_BUILTINS): New, helper for TARGET_OS_CPP_BUILTIN. (TARGET_OS_CPP_BUILTIN): Invoke MAYBE_TARGET_BPABI_CPP_BUILTINS(), refine CPU definitions for arm_arch5 and add those for arm_arch6 and arm_arch7. (MAYBE_ASM_ABI_SPEC): New, helper for SUBTARGET_EXTRA_ASM_SPEC, passing required abi options to the assembler for EABI configurations. (EXTRA_CC1_SPEC): New macro, to help prevent the implicit production of .text.hot and .text.unlikely sections for kernel modules when using ARM style exceptions. (CC1_SPEC): Remove obsolete attempt at mimicking Diab toolchain options. Add EXTRA_CC1_SPEC. (VXWORKS_ENDIAN_SPEC): Adjust comment and remove handling of Diab toolchain options. (DWARF2_UNWIND_INFO): Redefine to handle the pre/post VxWorks 7 transition. (ARM_TARGET2_DWARF_FORMAT): Define. * config/arm/t-vxworks: Adjust multilib control to removal of the Diab command line options. libgcc/ * config.host (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. * config/arm/t-vxworks7: New file. Add unwind-arm-vxworks.c to LIB2ADDEH. * config/arm/unwind-arm-vxworks.c: New file. Provide dummy __exidx_start and __exidx_end for downloadable modules. Co-Authored-By: Doug Rupp <rupp@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r250781
2017-07-31[Committed] S/390: Support z14 as CPU name.Andreas Krebbel1-1/+1
With IBM z14 officially announced we can add support for z14 as preferred CPU name. We still pass arch12 to Binutils in order to keep older Binutils versions supported. gcc/ChangeLog: 2017-07-31 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config.gcc: Add z14. * config/s390/driver-native.c (s390_host_detect_local_cpu): Add CPU model numbers for z13s and z14. * config/s390/s390-c.c (s390_resolve_overloaded_builtin): Replace arch12 with z14. * config/s390/s390-opts.h (enum processor_type): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. * config/s390/s390.c (processor_table): Add field for CPU name to be passed to Binutils. (s390_asm_output_machine_for_arch): Use the new field in processor_table for Binutils. (s390_expand_builtin): Replace arch12 with z14. (s390_issue_rate): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. (s390_get_sched_attrmask): Likewise. (s390_get_unit_mask): Likewise. * config/s390/s390.opt: Add z14 to processor_type enum. From-SVN: r250739
2017-07-28[PowerPC/RTEMS] Add 64-bit support using ELFv2 ABISebastian Huber1-1/+1
Add 64-bit support for RTEMS using the ELFv2 ABI with 64-bit long double. gcc/ * config.gcc (powerpc-*-rtems*): Remove rs6000/eabi.h. Add rs6000/biarch64.h. * config/rs6000/rtems.h (ASM_DECLARE_FUNCTION_SIZE): New macro. (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise. (CRT_CALL_STATIC_FUNCTION): Likewise. (ASM_DEFAULT_SPEC): New define. (ASM_SPEC32): Likewise. (ASM_SPEC64): Likewise. (ASM_SPEC_COMMON): Likewise. (ASM_SPEC): Likewise. (INVALID_64BIT): Likewise. (LINK_OS_DEFAULT_SPEC): Likewise. (LINK_OS_SPEC32): Likewise. (LINK_OS_SPEC64): Likewise. (POWERPC_LINUX): Likewise. (PTRDIFF_TYPE): Likewise. (RESTORE_FP_PREFIX): Likewise. (RESTORE_FP_SUFFIX): Likewise. (SAVE_FP_PREFIX): Likewise. (SAVE_FP_SUFFIX): Likewise. (SIZE_TYPE): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_64BIT): Likewise. (TARGET_64BIT): Likewise. (TARGET_AIX): Likewise. (WCHAR_TYPE_SIZE): Likewise. (WCHAR_TYPE): Undefine. (TARGET_OS_CPP_BUILTINS): Add 64-bit PowerPC defines. (CPP_OS_DEFAULT_SPEC): Use previous CPP_OS_RTEMS_SPEC. (CPP_OS_RTEMS_SPEC): Delete. (SUBSUBTARGET_EXTRA_SPECS): Remove cpp_os_rtems. Add asm_spec_common, asm_spec32, asm_spec64, link_os_spec32, and link_os_spec64. * config/rs6000/t-rtems: Add mcpu=e6500/m64 multilibs. libgcc/ * config/rs6000/ibm-ldouble.c: Disable if defined __rtems__. From-SVN: r250652
2017-07-27Add RTEMS supportSebastian Huber1-1/+6
gcc/ChangeLog 2017-07-27 Sebastian Huber <sebastian.huber@embedded-brains.de> * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*). * config/riscv/rtems.h: New file. From-SVN: r250632
2017-07-23config.gcc (*-*-netbsd*): Remove check for NetBSD versions not having ↵Krister Walfridsson1-8/+1
__cxa_atexit. 2017-07-23 Krister Walfridsson <krister.walfridsson@gmail.com> * config.gcc (*-*-netbsd*): Remove check for NetBSD versions not having __cxa_atexit. From-SVN: r250466
2017-07-19Now adding the mmintrin.h intrinsic headers. The DG tests will follow.Steven Munroe1-1/+2
2017-07-19 Steven Munroe <munroesj@gcc.gnu.org> * config.gcc (powerpc*-*-*): Add mmintrin.h. * config/rs6000/mmintrin.h: New file. * config/rs6000/x86intrin.h [__ALTIVEC__]: Include mmintrin.h. From-SVN: r250350
2017-07-10[ARC] Configure script to allow non uclibc based tripletsVineet Gupta1-1/+1
gcc/ 2017-07-10 Vineet Gupta <vgupta@synopsys.com> * config.gcc: Remove uclibc from arc target spec. libgcc/ 2017-07-10 Vineet Gupta <vgupta@synopsys.com> * config.host: Remove uclibc from arc target spec. From-SVN: r250097
generated by cgit v1.1 at 2025-08-07 03:06:57 +0000