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2017-10-31GFNI enabling [2/4]Julia Koval1-2/+4
gcc/ * config.gcc: Add gfniintrin.h. * config/i386/gfniintrin.h: New. * config/i386/i386-builtin-types.def ( __builtin_ia32_vgf2p8affineinvqb_v64qi, __builtin_ia32_vgf2p8affineinvqb_v64qi_mask, __builtin_ia32_vgf2p8affineinvqb_v32qi __builtin_ia32_vgf2p8affineinvqb_v32qi_mask, __builtin_ia32_vgf2p8affineinvqb_v16qi, __builtin_ia32_vgf2p8affineinvqb_v16qi_mask): New builtins. * config/i386/i386-builtin.def (V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI, V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI, V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI, V64QI_FTYPE_V64QI_V64QI_INT): New types. * config/i386/i386.c (ix86_expand_args_builtin): Handle new types. * config/i386/immintrin.h: Include gfniintrin.h. * config/i386/sse.md (vgf2p8affineinvqb_*) New pattern. gcc/testsuite/ * gcc.target/i386/avx-1.c: Handle new intrinsics. * gcc.target/i386/avx512-check.h: Check GFNI bit. * gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c: Runtime test. * gcc.target/i386/gfni-1.c: New. * gcc.target/i386/gfni-2.c: New. * gcc.target/i386/gfni-3.c: New. * gcc.target/i386/gfni-4.c: New. * gcc.target/i386/i386.exp: (check_effective_target_gfni): New. * gcc.target/i386/sse-12.c: Handle new intrinsics. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. From-SVN: r254250
2017-10-30Part 1/2 for contributing PPC64LE support for X86 SSE2 instrisics.Steven Munroe1-1/+1
Part 1/2 for contributing PPC64LE support for X86 SSE2 instrisics. This patch includes the new (for PPC) emmintrin.h, changes x86intrin.h to include xmmintrin.h, and associated config.gcc changes. From-SVN: r254234
2017-10-21Update x86 backend to enable Intel CET.Igor Tsimbalist1-3/+4
All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977
2017-10-16config.gcc (powerpc*-*-*spe*): Pick 8548 as the default with_cpu if we were ↵Olivier Hainque1-4/+11
configured for an e500v2 target... 2017-10-16 Olivier Hainque <hainque@adacore.com> * gcc/config.gcc (powerpc*-*-*spe*): Pick 8548 as the default with_cpu if we were configured for an e500v2 target cpu name. From-SVN: r253789
2017-10-14re PR bootstrap/82548 (After -r 253646 GCC 8.0 can't build cross compiler ↵Jakub Jelinek1-4/+4
for mingw32) PR bootstrap/82548 * config.gcc (*-*-solaris2*, i[34567]86-*-cygwin*, x86_64-*-cygwin*, i[34567]86-*-mingw* | x86_64-*-mingw*): Append objects to extra_objs instead of overwriting it. From-SVN: r253753
2017-10-11config.gcc (i386, x86_64): Add extra objects.Jan Hubicka1-0/+2
* config.gcc (i386, x86_64): Add extra objects. * i386/i386-protos.h (ix86_rip_relative_addr_p): Declare. (ix86_min_insn_size): Declare. (ix86_issue_rate): Declare. (ix86_adjust_cost): Declare. (ia32_multipass_dfa_lookahead): Declare. (ix86_macro_fusion_p): Declare. (ix86_macro_fusion_pair_p): Declare. (ix86_bd_has_dispatch): Declare. (ix86_bd_do_dispatch): Declare. (ix86_core2i7_init_hooks): Declare. (ix86_atom_sched_reorder): Declare. * i386/i386.c Move all CPU cost tables to x86-tune-costs.h. (COSTS_N_BYTES): Move to x86-tune-costs.h. (DUMMY_STRINGOP_ALGS):x86-tune-costs.h. (rip_relative_addr_p): Rename to ... (ix86_rip_relative_addr_p): ... this one; export. (memory_address_length): Update. (ix86_issue_rate): Move to x86-tune-sched.c. (ix86_flags_dependent): Move to x86-tune-sched.c. (ix86_agi_dependent): Move to x86-tune-sched.c. (exact_dependency_1): Move to x86-tune-sched.c. (exact_store_load_dependency): Move to x86-tune-sched.c. (ix86_adjust_cost): Move to x86-tune-sched.c. (ia32_multipass_dfa_lookahead): Move to x86-tune-sched.c. (ix86_macro_fusion_p): Move to x86-tune-sched.c. (ix86_macro_fusion_pair_p): Move to x86-tune-sched.c. (do_reorder_for_imul): Move to x86-tune-sched-atom.c. (swap_top_of_ready_list): Move to x86-tune-sched-atom.c. (ix86_sched_reorder): Move to x86-tune-sched-atom.c. (core2i7_first_cycle_multipass_init): Move to x86-tune-sched-core.c. (core2i7_dfa_post_advance_cycle): Move to x86-tune-sched-core.c. (min_insn_size): Rename to ... (ix86_min_insn_size): ... this one; export. (core2i7_first_cycle_multipass_begin): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_issue): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_backtrack): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_end): Move to x86-tune-sched-core.c. (core2i7_first_cycle_multipass_fini): Move to x86-tune-sched-core.c. (ix86_sched_init_global): Break up logic to ix86_core2i7_init_hooks. (ix86_avoid_jump_mispredicts): Update. (TARGET_SCHED_DISPATCH): Move to ix86-tune-sched-bd.c. (TARGET_SCHED_DISPATCH_DO): Move to ix86-tune-sched-bd.c. (TARGET_SCHED_REORDER): Move to ix86-tune-sched-bd.c. (DISPATCH_WINDOW_SIZE): Move to ix86-tune-sched-bd.c. (MAX_DISPATCH_WINDOWS): Move to ix86-tune-sched-bd.c. (MAX_INSN): Move to ix86-tune-sched-bd.c. (MAX_IMM): Move to ix86-tune-sched-bd.c. (MAX_IMM_SIZE): Move to ix86-tune-sched-bd.c. (MAX_IMM_32): Move to ix86-tune-sched-bd.c. (MAX_IMM_64): Move to ix86-tune-sched-bd.c. (MAX_LOAD): Move to ix86-tune-sched-bd.c. (MAX_STORE): Move to ix86-tune-sched-bd.c. (BIG): Move to ix86-tune-sched-bd.c. (enum dispatch_group): Move to ix86-tune-sched-bd.c. (enum insn_path): Move to ix86-tune-sched-bd.c. (get_mem_group): Move to ix86-tune-sched-bd.c. (is_cmp): Move to ix86-tune-sched-bd.c. (dispatch_violation): Move to ix86-tune-sched-bd.c. (is_branch): Move to ix86-tune-sched-bd.c. (is_prefetch): Move to ix86-tune-sched-bd.c. (init_window): Move to ix86-tune-sched-bd.c. (allocate_window): Move to ix86-tune-sched-bd.c. (init_dispatch_sched): Move to ix86-tune-sched-bd.c. (is_end_basic_block): Move to ix86-tune-sched-bd.c. (process_end_window): Move to ix86-tune-sched-bd.c. (allocate_next_window): Move to ix86-tune-sched-bd.c. (find_constant): Move to ix86-tune-sched-bd.c. (get_num_immediates): Move to ix86-tune-sched-bd.c. (has_immediate): Move to ix86-tune-sched-bd.c. (get_insn_path): Move to ix86-tune-sched-bd.c. (get_insn_group): Move to ix86-tune-sched-bd.c. (count_num_restricted): Move to ix86-tune-sched-bd.c. (fits_dispatch_window): Move to ix86-tune-sched-bd.c. (add_insn_window): Move to ix86-tune-sched-bd.c. (add_to_dispatch_window): Move to ix86-tune-sched-bd.c. (debug_dispatch_window_file): Move to ix86-tune-sched-bd.c. (debug_dispatch_window): Move to ix86-tune-sched-bd.c. (debug_insn_dispatch_info_file): Move to ix86-tune-sched-bd.c. (debug_ready_dispatch): Move to ix86-tune-sched-bd.c. (do_dispatch): Move to ix86-tune-sched-bd.c. (has_dispatch): Move to ix86-tune-sched-bd.c. * i386/t-i386: Add new object files. * i386/x86-tune-costs.h: New file. * i386/x86-tune-sched-atom.c: New file. * i386/x86-tune-sched-bd.c: New file. * i386/x86-tune-sched-core.c: New file. * i386/x86-tune-sched.c: New file. From-SVN: r253646
2017-10-11Enable ifunc attribute by default for ARM GNU/LinuxAdhemerval Zanella1-1/+1
Similar to other architectures with IFUNC binutils/glibc support, this patch enables the ifunc attribute for ARM GNU/Linux. Although not required for build master GLIBC, the intention is to allow refactor its assembly implementation to C. Tested compilation of glibc (in conjunction with a glibc patch to support using the attribute on ARM) with build-many-glibcs.py (with a patch to add a armv7 variant which enables multiarch). I have not run the GCC tests for ARM. * config.gcc (default_gnu_indirect_function): Default to yes for arm*-*-linux* with glibc. From-SVN: r253635
2017-10-10config.gcc (armv7*-*-freebsd*): New target.Andreas Tobler1-1/+4
2017-10-10 Andreas Tobler <andreast@gcc.gnu.org> * config.gcc (armv7*-*-freebsd*): New target. (armv6*-*-freebsd*): Remove obsolete TARGET_FREEBSD_ARMv6 define. From-SVN: r253602
2017-10-09amo.h: New include file to provide ISA 3.0 atomic memory operation ↵Michael Meissner1-1/+2
instruction support. [gcc] 2017-10-09 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/amo.h: New include file to provide ISA 3.0 atomic memory operation instruction support. * config.gcc (powerpc*-*-*): Include amo.h as an extra header. (rs6000-ibm-aix[789]*): Likewise. * doc/extend.texi (PowerPC Atomic Memory Operation Functions): Document new functions. [gcc/testsuite] 2017-10-09 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/amo1.c: New test. * gcc.target/powerpc/amo2.c: Likewise. From-SVN: r253552
2017-09-30config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, ↵Krister Walfridsson1-12/+14
netbsd-stdint.h, and netbsd-elf.h. 2017-09-30 Krister Walfridsson <krister.walfridsson@gmail.com> Maya Rashish <coypu@sdf.org> * config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, netbsd-stdint.h, and netbsd-elf.h. (alpha*-*-netbsd*) Use nbsd_tm_file. (arm*-*-netbsdelf*) Likewise. (i[34567]86-*-netbsdelf*) Likewise. (x86_64-*-netbsd*) Likewise. (mips*-*-netbsd*) Likewise. (powerpc-*-netbsd*) Likewise. (sh*-*-netbsd*) Likewise. (sparc-*-netbsdelf*) Likewise. (sparc64-*-netbsd*) Likewise. (m68k*-*-netbsdelf*) Use nbsd_tm_file and add CHAR_FAST8/SHORT_FAST16 to tm_defines. (vax-*-netbsdelf*) Likewise. * config/netbsd-stdint.h (INT_FAST8_TYPE): Check CHAR_FAST8. (UINT_FAST8_TYPE) Likewise. (INT_FAST16_TYPE) Check CHAR_FAST16. (UINT_FAST16_TYPE) Likewise. Co-Authored-By: Maya Rashish <coypu@sdf.org> From-SVN: r253323
2017-09-28Enable ifunc attribute by default for SPARC GNU/Linux.Joseph Myers1-1/+1
Similar to other architectures with IFUNC binutils/glibc support, this patch enables the ifunc attribute for SPARC GNU/Linux. This is needed for building glibc with the current checks on IFUNC resolver types (and use of the attribute in glibc rather than manually created IFUNCs is beneficial anyway because it results in better debug info). Tested compilation of glibc with build-many-glibcs.py. I have not run the GCC tests for SPARC. * config.gcc (default_gnu_indirect_function): Default to yes for sparc*-*-linux* with glibc. From-SVN: r253253
2017-09-26re PR target/39570 (cabs and cabsf are named differently on NetBSD 5)Krister Walfridsson1-1/+3
2017-09-26 Krister Walfridsson <krister.walfridsson@gmail.com> PR target/39570 * gcc/config/netbsd-protos.h: New file. * gcc/config/netbsd.c: New file. * gcc/config/netbsd.h (SUBTARGET_INIT_BUILTINS): Define. * gcc/config/t-netbsd: New file. * gcc/config.gcc (tm_p_file): Add netbsd-protos.h. (tmake_file) Add t-netbsd. (extra_objs) Add netbsd.o. From-SVN: r253216
2017-09-22config.gcc: Add new case statement to set default_gnu_indirect_function.Steve Ellcey1-27/+14
2017-09-22 Steve Ellcey <sellcey@cavium.com> * config.gcc: Add new case statement to set default_gnu_indirect_function. Remove it from x86_64-*-linux*, i[34567]86-*, powerpc*-*-linux*spe*, powerpc*-*-linux*, s390-*-linux*, s390x-*-linux* case statements. Added aarch64 to the list of supported architectures. From-SVN: r253104
2017-09-22[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-1/+1
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. 2017-09-22 Richard Earnshaw <richard.earnshaw@arm.com> * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (TM_H): Remove. (GTM_H): Add arm-isa.h. (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r253097
2017-09-20config.gcc: Support "knm".Sebastian Peryt1-1/+1
gcc/ * config.gcc: Support "knm". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "knm". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_KNM. * config/i386/i386.c (m_KNM): Define. (processor_target_table): Add "knm". (PTA_KNM): Define. (ix86_option_override_internal): Add "knm". (ix86_issue_rate): Add PROCESSOR_KNM. (ix86_adjust_cost): Ditto. (ia32_multipass_dfa_lookahead): Ditto. (get_builtin_code_for_version): Handle PROCESSOR_KNM. (fold_builtin_cpu): Add M_INTEL_KNM. * config/i386/i386.h (processor_costs): Define TARGET_KNM. (processor_type): Add PROCESSOR_KNM. * config/i386/x86-tune.def: Add m_KNM. * doc/invoke.texi: Add knm as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_KNM. * config/i386/cpuinfo.c (get_intel_cpu): Detect Knights Mill. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test knm. * gcc.target/i386/funcspec-56.inc: Test arch=knm. From-SVN: r253013
2017-09-112017-09-11 Vidya Praveen <vidyapraveen@arm.com>Vidya Praveen1-1/+1
Revert r251800 and r251799. From-SVN: r251980
2017-09-06config.gcc (powerpc-wrs-vxworksspe): Now match as vxworks*spe.Olivier Hainque1-1/+1
2017-09-06 Olivier Hainque <hainque@adacore.com> * config.gcc (powerpc-wrs-vxworksspe): Now match as vxworks*spe. From-SVN: r251809
2017-09-06[arm] auto-generate arm-isa.h from CPU descriptionsRichard Earnshaw1-1/+1
This patch autogenerates arm-isa.h from new entries in arm-cpus.in. This has the primary advantage that it makes the description file more self-contained, but it also solves the 'array dimensioning' problem that Tamar recently encountered. It adds two new constructs to arm-cpus.in: features and fgroups. Fgroups are simply a way of naming a group of feature bits so that they can be referenced together. We follow the convention that feature bits are all lower case, while fgroups are (predominantly) upper case. This is helpful as in some contexts they share the same namespace. Most of the minor changes in this patch are related to adopting this new naming convention. * config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file. * config/arm/arm-isa.h: Delete. Move definitions to ... * arm-cpus.in: ... here. Use new feature and fgroup values. * config/arm/arm.c (arm_option_override): Use lower case for feature bit names. * config/arm/arm.h (TARGET_HARD_FLOAT): Likewise. (TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise. * config/arm/parsecpu.awk (END): Add new command 'isa'. (isa_pfx): Delete. (print_isa_bits_for): New function. (gen_isa): New function. (gen_comm_data): Use print_isa_bits_for. (define feature): New keyword. (define fgroup): New keyword. * config/arm/t-arm (OPTIONS_H_EXTRA): Add arm-isa.h (arm-isa.h): Add rule to generate file. * common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower case for feature bit names. From-SVN: r251799
2017-08-31config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now match as ↵Olivier Hainque1-1/+1
powerpc-wrs-vxworks*. 2017-08-31 Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now match as powerpc-wrs-vxworks*. libgcc/ * config.host: Likewise. From-SVN: r251573
2017-08-31[ARC] Use -G option to control sdata behaviorClaudiu Zissulescu1-1/+1
gcc/ 2017-04-24 Claudiu Zissulescu <claziss@synopsys.com> * config.gcc: Use g.opt for arc. * config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted, functionality moved to ... (legitimate_scaled_address_p): New function, ...here. (LEGITIMATE_SMALL_DATA_OFFSET_P): New define. (LEGITIMATE_SMALL_DATA_ADDRESS_P): Use the above define. (legitimate_offset_address_p): Delete TARGET_NO_SDATA_SET condition. (arc_override_options): Handle G option. (arc_output_pic_addr_const): Correct function definition. (arc_legitimate_address_p): Use legitimate_scaled_address_p. (arc_decl_anon_ns_mem_p): Delete. (arc_in_small_data_p): Overhaul this function to take into consideration the value given via G option. (arc_rewrite_small_data_1): Renamed and corrected old arc_rewrite_small_data function. (arc_rewrite_small_data): New function. (small_data_pattern): Don't use pic_offset_table_rtx. * config/arc/arc.h (CC1_SPEC): Recognize G option. * config/arc/simdext.md (movmisalignv2hi): Use prepare_move_operands function. (mov*): Likewise. (movmisalign*): Likewise. gcc/testsuite/ 2017-04-24 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/sdata-5.c: New test. * gcc.target/arc/arc700-stld-hazard.c: Update test options. Fix test From-SVN: r251564
2017-08-25Part 2/3 for contributing PPC64LE support for X86 SSE instrisics.Steven Munroe1-0/+1
Part 2/3 for contributing PPC64LE support for X86 SSE instrisics. This patch includes the new (for PPC) xmmintrin.h, changes x86intrin.h to include xmmintrin.h and associated config.gcc changes. From-SVN: r251356
2017-08-22[PowerPC/RTEMS] Enable -mcmodel optionSebastian Huber1-1/+1
gcc/ * config.gcc (powerpc-*-rtems*): Add rs6000/linux64.opt. * config/rs6000/rtems.h (ASM_PREFERRED_EH_DATA_FORMAT): New define. (DOT_SYMBOLS): Likewise. (MINIMAL_TOC_SECTION_ASM_OP): Likewise. (RELOCATABLE_NEEDS_FIXUP): Likewise. (RS6000_ABI_NAME): Likewise. (TARGET_CMODEL): Likewise. (TOC_SECTION_ASM_OP): Likewise. (SET_CMODEL): New macro. (SUBSUBTARGET_OVERRIDE_OPTIONS): Evaluate cmodel options. From-SVN: r251275
2017-08-16Fix building of cross compiler (PR target/81753).Martin Liska1-1/+1
2017-08-16 Martin Liska <mliska@suse.cz> PR target/81753 * config.gcc: Respect previously set extra_objs in case of darwin target. From-SVN: r251118
2017-08-01config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as ↵Jerome Lambourg1-3/+15
arm-wrs-vxworks. 2017-08-01 Jerome Lambourg <lambourg@adacore.com> Doug Rupp <rupp@adacore.com> Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. Update target_cpu_name from arm6 (arch v3) to arm8 (arch v4). * config/arm/vxworks.h (MAYBE_TARGET_BPABI_CPP_BUILTINS): New, helper for TARGET_OS_CPP_BUILTIN. (TARGET_OS_CPP_BUILTIN): Invoke MAYBE_TARGET_BPABI_CPP_BUILTINS(), refine CPU definitions for arm_arch5 and add those for arm_arch6 and arm_arch7. (MAYBE_ASM_ABI_SPEC): New, helper for SUBTARGET_EXTRA_ASM_SPEC, passing required abi options to the assembler for EABI configurations. (EXTRA_CC1_SPEC): New macro, to help prevent the implicit production of .text.hot and .text.unlikely sections for kernel modules when using ARM style exceptions. (CC1_SPEC): Remove obsolete attempt at mimicking Diab toolchain options. Add EXTRA_CC1_SPEC. (VXWORKS_ENDIAN_SPEC): Adjust comment and remove handling of Diab toolchain options. (DWARF2_UNWIND_INFO): Redefine to handle the pre/post VxWorks 7 transition. (ARM_TARGET2_DWARF_FORMAT): Define. * config/arm/t-vxworks: Adjust multilib control to removal of the Diab command line options. libgcc/ * config.host (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as well as arm-wrs-vxworks. * config/arm/t-vxworks7: New file. Add unwind-arm-vxworks.c to LIB2ADDEH. * config/arm/unwind-arm-vxworks.c: New file. Provide dummy __exidx_start and __exidx_end for downloadable modules. Co-Authored-By: Doug Rupp <rupp@adacore.com> Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r250781
2017-07-31[Committed] S/390: Support z14 as CPU name.Andreas Krebbel1-1/+1
With IBM z14 officially announced we can add support for z14 as preferred CPU name. We still pass arch12 to Binutils in order to keep older Binutils versions supported. gcc/ChangeLog: 2017-07-31 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config.gcc: Add z14. * config/s390/driver-native.c (s390_host_detect_local_cpu): Add CPU model numbers for z13s and z14. * config/s390/s390-c.c (s390_resolve_overloaded_builtin): Replace arch12 with z14. * config/s390/s390-opts.h (enum processor_type): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. * config/s390/s390.c (processor_table): Add field for CPU name to be passed to Binutils. (s390_asm_output_machine_for_arch): Use the new field in processor_table for Binutils. (s390_expand_builtin): Replace arch12 with z14. (s390_issue_rate): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14. (s390_get_sched_attrmask): Likewise. (s390_get_unit_mask): Likewise. * config/s390/s390.opt: Add z14 to processor_type enum. From-SVN: r250739
2017-07-28[PowerPC/RTEMS] Add 64-bit support using ELFv2 ABISebastian Huber1-1/+1
Add 64-bit support for RTEMS using the ELFv2 ABI with 64-bit long double. gcc/ * config.gcc (powerpc-*-rtems*): Remove rs6000/eabi.h. Add rs6000/biarch64.h. * config/rs6000/rtems.h (ASM_DECLARE_FUNCTION_SIZE): New macro. (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise. (CRT_CALL_STATIC_FUNCTION): Likewise. (ASM_DEFAULT_SPEC): New define. (ASM_SPEC32): Likewise. (ASM_SPEC64): Likewise. (ASM_SPEC_COMMON): Likewise. (ASM_SPEC): Likewise. (INVALID_64BIT): Likewise. (LINK_OS_DEFAULT_SPEC): Likewise. (LINK_OS_SPEC32): Likewise. (LINK_OS_SPEC64): Likewise. (POWERPC_LINUX): Likewise. (PTRDIFF_TYPE): Likewise. (RESTORE_FP_PREFIX): Likewise. (RESTORE_FP_SUFFIX): Likewise. (SAVE_FP_PREFIX): Likewise. (SAVE_FP_SUFFIX): Likewise. (SIZE_TYPE): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_64BIT): Likewise. (TARGET_64BIT): Likewise. (TARGET_AIX): Likewise. (WCHAR_TYPE_SIZE): Likewise. (WCHAR_TYPE): Undefine. (TARGET_OS_CPP_BUILTINS): Add 64-bit PowerPC defines. (CPP_OS_DEFAULT_SPEC): Use previous CPP_OS_RTEMS_SPEC. (CPP_OS_RTEMS_SPEC): Delete. (SUBSUBTARGET_EXTRA_SPECS): Remove cpp_os_rtems. Add asm_spec_common, asm_spec32, asm_spec64, link_os_spec32, and link_os_spec64. * config/rs6000/t-rtems: Add mcpu=e6500/m64 multilibs. libgcc/ * config/rs6000/ibm-ldouble.c: Disable if defined __rtems__. From-SVN: r250652
2017-07-27Add RTEMS supportSebastian Huber1-1/+6
gcc/ChangeLog 2017-07-27 Sebastian Huber <sebastian.huber@embedded-brains.de> * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*). * config/riscv/rtems.h: New file. From-SVN: r250632
2017-07-23config.gcc (*-*-netbsd*): Remove check for NetBSD versions not having ↵Krister Walfridsson1-8/+1
__cxa_atexit. 2017-07-23 Krister Walfridsson <krister.walfridsson@gmail.com> * config.gcc (*-*-netbsd*): Remove check for NetBSD versions not having __cxa_atexit. From-SVN: r250466
2017-07-19Now adding the mmintrin.h intrinsic headers. The DG tests will follow.Steven Munroe1-1/+2
2017-07-19 Steven Munroe <munroesj@gcc.gnu.org> * config.gcc (powerpc*-*-*): Add mmintrin.h. * config/rs6000/mmintrin.h: New file. * config/rs6000/x86intrin.h [__ALTIVEC__]: Include mmintrin.h. From-SVN: r250350
2017-07-10[ARC] Configure script to allow non uclibc based tripletsVineet Gupta1-1/+1
gcc/ 2017-07-10 Vineet Gupta <vgupta@synopsys.com> * config.gcc: Remove uclibc from arc target spec. libgcc/ 2017-07-10 Vineet Gupta <vgupta@synopsys.com> * config.host: Remove uclibc from arc target spec. From-SVN: r250097
2017-07-09config.gcc (*-*-netbsd*): Remove check for NetBSD versions not supporting ↵Krister Walfridsson1-15/+1
pthreds. 2017-07-09 Krister Walfridsson <krister.walfridsson@gmail.com> * config.gcc (*-*-netbsd*): Remove check for NetBSD versions not supporting pthreds. * config/netbsd.h (NETBSD_LIBGCC_SPEC): Always enable pthreads. From-SVN: r250081
2017-07-07Support for the SPARC M8 cpu.Jose E. Marchesi1-1/+1
This patch serie adds support for the SPARC M8 processor to GCC. The SPARC M8 processor implements the Oracle SPARC Architecture 2017. - bmask* instructions are put in their own instruction type. It makes little sense to have them in the same category than array instructions. - Similarly, VIS compare instructions are put in their own instruction type. This is to better accommodate subtypes, which are not quite the same than the subtypes of `visl' instructions. - The introduction of a new `subtype' insn attribute in sparc.md avoids the need for adjusting the instruction scheduler DFAs for previous cpu models every time a new cpu is introduced. - The full set of SPARC instructions used in sparc.md, and their position in the type/subtype hierarchy, is documented in a comment. This eases the modification of the DFA schedulers, and the addition of new cpus. - The M7 DFA scheduler is reworked: + To use the new type/subtype hierarchy. + The v3pipe insn attribute is no longer needed. + More accurate latencies for instructions. + The C4 core pipeline is documented in a comment in niagara7.md. - Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN denomination for M8 and later processors.) - Support for a new VIS level, VIS4B, covering the new VIS instructions introduced in OSA2017 and implemented in the M8. Also built-ins. - A M8 DFA scheduler: + Also based on the new type/subtype hierarchy. + The functional units in the C5 core are explicitly documented in a comment in m8.md. gcc/ChangeLog: * config/sparc/m8.md: New file. * config/sparc/sparc.md: Include m8.md. * config/sparc/sparc.opt: New option -mvis4b. * config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B. (sparc_option_override): Handle VIS4B. (enum sparc_builtins): Define SPARC_BUILTIN_DICTUNPACK{8,16,32}, SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL, SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL, SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and SPARC_BUILTIN_FPCMPUR{8,16,32}SHL. (check_constant_argument): New function. (sparc_vis_init_builtins): Define builtins __builtin_vis_dictunpack{8,16,32}, __builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl, __builtin_vis_fpcmpu{le,gt}{8,16,32}shl, __builtin_vis_fpcmpde{8,16,32}shl and __builtin_vis_fpcmpur{8,16,32}shl. (sparc_expand_builtin): Check that the constant operands to __builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed constant and in range. * config/sparc/sparc-c.c (sparc_target_macros): Handle TARGET_VIS4B. * config/sparc/sparc.h (SPARC_IMM2_P): Define. (SPARC_IMM5_P): Likewise. * config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b". (enabled): Handle vis4b. (UNSPEC_DICTUNPACK): New unspec. (UNSPEC_FPCMPSHL): Likewise. (UNSPEC_FPUCMPSHL): Likewise. (UNSPEC_FPCMPDESHL): Likewise. (UNSPEC_FPCMPURSHL): Likewise. (cpu_feature): New CPU feature `vis4b'. (dictunpack{8,16,32}): New insns. (FPCSMODE): New mode iterator. (fpcscond): New code iterator. (fpcsucond): Likewise. (fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns. (fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise. (fpcmpde{8,16,32}{si,di}shl): Likewise. (fpcmpur{8,16,32}{si,di}shl): Likewise. * config/sparc/constraints.md: Define constraints `q' for unsigned 2-bit integer constants and `t' for unsigned 5-bit integer constants. * config/sparc/predicates.md (imm5_operand_dictunpack8): New predicate. (imm5_operand_dictunpack16): Likewise. (imm5_operand_dictunpack32): Likewise. (imm2_operand): Likewise. * doc/invoke.texi (SPARC Options): Document -mvis4b. * doc/extend.texi (SPARC VIS Built-in Functions): Document the ditunpack* and fpcmp*shl builtins. * config.gcc: Handle m8 in --with-{cpu,tune} options. * config.in: Add HAVE_AS_SPARC6 define. * config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC M8. * config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for TARGET_CPU_m8. (ASM_CPU32_DEFAUILT_SPEC): Likewise. (CPP_CPU_SPEC): Handle m8. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_M8. * config/sparc/sparc.c (m8_costs): New struct. (sparc_option_override): Handle TARGET_CPU_m8. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. * config/sparc/sparc.h (TARGET_CPU_m8): Define. (CPP_CPU64_DEFAULT_SPEC): Define for M8. (ASM_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle M8. (ASM_CPU_SPEC): Likewise. (AS_M8_FLAG): Define. * config/sparc/sparc.md: Add m8 to the cpu attribute. * config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets. * configure.ac (HAVE_AS_SPARC6): Check for assembler support for M8 instructions. * configure: Regenerate. * doc/invoke.texi (SPARC Options): Document -mcpu=m8 and -mtune=m8. * config/sparc/niagara7.md: Rework the DFA scheduler to use insn subtypes. * config/sparc/sparc.md: Remove the `v3pipe' insn attribute. ("*movdi_insn_sp32"): Do not set v3pipe. ("*movsi_insn"): Likewise. ("*movdi_insn_sp64"): Likewise. ("*movsf_insn"): Likewise. ("*movdf_insn_sp32"): Likewise. ("*movdf_insn_sp64"): Likewise. ("*zero_extendsidi2_insn_sp64"): Likewise. ("*sign_extendsidi2_insn"): Likewise. ("*mov<VM32:mode>_insn"): Likewise. ("*mov<VM64:mode>_insn_sp64"): Likewise. ("*mov<VM64:mode>_insn_sp32"): Likewise. ("<plusminus_insn><VADDSUB:mode>3"): Likewise. ("<vlop:code><VL:mode>3"): Likewise. ("*not_<vlop:code><VL:mode>3"): Likewise. ("*nand<VL:mode>_vis"): Likewise. ("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise. ("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise. ("one_cmpl<VL:mode>2"): Likewise. ("faligndata<VM64:mode>_vis"): Likewise. ("alignaddrsi_vis"): Likewise. ("alignaddrdi_vis"): Likweise. ("alignaddrlsi_vis"): Likewise. ("alignaddrldi_vis"): Likewise. ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. ("bmaskdi_vis"): Likewise. ("bmasksi_vis"): Likewise. ("bshuffle<VM64:mode>_vis"): Likewise. ("cmask8<P:mode>_vis"): Likewise. ("cmask16<P:mode>_vis"): Likewise. ("cmask32<P:mode>_vis"): Likewise. ("pdistn<P:mode>_vis"): Likewise. ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. * config/sparc/sparc.md ("subtype"): New insn attribute. ("*wrgsr_sp64"): Set insn subtype. ("*rdgsr_sp64"): Likewise. ("alignaddrsi_vis"): Likewise. ("alignaddrdi_vis"): Likewise. ("alignaddrlsi_vis"): Likewise. ("alignaddrldi_vis"): Likewise. ("<plusminus_insn><VADDSUB:mode>3"): Likewise. ("fexpand_vis"): Likewise. ("fpmerge_vis"): Likewise. ("faligndata<VM64:mode>_vis"): Likewise. ("bshuffle<VM64:mode>_vis"): Likewise. ("cmask8<P:mode>_vis"): Likewise. ("cmask16<P:mode>_vis"): Likewise. ("cmask32<P:mode>_vis"): Likewise. ("fchksm16_vis"): Likewise. ("v<vis3_shift_patname><GCM:mode>3"): Likewise. ("fmean16_vis"): Likewise. ("fp<plusminus_insn>64_vis"): Likewise. ("<plusminus_insn>v8qi3"): Likewise. ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise. ("<vis4_minmax_patname><VMMAX:mode>3"): Likewise. ("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise. ("<vis3_addsub_ss_patname>v8qi3"): Likewise. ("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise. ("*movqi_insn"): Likewise. ("*movhi_insn"): Likewise. ("*movsi_insn"): Likewise. ("movsi_pic_gotdata_op"): Likewise. ("*movdi_insn_sp32"): Likewise. ("*movdi_insn_sp64"): Likewise. ("movdi_pic_gotdata_op"): Likewise. ("*movsf_insn"): Likewise. ("*movdf_insn_sp32"): Likewise. ("*movdf_insn_sp64"): Likewise. ("*zero_extendhisi2_insn"): Likewise. ("*zero_extendqihi2_insn"): Likewise. ("*zero_extendqisi2_insn"): Likewise. ("*zero_extendqidi2_insn"): Likewise. ("*zero_extendhidi2_insn"): Likewise. ("*zero_extendsidi2_insn_sp64"): Likewise. ("ldfsr"): Likewise. ("prefetch_64"): Likewise. ("prefetch_32"): Likewise. ("tie_ld32"): Likewise. ("tie_ld64"): Likewise. ("*tldo_ldub_sp32"): Likewise. ("*tldo_ldub1_sp32"): Likewise. ("*tldo_ldub2_sp32"): Likewise. ("*tldo_ldub_sp64"): Likewise. ("*tldo_ldub1_sp64"): Likewise. ("*tldo_ldub2_sp64"): Likewise. ("*tldo_ldub3_sp64"): Likewise. ("*tldo_lduh_sp32"): Likewise. ("*tldo_lduh1_sp32"): Likewise. ("*tldo_lduh_sp64"): Likewise. ("*tldo_lduh1_sp64"): Likewise. ("*tldo_lduh2_sp64"): Likewise. ("*tldo_lduw_sp32"): Likewise. ("*tldo_lduw_sp64"): Likewise. ("*tldo_lduw1_sp64"): Likewise. ("*tldo_ldx_sp64"): Likewise. ("*mov<VM32:mode>_insn"): Likewise. ("*mov<VM64:mode>_insn_sp64"): Likewise. ("*mov<VM64:mode>_insn_sp32"): Likewise. * config/sparc/sparc.md ("type"): New insn type viscmp. ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to viscmp. ("fpcmp<gcond:code>8<P:mode>_vis"): Likewise. ("fucmp<gcond:code>8<P:mode>_vis"): Likewise. ("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. * config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle viscmp. ("n7_vis_logical_11cycle"): Likewise. * config/sparc/niagara4.md ("n4_vis_logical"): Likewise. * config/sparc/niagara2.md ("niag3_vis": Likewise. * config/sparc/niagara.md ("niag_vis"): Likewise. * config/sparc/ultra3.md ("us3_fga"): Likewise. * config/sparc/ultra1_2.md ("us1_fga_double"): Likewise. * config/sparc/sparc.md: New instruction type `bmask'. (bmaskdi_vis): Use the `bmask' type. (bmasksi_vis): Likewise. * config/sparc/ultra3.md (us3_array): Likewise. * config/sparc/niagara7.md (n7_array): Likewise. * config/sparc/niagara4.md (n4_array): Likewise. * config/sparc/niagara2.md (niag2_vis): Likewise. (niag3_vis): Likewise. * config/sparc/niagara.md (niag_vis): Likewise. gcc/testsuite/ChangeLog: * gcc.target/sparc/dictunpack.c: New file. * gcc.target/sparc/fpcmpdeshl.c: Likewise. * gcc.target/sparc/fpcmpshl.c: Likewise. * gcc.target/sparc/fpcmpurshl.c: Likewise. * gcc.target/sparc/fpcmpushl.c: Likewise. From-SVN: r250049
2017-07-06rs6000.c (union_defs, [...]): Move all code related to p8 swap optimizations ↵Aaron Sawdey1-2/+2
to file rs6000-p8swap.c. 2017-07-06 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> * config/rs6000/rs6000.c (union_defs, union_uses, insn_is_load_p, insn_is_store_p, insn_is_swap_p, const_load_sequence_p, v2df_reduction_p, rtx_is_swappable_p, insn_is_swappable_p, chain_contains_only_swaps, mark_swaps_for_removal, swap_const_vector_halves, adjust_subreg_index, permute_load, permute_store, adjust_extract, adjust_splat, adjust_xxpermdi, adjust_concat, adjust_vperm, handle_special_swappables, replace_swap_with_copy, dump_swap_insn_table, alignment_with_canonical_addr, alignment_mask, find_alignment_op, recombine_lvx_pattern, recombine_stvx_pattern, recombine_lvx_stvx_patterns, rs6000_analyze_swaps, make_pass_analyze_swaps): Move all code related to p8 swap optimizations to file rs6000-p8swap.c. * config/rs6000/rs6000-p8swap.c: New file. * config/rs6000/t-rs6000: Add rule to build rs6000-p8swap.o. * config.gcc: Add rs6000-p8swap.o to extra_objs for powerpc*-*-* and rs6000*-*-* targets. From-SVN: r250040
2017-06-28multiarch support for non-glibc linux systemsSzabolcs Nagy1-0/+10
Current multiarch directory name is always *-linux-gnu* on linux, this patch configures different names for uclibc and musl targets. 2017-06-28 Szabolcs Nagy <szabolcs.nagy@arm.com> * config.gcc (*-linux-musl*): Add t-musl tmake_file. (*-linux-uclibc*): Add t-uclibc tmake_file. * config/t-musl: New. * config/t-uclibc: New. From-SVN: r249745
2017-06-27config.gcc (i*86-wrs-vxworks7): Handle new acceptable triplet.Jerome Lambourg1-2/+9
2017-06-27 Jerome Lambourg <lambourg@adacore.com> gcc/ * config.gcc (i*86-wrs-vxworks7): Handle new acceptable triplet. (x86_64-wrs-vxworks7): Likewise. libgcc/ * config.host (i*86-wrs)vxworks7): Handle new acceptable triplet. (x86_64-wrs-vxworks7): Likewise. From-SVN: r249689
2017-06-26config.gcc (*-*-vxworks*): Add TARGET_VXWORKS7=1 to tm_defines for all ↵Jerome Lambourg1-0/+5
vxworks7 targets. 2017-06-26 Jerome Lambourg <lambourg@adacore.com> Olivier Hainque <hainque@adacore.com> * config.gcc (*-*-vxworks*): Add TARGET_VXWORKS7=1 to tm_defines for all vxworks7 targets. * config/vxworks.h (TARGET_VXWORKS7): If not defined, define to 0. (VXWORKS_ADDITIONAL_CPP_SPEC): Alternative definition for VXWORKS7. (VXWORKS_LIBS_RTP, VXWORKS_LIBS_RTP_DIR): New macros, allowing variations for VX6/VX7 and 32/64bits later on in ... (VXWORKS_LIB_SPEC): Leverage new macros. (VXWORKS_OS_CPP_BUILTINS): Define _VSB_CONFIG_FILE for VXWORKS7, as well as _ALLOW_KEYWORD_MACROS when "inline" is not a keyword. Co-Authored-By: Olivier Hainque <hainque@adacore.com> From-SVN: r249659
2017-06-23rs6000-string.c: (expand_block_clear...Aaron Sawdey1-0/+2
2017-06-23 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> * config/rs6000/rs6000-string.c: (expand_block_clear, do_load_for_compare, select_block_compare_mode, compute_current_alignment, expand_block_compare, expand_strncmp_align_check, expand_strn_compare, expand_block_move, rs6000_output_load_multiple) Move functions related to string/block move/compare to a separate file. * config/rs6000/rs6000.c: Move above functions to rs6000-string.c. * config/rs6000/rs6000-protos.h (rs6000_emit_dot_insn): Add prototype for this function which is now used in two files. * config/rs6000/t-rs6000: Add rule to compile rs6000-string.o. * config.gcc: Add rs6000-string.o to extra_objs for targets powerpc*-*-* and rs6000*-*-*. From-SVN: r249608
2017-06-20config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to arm1176jzf-s.Andreas Tobler1-1/+1
2017-06-20 Andreas Tobler <andreast@gcc.gnu.org> * config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to arm1176jzf-s. From-SVN: r249428
2017-06-16[arm] Rework multilib supportRichard Earnshaw1-1/+1
It looks like the fuchsia port relied on inheriting the multilib rules from the bare-metal port (the t-arm-elf makefile fragment), but that has now been rewritten on the assuption that the base architecture is ARMv4t; fuchsia has a base architecture of ARMv7-a. To account for this, I've cloned the original t-arm-elf rules into a new makefile fragment t-fuchsia and arranged for that to be used when targetting this system. * config/arm/t-fuchsia: New file. * config.gcc (arm*-*-fuchsia*): Use it. From-SVN: r249305
2017-06-16[arm] Rewrite t-aprofile using new selector methodologyRichard Earnshaw1-1/+3
Now that the default FPU is 'auto' we can finally rewrite (and simplify) the rules for mapping compiler options to multilibs. We no-longer need to know the specific CPU, since the driver will construct a suitable -march flag for us; this greatly simplifies the overall logic. This patch rewrites the library list for A-profile cores. We use various Make extention rules to simplify the logic even further. A couple of minor tweaks to the configure script and to the main driver ensures that we always know the setting of -mfloat-abi and -marm/-mthumb. Again, this helps simplify the logic further. The change to arm_target_thumb_only relies on the fact that this routine is only called if neither -marm nor -mthumb has been previously selected or specified by the user. A new testsuite module is added to check the libraries generated. The new tests are only run if the compiler is configured with the relevant multilibs enabled. gcc: * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm rather than NULL. * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. (all_feat_combs): New rule. (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework default libraries. * config/arm/t-aprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilibs.exp: New file. From-SVN: r249296
2017-06-16[arm] Force a CPU default in the config args defaultsRichard Earnshaw1-3/+6
Currently if the user does not specify a default CPU or architecture the compiler provieds no default values in the spec defaults. We can try to work from TARGET_CPU_DEFAULT but pulling that into the driver is a bit crufty and doesn't really work well with the general spec-processing model. A better way is to ensure that with_cpu is always set appropirately during configure. To avoid problems with the multilib fragment processing we defer this until after we have processed any required fragments before selecting the default. * config.gcc (arm*-*-*): Ensure both target_cpu_cname and with_cpu are set after handling multilib fragments. Set target_cpu_default2 from with_cpu. From-SVN: r249291
2017-06-16[arm] Allow new extended syntax CPU and architectureRichard Earnshaw1-3/+3
This patch extends support for the new extended-style architecture strings to configure and the target default options. We validate any options passed by the user to configure against the permitted extensions for that CPU or architecture. * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real cpu name. (arm*-*-*): Set target_cpu_default2 to a quoted string. * config/arm/parsecpu.awk (check_cpu): Validate any extension options. (check_arch): Likewise. * config/arm/arm.c (arm_configure_build_target): Handle TARGET_CPU_DEFAULT being a string constant. Scan any feature options in the default. From-SVN: r249290
2017-06-12config.gcc (*-*-vxworks*): Set use_gcc_stdint to "provide".Doug Rupp1-0/+2
2017-06-12 Doug Rupp <rupp@adacore.com> gcc/ * config.gcc (*-*-vxworks*): Set use_gcc_stdint to "provide". Append vxworks-stdint.h to the tm_file list. * config/vxworks-stdint.h: New file. fixincludes/ * inclhack.def (AAB_vxworks_stdint): Remove hack. * fixincl.x: Regenerate. From-SVN: r249121
2017-06-12rs6000: Remove e500.h from config.gcc some moreSegher Boessenkool1-10/+10
* config.gcc: Remove rs6000/e500.h from tm_file for all targets. From-SVN: r249117
2017-06-07rs6000: Remove spe.md, spe.h, linuxspe.hSegher Boessenkool1-2/+2
* config.gcc (powerpc*-*-*): Don't add spe.h to extra_headers. (powerpc*-linux*spe*): Use ${cpu_type} instead of rs6000. * config/rs6000/linuxspe.h: Delete file. * config/rs6000/rs6000.md: Don't include spe.md. * config/rs6000/spe.h: Delete file. * config/rs6000/spe.md: Delete file. * config/rs6000/t-rs6000: Remove spe.md. From-SVN: r248983
2017-05-24Split off powerpcspe from rs6000 portSegher Boessenkool1-8/+41
* config/powerpcspe: New port. Files are copied from the rs6000 port, with "rs6000" in filenames replaced by "powerpcspe". * config.gcc (powerpc*-*-*spe*): New. (powerpc-*-eabispe*): Use ${cpu_type} instead of hardcoded pathnames. (powerpc-*-rtems*spe*): New. (powerpc*-*-linux*spe*): New. (powerpc-wrs-vxworksspe): New. (powerpc*-*-*, rs6000-*-*): Use ${cpu_type}. (misc flags) [powerpc*-*-*, rs6000-*-*): Use ${cpu_type}. * config.host (powerpc*-*-*spe*): New. From-SVN: r248429
2017-05-12config.gcc (powerpc*-*-*): Add bmi2intrin.h, bmiintrin.h, and x86intrin.hSteven Munroe1-1/+4
[gcc] 2017-05-12 Steven Munroe <munroesj@gcc.gnu.org> * config.gcc (powerpc*-*-*): Add bmi2intrin.h, bmiintrin.h, and x86intrin.h * config/rs6000/bmiintrin.h: New file. * config/rs6000/bmi2intrin.h: New file. * config/rs6000/x86intrin.h: New file. [gcc/testsuite] 2017-05-12 Steven Munroe <munroesj@gcc.gnu.org> * gcc.target/powerpc/bmi-andn-1.c: New file * gcc.target/powerpc/bmi-andn-2.c: New file. * gcc.target/powerpc/bmi-bextr-1.c: New file. * gcc.target/powerpc/bmi-bextr-2.c: New file. * gcc.target/powerpc/bmi-bextr-4.c: New file. * gcc.target/powerpc/bmi-bextr-5.c: New file. * gcc.target/powerpc/bmi-blsi-1.c: New file. * gcc.target/powerpc/bmi-blsi-2.c: New file. * gcc.target/powerpc/bmi-blsmsk-1.c: new file. * gcc.target/powerpc/bmi-blsmsk-2.c: New file. * gcc.target/powerpc/bmi-blsr-1.c: New file. * gcc.target/powerpc/bmi-blsr-2.c: New File. * gcc.target/powerpc/bmi-check.h: New File. * gcc.target/powerpc/bmi-tzcnt-1.c: new file. * gcc.target/powerpc/bmi-tzcnt-2.c: New file. * gcc.target/powerpc/bmi2-bzhi32-1.c: New file. * gcc.target/powerpc/bmi2-bzhi64-1.c: New file. * gcc.target/powerpc/bmi2-bzhi64-1a.c: New file. * gcc.target/powerpc/bmi2-check.h: New file. * gcc.target/powerpc/bmi2-mulx32-1.c: New file. * gcc.target/powerpc/bmi2-mulx32-2.c: New file. * gcc.target/powerpc/bmi2-mulx64-1.c: New file. * gcc.target/powerpc/bmi2-mulx64-2.c: New file. * gcc.target/powerpc/bmi2-pdep32-1.c: New file. * gcc.target/powerpc/bmi2-pdep64-1.c: New file. * gcc.target/powerpc/bmi2-pext32-1.c: New File. * gcc.target/powerpc/bmi2-pext64-1.c: New file. * gcc.target/powerpc/bmi2-pext64-1a.c: New File. From-SVN: r247988
2017-05-08Define TM_MULTILIB_CONFIG for ARM multilibThomas Preud'homme1-1/+2
TM_MULTILIB_CONFIG is not set in config.gcc when building with multilib for arm targets, leading to config/arm/t-multilib not including any of the files (t-aprofile and t-rmprofile) definining the architecture and FPU to build multilib for. This patch fixes that by setting TM_MULTILIB_CONFIG to with_multilib_list's value after it has been checked. It also fix a trailing whitespace issue. 2017-05-08 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config.gcc (arm*-*-*): Set TM_MULTILIB_CONFIG from with_multilib_list after it has been checked. From-SVN: r247741
2017-05-05* config.gcc (arm*-*-*): Add missing 'fi'.Nathan Sidwell1-0/+1
From-SVN: r247650
2017-05-05[ARM] Allow combination of aprofile and rmprofile multilibsThomas Preud'homme1-28/+12
2017-05-05 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config.gcc: Allow combinations of aprofile and rmprofile values for --with-multilib-list. * config/arm/t-multilib: New file. * config/arm/t-aprofile: Remove initialization of MULTILIB_* variables. Remove setting of ISA and floating-point ABI in MULTILIB_OPTIONS and MULTILIB_DIRNAMES. Set architecture and FPU in MULTI_ARCH_OPTS_A and MULTI_ARCH_DIRS_A rather than MULTILIB_OPTIONS and MULTILIB_DIRNAMES respectively. Add comment to introduce all matches. Add architecture matches for marvel-pj4 and generic-armv7-a CPU options. * config/arm/t-rmprofile: Likewise except for the matches changes. * doc/install.texi (--with-multilib-list): Document the combination of aprofile and rmprofile values and warn about pitfalls in doing that. From-SVN: r247646
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