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gcc/ChangeLog:
* config.gcc: add loongarch*-elf target.
* config/loongarch/elf.h: New file.
Link against newlib by default.
libgcc/ChangeLog:
* config.host: add loongarch*-elf target.
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LoongArch processors may not support memory accesses without natural
alignments. Building libraries with -mstrict-align may help with
toolchain binary compatiblity and performance on these implementations
(e.g. Loongson 2K1000LA).
No significant performance degredation is observed on current mainstream
LoongArch processors when the option is enabled.
gcc/ChangeLog:
* config.gcc: use -mstrict-align for building libraries
if --with-strict-align-lib is given.
* doc/install.texi: likewise.
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The configure script and the GCC driver are updated so that
it is easier to customize and control GCC builds for targeting
different LoongArch implementations.
* Make --with-abi obsolete, since it might cause different default ABI
under the same target triplet, which is undesirable. The default ABI
is now purely decided by the target triplet.
* Support options for LoongArch SIMD extensions:
new configure options --with-simd={none,lsx,lasx};
new compiler option -msimd={none,lsx,lasx};
new driver options -m[no]-l[a]sx.
* Enforce the priority of configuration paths (for <parm>={fpu,tune,simd}):
-m<parm> > -march-implied > --with-<parm> > --with-arch-implied.
* Allow the user to control the compiler options used when building
GCC libraries for each multilib variant via --with-multilib-list
and --with-multilib-default. This could become more useful when
we have 32-bit support later.
Example 1: the following configure option
--with-multilib-list=lp64d/la464/mno-strict-align/msimd=lsx,lp64s/mfpu=32
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-mabi=ABI -march=ARCH a list of other options
(mandatory) (optional) (optional)
builds two sets of libraries:
1. lp64d/base ABI (built with "-march=la464 -mno-strict-align -msimd=lsx")
2. lp64s/base ABI (built with "-march=abi-default -mfpu=32")
Example 2: the following 3 configure options
--with-arch=loongarch64
--with-multilib-list=lp64d,lp64f,lp64s/la464
--with-multilib-default=fixed/mno-strict-align/mfpu=64
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-march=ARCH a list of other options
(optional) (optional)
is equivalent to (in terms of building libraries):
--with-multilib-list=\
lp64d/loongarch64/mno-strict-align/mfpu=64,\
lp64f/loongarch64/mno-strict-align/mfpu=64,\
lp64s/la464
Note:
1. the GCC driver and compiler proper does not support
"-march=fixed". "fixed" that appear here acts as a placeholder for
"use whatever ARCH in --with-arch=ARCH" (or the default value
of --with-arch=ARCH if --with-arch is not explicitly configured).
2. if the ARCH part is omitted, "-march=abi-default"
is used for building all library variants, which
practically means enabling the minimal ISA features
that can support the given ABI.
ChangeLog:
* config-ml.in: Do not build the multilib library variant
that is duplicate with the toplevel one.
gcc/ChangeLog:
* config.gcc: Make --with-abi= obsolete, decide the default ABI
with target triplet. Allow specifying multilib library build
options with --with-multilib-list and --with-multilib-default.
* config/loongarch/t-linux: Likewise.
* config/loongarch/genopts/loongarch-strings: Likewise.
* config/loongarch/loongarch-str.h: Likewise.
* doc/install.texi: Likewise.
* config/loongarch/genopts/loongarch.opt.in: Introduce
-m[no-]l[a]sx options. Only process -m*-float and
-m[no-]l[a]sx in the GCC driver.
* config/loongarch/loongarch.opt: Likewise.
* config/loongarch/la464.md: Likewise.
* config/loongarch/loongarch-c.cc: Likewise.
* config/loongarch/loongarch-cpu.cc: Likewise.
* config/loongarch/loongarch-cpu.h: Likewise.
* config/loongarch/loongarch-def.c: Likewise.
* config/loongarch/loongarch-def.h: Likewise.
* config/loongarch/loongarch-driver.cc: Likewise.
* config/loongarch/loongarch-driver.h: Likewise.
* config/loongarch/loongarch-opts.cc: Likewise.
* config/loongarch/loongarch-opts.h: Likewise.
* config/loongarch/loongarch.cc: Likewise.
* doc/invoke.texi: Likewise.
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Hi, currently RVV vectorization only support picking LMUL according to
compile option --param=riscv-autovec-lmul= which is no ideal.
Compiler should be able to pick optimal LMUL/vectorization factor to
vectorize the loop according to the loop_vec_info and SSA-based register
pressure analysis.
Now, I figure out current GCC cost model provide the approach that we
can choose LMUL/vectorization factor by adjusting the COST.
This patch is just add the minimum COST model framework which is still
applying the default cost model (No vector codes changed from before).
Regression all pased and no difference.
gcc/ChangeLog:
* config.gcc: Add vector cost model framework for RVV.
* config/riscv/riscv.cc (riscv_vectorize_create_costs): Ditto.
(TARGET_VECTORIZE_CREATE_COSTS): Ditto.
* config/riscv/t-riscv: Ditto.
* config/riscv/riscv-vector-costs.cc: New file.
* config/riscv/riscv-vector-costs.h: New file.
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This patch updates the support for the BPF CO-RE builtins
__builtin_preserve_access_index and __builtin_preserve_field_info,
and adds support for the CO-RE builtins __builtin_btf_type_id,
__builtin_preserve_type_info and __builtin_preserve_enum_value.
These CO-RE relocations are now converted to __builtin_core_reloc which
abstracts all of the original builtins in a polymorphic relocation
specific builtin.
The builtin processing is now split in 2 stages, the first (pack) is
executed right after the front-end and the second (process) right before
the asm output.
In expand pass the __builtin_core_reloc is converted to a
unspec:UNSPEC_CORE_RELOC rtx entry.
The data required to process the builtin is now collected in the packing
stage (after front-end), not allowing the compiler to optimize any of
the relevant information required to compose the relocation when
necessary.
At expansion, that information is recovered and CTF/BTF is queried to
construct the information that will be used in the relocation.
At this point the relocation is added to specific section and the
builtin is expanded to the expected default value for the builtin.
In order to process __builtin_preserve_enum_value, it was necessary to
hook the front-end to collect the original enum value reference.
This is needed since the parser folds all the enum values to its
integer_cst representation.
More details can be found within the core-builtins.cc.
Regtested in host x86_64-linux-gnu and target bpf-unknown-none.
gcc/ChangeLog:
PR target/107844
PR target/107479
PR target/107480
PR target/107481
* config.gcc: Added core-builtins.cc and .o files.
* config/bpf/bpf-passes.def: Removed file.
* config/bpf/bpf-protos.h (bpf_add_core_reloc,
bpf_replace_core_move_operands): New prototypes.
* config/bpf/bpf.cc (enum bpf_builtins, is_attr_preserve_access,
maybe_make_core_relo, bpf_core_field_info, bpf_core_compute,
bpf_core_get_index, bpf_core_new_decl, bpf_core_walk,
bpf_is_valid_preserve_field_info_arg, is_attr_preserve_access,
handle_attr_preserve, pass_data_bpf_core_attr, pass_bpf_core_attr):
Removed.
(def_builtin, bpf_expand_builtin, bpf_resolve_overloaded_builtin): Changed.
* config/bpf/bpf.md (define_expand mov<MM:mode>): Changed.
(mov_reloc_core<mode>): Added.
* config/bpf/core-builtins.cc (struct cr_builtin, enum
cr_decision struct cr_local, struct cr_final, struct
core_builtin_helpers, enum bpf_plugin_states): Added types.
(builtins_data, core_builtin_helpers, core_builtin_type_defs):
Added variables.
(allocate_builtin_data, get_builtin-data, search_builtin_data,
remove_parser_plugin, compare_same_kind, compare_same_ptr_expr,
compare_same_ptr_type, is_attr_preserve_access, core_field_info,
bpf_core_get_index, compute_field_expr,
pack_field_expr_for_access_index, pack_field_expr_for_preserve_field,
process_field_expr, pack_enum_value, process_enum_value, pack_type,
process_type, bpf_require_core_support, make_core_relo, read_kind,
kind_access_index, kind_preserve_field_info, kind_enum_value,
kind_type_id, kind_preserve_type_info, get_core_builtin_fndecl_for_type,
bpf_handle_plugin_finish_type, bpf_init_core_builtins,
construct_builtin_core_reloc, bpf_resolve_overloaded_core_builtin,
bpf_expand_core_builtin, bpf_add_core_reloc,
bpf_replace_core_move_operands): Added functions.
* config/bpf/core-builtins.h (enum bpf_builtins): Added.
(bpf_init_core_builtins, bpf_expand_core_builtin,
bpf_resolve_overloaded_core_builtin): Added functions.
* config/bpf/coreout.cc (struct bpf_core_extra): Added.
(bpf_core_reloc_add, output_asm_btfext_core_reloc): Changed.
* config/bpf/coreout.h (bpf_core_reloc_add) Changed prototype.
* config/bpf/t-bpf: Added core-builtins.o.
* doc/extend.texi: Added documentation for new BPF builtins.
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The .spec files used for linking on ppc-vx6, when the rtp-smp runtime
is selected, add -L flags for /lib_smp/ and /lib/.
There was a problem, though: although /lib_smp/ and /lib/ were to be
searched in this order, and the specs files do that correctly, the
compiler would search /lib/ first regardless, because
STARTFILE_PREFIX_SPEC said so, and specs files cannot override that.
With this patch, we arrange for the presence of -msmp to affect
STARTFILE_PREFIX_SPEC, so that the compiler searches /lib_smp/ rather
than /lib/ for crt files. A separate patch for GNAT ensures that when
the rtp-smp runtime is selected, -msmp is passed to the compiler
driver for linking, along with the --specs flags.
for gcc/ChangeLog
* config/vxworks-smp.opt: New. Introduce -msmp.
* config.gcc: Enable it on powerpc* vxworks prior to 7r*.
* config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Choose
lib_smp when -msmp is present in the command line.
* doc/invoke.texi: Document it.
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake,
Arrow Lake and Arrow Lake S.
* common/config/i386/i386-common.cc:
(processor_name): Add arrowlake.
(processor_alias_table): Add arrow lake, arrow lake s and lunar
lake.
* common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S.
* config.gcc: Add -march=arrowlake and -march=arrowlake-s.
* config/i386/driver-i386.cc (host_detect_local_cpu): Handle
arrowlake-s.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add
arrowlake.
* config/i386/i386-options.cc (m_ARROWLAKE): New.
(processor_cost_table): Add arrowlake.
* config/i386/i386.h (enum processor_type):
Add PROCESSOR_ARROWLAKE.
* config/i386/x86-tune.def: Add m_ARROWLAKE.
* doc/extend.texi: Add arrowlake and arrowlake-s.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv16.C: Add arrowlake and arrowlake-s.
* gcc.target/i386/funcspec-56.inc: Handle new march.
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detech SM4.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET,
OPTION_MASK_ISA2_SM4_UNSET): New.
(OPTION_MASK_ISA2_AVX_UNSET): Add SM4.
(ix86_handle_option): Handle -msm4.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_SM4.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
sm4.
* config.gcc: Add sm4intrin.h.
* config/i386/cpuid.h (bit_SM4): New.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__SM4__.
* config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4).
* config/i386/i386-options.cc (isa2_opts): Add -msm4.
(ix86_valid_target_attribute_inner_p): Handle sm4.
* config/i386/i386.opt: Add option -msm4.
* config/i386/immintrin.h: Include sm4intrin.h
* config/i386/sse.md (vsm4key4_<mode>): New define insn.
(vsm4rnds4_<mode>): Ditto.
* doc/extend.texi: Document sm4.
* doc/invoke.texi: Document -msm4.
* doc/sourcebuild.texi: Document target sm4.
* config/i386/sm4intrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -msm4.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -msm4.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add sm4.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp (check_effective_target_sm4): New.
* gcc.target/i386/sm4-1.c: New test.
* gcc.target/i386/sm4-check.h: Ditto.
* gcc.target/i386/sm4key4-2.c: Ditto.
* gcc.target/i386/sm4rnds4-2.c: Ditto.
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect SHA512.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET,
OPTION_MASK_ISA2_SHA512_UNSET): New.
(OPTION_MASK_ISA2_AVX_UNSET): Add SHA512.
(ix86_handle_option): Handle -msha512.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_SHA512.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
sha512.
* config.gcc: Add sha512intrin.h.
* config/i386/cpuid.h (bit_SHA512): New.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__SHA512__.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI.
* config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512).
* config/i386/i386-options.cc (isa2_opts): Add -msha512.
(ix86_valid_target_attribute_inner_p): Handle sha512.
* config/i386/i386.opt: Add option -msha512.
* config/i386/immintrin.h: Include sha512intrin.h.
* config/i386/sse.md (vsha512msg1): New define insn.
(vsha512msg2): Ditto.
(vsha512rnds2): Ditto.
* doc/extend.texi: Document sha512.
* doc/invoke.texi: Document -msha512.
* doc/sourcebuild.texi: Document target sha512.
* config/i386/sha512intrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -msha512.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -msha512.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add sha512.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp (check_effective_target_sha512): New.
* gcc.target/i386/sha512-1.c: New test.
* gcc.target/i386/sha512-check.h: Ditto.
* gcc.target/i386/sha512msg1-2.c: Ditto.
* gcc.target/i386/sha512msg2-2.c: Ditto.
* gcc.target/i386/sha512rnds2-2.c: Ditto.
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect SM3.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET,
OPTION_MASK_ISA2_SM3_UNSET): New.
(OPTION_MASK_ISA2_AVX_UNSET): Add SM3.
(ix86_handle_option): Handle -msm3.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_SM3.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
SM3.
* config.gcc: Add sm3intrin.h
* config/i386/cpuid.h (bit_SM3): New.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__SM3__.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
V4SI_FTYPE_V4SI_V4SI_V4SI_INT.
* config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3).
* config/i386/i386-options.cc (isa2_opts): Add -msm3.
(ix86_valid_target_attribute_inner_p): Handle sm3.
* config/i386/i386.opt: Add option -msm3.
* config/i386/immintrin.h: Include sm3intrin.h.
* config/i386/sse.md (vsm3msg1): New define insn.
(vsm3msg2): Ditto.
(vsm3rnds2): Ditto.
* doc/extend.texi: Document sm3.
* doc/invoke.texi: Document -msm3.
* doc/sourcebuild.texi: Document target sm3.
* config/i386/sm3intrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -msm3.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Add new define for immediate.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -msm3.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add sm3.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp (check_effective_target_sm3): New.
* gcc.target/i386/sm3-1.c: New test.
* gcc.target/i386/sm3-check.h: Ditto.
* gcc.target/i386/sm3msg1-2.c: Ditto.
* gcc.target/i386/sm3msg2-2.c: Ditto.
* gcc.target/i386/sm3rnds2-2.c: Ditto.
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gcc/ChangeLog
* common/config/i386/cpuinfo.h (get_available_features): Detect
avxvnniint16.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVXVNNIINT16_SET): New.
(OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto.
(ix86_handle_option): Handle -mavxvnniint16.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVXVNNIINT16.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxvnniint16.
* config.gcc: Add avxvnniint16.h.
* config/i386/avxvnniint16intrin.h: New file.
* config/i386/cpuid.h (bit_AVXVNNIINT16): New.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXVNNIINT16__.
* config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16.
(ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h.
* config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16).
* config/i386/i386.opt: Add option -mavxvnniint16.
* config/i386/immintrin.h: Include avxvnniint16.h.
* config/i386/sse.md
(vpdp<vpdpwprodtype>_<mode>): New define_insn.
* doc/extend.texi: Document avxvnniint16.
* doc/invoke.texi: Document -mavxvnniint16.
* doc/sourcebuild.texi: Document target avxvnniint16.
gcc/testsuite/ChangeLog
* g++.dg/other/i386-2.C: Add -mavxvnniint16.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-check.h: Add avxvnniint16 check.
* gcc.target/i386/sse-12.c: Add -mavxvnniint16.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avxvnniint16): New.
* gcc.target/i386/avxvnniint16-1.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwusd-2.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwusds-2.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwsud-2.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwsuds-2.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwuud-2.c: Ditto.
* gcc.target/i386/avxvnniint16-vpdpwuuds-2.c: Ditto.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_intel_cpu): Handle Granite Rapids D.
* common/config/i386/i386-common.cc:
(processor_alias_table): Add graniterapids-d.
* common/config/i386/i386-cpuinfo.h
(enum processor_subtypes): Add INTEL_COREI7_GRANITERAPIDS_D.
* config.gcc: Add -march=graniterapids-d.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Handle graniterapids-d.
* config/i386/i386.h: (PTA_GRANITERAPIDS_D): New.
* doc/extend.texi: Add graniterapids-d.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv16.C: Add graniterapids-d.
* gcc.target/i386/funcspec-56.inc: Handle new march.
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POSIX sh does not support the == for string comparisons, use = instead.
The gen_directive_tests script uses a bash shebang so == does work, but
there's no reason this script can't just use the more portable form
anyway.
PR bootstrap/105831
gcc/ChangeLog:
* config.gcc: Use = operator instead of ==.
gcc/testsuite/ChangeLog:
* gcc.test-framework/gen_directive_tests: Use = operator instead
of ==.
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This patch introduces the new MVE intrinsics framework, heavily
inspired by the SVE one in the aarch64 port.
Like the MVE intrinsic types implementation, the intrinsics framework
defines functions via a new pragma in arm_mve.h. A boolean parameter
is used to pass true when __ARM_MVE_PRESERVE_USER_NAMESPACE is
defined, and false when it is not, allowing for non-prefixed intrinsic
functions to be conditionally defined.
Future patches will build on this framework by adding new intrinsic
functions and adding the features needed to support them.
Differences compared to the aarch64/SVE port include:
- when present, the predicate argument is the last one with MVE (the
first one with SVE)
- when using merging predicates ("_m" suffix), the "inactive" argument
(if any) is inserted in the first position
- when using merging predicates ("_m" suffix), some function do not
have the "inactive" argument, so we maintain an exception-list
- MVE intrinsics dealing with floating-point require the FP extension,
while SVE may support different extensions
- regarding global state, MVE does not have any prefetch intrinsic, so
we do not need a flag for this
- intrinsic names can be prefixed with "__arm", depending on whether
preserve_user_namespace is true or false
- parse_signature: the maximum number of arguments is now a parameter,
this helps detecting an overflow with a new assert.
- suffixes and overloading can be controlled using
explicit_mode_suffix_p and skip_overload_p in addition to
explicit_type_suffix_p
At this implemtation stage, there are some limitations compared
to aarch64/SVE, which are removed later in the series:
- "offset" mode is not supported yet
- gimple folding is not implemented
2022-09-08 Murray Steele <murray.steele@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
gcc/ChangeLog:
* config.gcc: Add arm-mve-builtins-base.o and
arm-mve-builtins-shapes.o to extra_objs.
* config/arm/arm-builtins.cc (arm_builtin_decl): Handle MVE builtin
numberspace.
(arm_expand_builtin): Likewise
(arm_check_builtin_call): Likewise
(arm_describe_resolver): Likewise.
* config/arm/arm-builtins.h (enum resolver_ident): Add
arm_mve_resolver.
* config/arm/arm-c.cc (arm_pragma_arm): Handle new pragma.
(arm_resolve_overloaded_builtin): Handle MVE builtins.
(arm_register_target_pragmas): Register arm_check_builtin_call.
* config/arm/arm-mve-builtins.cc (class registered_function): New
class.
(struct registered_function_hasher): New struct.
(pred_suffixes): New table.
(mode_suffixes): New table.
(type_suffix_info): New table.
(TYPES_float16): New.
(TYPES_all_float): New.
(TYPES_integer_8): New.
(TYPES_integer_8_16): New.
(TYPES_integer_16_32): New.
(TYPES_integer_32): New.
(TYPES_signed_16_32): New.
(TYPES_signed_32): New.
(TYPES_all_signed): New.
(TYPES_all_unsigned): New.
(TYPES_all_integer): New.
(TYPES_all_integer_with_64): New.
(DEF_VECTOR_TYPE): New.
(DEF_DOUBLE_TYPE): New.
(DEF_MVE_TYPES_ARRAY): New.
(all_integer): New.
(all_integer_with_64): New.
(float16): New.
(all_float): New.
(all_signed): New.
(all_unsigned): New.
(integer_8): New.
(integer_8_16): New.
(integer_16_32): New.
(integer_32): New.
(signed_16_32): New.
(signed_32): New.
(register_vector_type): Use void_type_node for mve.fp-only types when
mve.fp is not enabled.
(register_builtin_tuple_types): Likewise.
(handle_arm_mve_h): New function..
(matches_type_p): Likewise..
(report_out_of_range): Likewise.
(report_not_enum): Likewise.
(report_missing_float): Likewise.
(report_non_ice): Likewise.
(check_requires_float): Likewise.
(function_instance::hash): Likewise
(function_instance::call_properties): Likewise.
(function_instance::reads_global_state_p): Likewise.
(function_instance::modifies_global_state_p): Likewise.
(function_instance::could_trap_p): Likewise.
(function_instance::has_inactive_argument): Likewise.
(registered_function_hasher::hash): Likewise.
(registered_function_hasher::equal): Likewise.
(function_builder::function_builder): Likewise.
(function_builder::~function_builder): Likewise.
(function_builder::append_name): Likewise.
(function_builder::finish_name): Likewise.
(function_builder::get_name): Likewise.
(add_attribute): Likewise.
(function_builder::get_attributes): Likewise.
(function_builder::add_function): Likewise.
(function_builder::add_unique_function): Likewise.
(function_builder::add_overloaded_function): Likewise.
(function_builder::add_overloaded_functions): Likewise.
(function_builder::register_function_group): Likewise.
(function_call_info::function_call_info): Likewise.
(function_resolver::function_resolver): Likewise.
(function_resolver::get_vector_type): Likewise.
(function_resolver::get_scalar_type_name): Likewise.
(function_resolver::get_argument_type): Likewise.
(function_resolver::scalar_argument_p): Likewise.
(function_resolver::report_no_such_form): Likewise.
(function_resolver::lookup_form): Likewise.
(function_resolver::resolve_to): Likewise.
(function_resolver::infer_vector_or_tuple_type): Likewise.
(function_resolver::infer_vector_type): Likewise.
(function_resolver::require_vector_or_scalar_type): Likewise.
(function_resolver::require_vector_type): Likewise.
(function_resolver::require_matching_vector_type): Likewise.
(function_resolver::require_derived_vector_type): Likewise.
(function_resolver::require_derived_scalar_type): Likewise.
(function_resolver::require_integer_immediate): Likewise.
(function_resolver::require_scalar_type): Likewise.
(function_resolver::check_num_arguments): Likewise.
(function_resolver::check_gp_argument): Likewise.
(function_resolver::finish_opt_n_resolution): Likewise.
(function_resolver::resolve_unary): Likewise.
(function_resolver::resolve_unary_n): Likewise.
(function_resolver::resolve_uniform): Likewise.
(function_resolver::resolve_uniform_opt_n): Likewise.
(function_resolver::resolve): Likewise.
(function_checker::function_checker): Likewise.
(function_checker::argument_exists_p): Likewise.
(function_checker::require_immediate): Likewise.
(function_checker::require_immediate_enum): Likewise.
(function_checker::require_immediate_range): Likewise.
(function_checker::check): Likewise.
(gimple_folder::gimple_folder): Likewise.
(gimple_folder::fold): Likewise.
(function_expander::function_expander): Likewise.
(function_expander::direct_optab_handler): Likewise.
(function_expander::get_fallback_value): Likewise.
(function_expander::get_reg_target): Likewise.
(function_expander::add_output_operand): Likewise.
(function_expander::add_input_operand): Likewise.
(function_expander::add_integer_operand): Likewise.
(function_expander::generate_insn): Likewise.
(function_expander::use_exact_insn): Likewise.
(function_expander::use_unpred_insn): Likewise.
(function_expander::use_pred_x_insn): Likewise.
(function_expander::use_cond_insn): Likewise.
(function_expander::map_to_rtx_codes): Likewise.
(function_expander::expand): Likewise.
(resolve_overloaded_builtin): Likewise.
(check_builtin_call): Likewise.
(gimple_fold_builtin): Likewise.
(expand_builtin): Likewise.
(gt_ggc_mx): Likewise.
(gt_pch_nx): Likewise.
(gt_pch_nx): Likewise.
* config/arm/arm-mve-builtins.def(s8): Define new type suffix.
(s16): Likewise.
(s32): Likewise.
(s64): Likewise.
(u8): Likewise.
(u16): Likewise.
(u32): Likewise.
(u64): Likewise.
(f16): Likewise.
(f32): Likewise.
(n): New mode.
(offset): New mode.
* config/arm/arm-mve-builtins.h (MAX_TUPLE_SIZE): New constant.
(CP_READ_FPCR): Likewise.
(CP_RAISE_FP_EXCEPTIONS): Likewise.
(CP_READ_MEMORY): Likewise.
(CP_WRITE_MEMORY): Likewise.
(enum units_index): New enum.
(enum predication_index): New.
(enum type_class_index): New.
(enum mode_suffix_index): New enum.
(enum type_suffix_index): New.
(struct mode_suffix_info): New struct.
(struct type_suffix_info): New.
(struct function_group_info): Likewise.
(class function_instance): Likewise.
(class registered_function): Likewise.
(class function_builder): Likewise.
(class function_call_info): Likewise.
(class function_resolver): Likewise.
(class function_checker): Likewise.
(class gimple_folder): Likewise.
(class function_expander): Likewise.
(get_mve_pred16_t): Likewise.
(find_mode_suffix): New function.
(class function_base): Likewise.
(class function_shape): Likewise.
(function_instance::operator==): New function.
(function_instance::operator!=): Likewise.
(function_instance::vectors_per_tuple): Likewise.
(function_instance::mode_suffix): Likewise.
(function_instance::type_suffix): Likewise.
(function_instance::scalar_type): Likewise.
(function_instance::vector_type): Likewise.
(function_instance::tuple_type): Likewise.
(function_instance::vector_mode): Likewise.
(function_call_info::function_returns_void_p): Likewise.
(function_base::call_properties): Likewise.
* config/arm/arm-protos.h (enum arm_builtin_class): Add
ARM_BUILTIN_MVE.
(handle_arm_mve_h): New.
(resolve_overloaded_builtin): New.
(check_builtin_call): New.
(gimple_fold_builtin): New.
(expand_builtin): New.
* config/arm/arm.cc (TARGET_GIMPLE_FOLD_BUILTIN): Define as
arm_gimple_fold_builtin.
(arm_gimple_fold_builtin): New function.
* config/arm/arm_mve.h: Use new arm_mve.h pragma.
* config/arm/predicates.md (arm_any_register_operand): New predicate.
* config/arm/t-arm: (arm-mve-builtins.o): Add includes.
(arm-mve-builtins-shapes.o): New target.
(arm-mve-builtins-base.o): New target.
* config/arm/arm-mve-builtins-base.cc: New file.
* config/arm/arm-mve-builtins-base.def: New file.
* config/arm/arm-mve-builtins-base.h: New file.
* config/arm/arm-mve-builtins-functions.h: New file.
* config/arm/arm-mve-builtins-shapes.cc: New file.
* config/arm/arm-mve-builtins-shapes.h: New file.
Co-authored-by: Christophe Lyon <christophe.lyon@arm.com
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|
PR target/105525 is a build regression for the vax and lm32 linux
targets present in gcc-12/13/head, where the builds fail due to
unsatisfied references to __INTPTR_TYPE__ and __UINTPTR_TYPE__,
caused by these two targets failing to provide glibc-stdint.h.
Fixed thusly, tested by building crosses, which now succeeds.
Ok for trunk? (Note I don't have commit rights.)
PR target/105525
gcc/
* config.gcc (vax-*-linux*): Add glibc-stdint.h.
(lm32-*-uclinux*): Likewise.
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|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect AMX-COMPLEX.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AMX_COMPLEX_SET,
OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New.
(ix86_handle_option): Handle -mamx-complex.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AMX_COMPLEX.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
amx-complex.
* config.gcc: Add amxcomplexintrin.h.
* config/i386/cpuid.h (bit_AMX_COMPLEX): New.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AMX_COMPLEX__.
* config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX).
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
Handle amx-complex.
* config/i386/i386.opt: Add option -mamx-complex.
* config/i386/immintrin.h: Include amxcomplexintrin.h.
* doc/extend.texi: Document amx-complex.
* doc/invoke.texi: Document -mamx-complex.
* doc/sourcebuild.texi: Document target amx-complex.
* config/i386/amxcomplexintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mamx-complex.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX.
* gcc.target/i386/amx-helper.h: Add amx-complex support.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -mamx-complex.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add amx-complex.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp (check_effective_target_amx_complex): New.
* gcc.target/i386/amxcomplex-asmatt-1.c: New test.
* gcc.target/i386/amxcomplex-asmintel-1.c: Ditto.
* gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto.
* gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto.
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|
The XTheadMemPair ISA extension allows to pair two loads or stores:
* th.ldd (2x LD)
* th.lwd (2x LW)
* th.lwud (2x LWU)
* th.sdd (2x SD)
* th.swd (2x SW)
The displacement of these instructions is quite limited:
* Displacement := imm2 << shamt
* imm2 is a 2-bit unsigned value {0..3}
* shamt is 4 for th.ldd/th.sdd and 3 otherwise
But even with this small displacement we can identify many candidates.
The merge of the two loads/stores is realized in form of peephole2
passes that support instruction reordering.
The CFA expansion (save/restore registers on/from stack) is not
processed by the peephole2 pass and, therefore, needs special-treatment.
Many ideas of this patch are inspired by similar/equal approaches
in other backends.
gcc/ChangeLog:
* config.gcc: Add thead.o to RISC-V extra_objs.
* config/riscv/peephole.md: Add mempair peephole passes.
* config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New
prototype.
(th_mempair_operands_p): Likewise.
(th_mempair_order_operands): Likewise.
(th_mempair_prepare_save_restore_operands): Likewise.
(th_mempair_save_restore_regs): Likewise.
(th_mempair_output_move): Likewise.
* config/riscv/riscv.cc (riscv_save_reg): Move code.
(riscv_restore_reg): Move code.
(riscv_for_each_saved_reg): Add code to emit mempair insns.
* config/riscv/t-riscv: Add thead.cc.
* config/riscv/thead.md (*th_mempair_load_<GPR:mode>2):
New insn.
(*th_mempair_store_<GPR:mode>2): Likewise.
(*th_mempair_load_extendsidi2): Likewise.
(*th_mempair_load_zero_extendsidi2): Likewise.
* config/riscv/thead.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadmempair-1.c: New test.
* gcc.target/riscv/xtheadmempair-2.c: New test.
* gcc.target/riscv/xtheadmempair-3.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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As discussed in the PR, t-cygwin-w64 file has been introduced in 2013
and has one important problem, two different multilib options -m64 and -m32,
but MULTILIB_DIRNAMES with just one word in it.
Before the genmultilib sanity checking was added, my understanding is that
this essentially resulted in effective --disable-multilib,
$ gcc -print-multi-lib
.;
;@m32
$ gcc -print-multi-directory
.
$ gcc -print-multi-directory -m64
.
$ gcc -print-multi-directory -m32
$ gcc -print-multi-os-directory
../lib
$ gcc -print-multi-os-directory -m64
../lib
$ gcc -print-multi-os-directory -m32
../lib32
and because of the way e.g. config-ml.in operates
multidirs=
for i in `${CC-gcc} --print-multi-lib 2>/dev/null`; do
dir=`echo $i | sed -e 's/;.*$//'`
if [ "${dir}" = "." ]; then
true
else
if [ -z "${multidirs}" ]; then
multidirs="${dir}"
else
multidirs="${multidirs} ${dir}"
fi
fi
done
dir was . first time (and so nothing was done) and empty
second time, multidirs empty too, so multidirs was set to empty
like it would be with --disable-multilib.
With the added sanity checking the build fails unless --disable-multilib
is used in configure (dunno whether people usually configure that way
on cygwin).
>From what has been said in the PR, multilibs were not meant to be supported
and e.g. cygwin headers probably aren't ready for it.
So the following patch just removes the file with the (incorrect) multilib
stuff instead of fixing it (say by setting MULTILIB_DIRNAMES to 64 32).
I have no way to test this though, no Windows around, can anyone please
test this? I just would like to get some progress on the P1s we have...
2023-02-22 Jakub Jelinek <jakub@redhat.com>
gcc/ChangeLog:
PR target/107998
* config.gcc (x86_64-*-cygwin*): Don't add i386/t-cygwin-w64 into
$tmake_file.
* config/i386/t-cygwin-w64: Remove.
Signed-off-by: Jonathan Yong <10walls@gmail.com>
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|
Add buildtime option to decide whether will compiler build with `-mmsa` option default.
gcc/ChangeLog:
* config.gcc: add -with-{no-}msa build option.
* config/mips/mips.h: Likewise.
* doc/install.texi: Likewise.
Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
|
|
Multiarch tuple will be coded in file or directory names in
multiarch-aware distros, so one ABI should have only one multiarch
tuple. For example, "--target=loongarch64-linux-gnu --with-abi=lp64s"
and "--target=loongarch64-linux-gnusf" should both set multiarch tuple
to "loongarch64-linux-gnusf". Before this commit,
"--target=loongarch64-linux-gnu --with-abi=lp64s --disable-multilib"
will produce wrong result (loongarch64-linux-gnu).
A recent LoongArch psABI revision mandates "loongarch64-linux-gnu" to be
used for -mabi=lp64d (instead of "loongarch64-linux-gnuf64") for some
non-technical reason [1]. Note that we cannot make
"loongarch64-linux-gnuf64" an alias for "loongarch64-linux-gnu" because
to implement such an alias, we must create thousands of symlinks in the
distro and doing so would be completely unpractical. This commit also
aligns GCC with the revision.
Tested by building cross compilers with --enable-multiarch and multiple
combinations of --target=loongarch64-linux-gnu*, --with-abi=lp64{s,f,d},
and --{enable,disable}-multilib; and run "xgcc --print-multiarch" then
manually verify the result with eyesight.
[1]: https://github.com/loongson/LoongArch-Documentation/pull/80
gcc/ChangeLog:
* config.gcc (triplet_abi): Set its value based on $with_abi,
instead of $target.
(la_canonical_triplet): Set it after $triplet_abi is set
correctly.
* config/loongarch/t-linux (MULTILIB_OSDIRNAMES): Make the
multiarch tuple for lp64d "loongarch64-linux-gnu" (without
"f64" suffix).
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|
I have committed a fix [1] into gcc trunk for a build
issue mentioned in pr108505 and latter received few upstream
comments proposing more robust fix for this issue.
In this patch I'm addressing those comments and sending this
as a followup patch.
gcc/ChangeLog:
2023-01-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/108505
* config.gcc (tm_mlib_file): Define new variable.
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|
Tested by building a toolchain and compiling gnumach for x86_64 [1].
This is the basic version without unwind support which I think is only
required to implement exceptions.
[1]
https://github.com/flavioc/cross-hurd/blob/master/bootstrap-kernel.sh.
gcc/ChangeLog:
* config.gcc: Recognize x86_64-*-gnu* targets and include
i386/gnu64.h.
* config/i386/gnu64.h: Define configuration for new target
including ld.so location.
libgcc/ChangeLog:
* config.host: Recognize x86_64-*-gnu* targets.
* config/i386/gnu-unwind.h: Update to handle __x86_64__ with a
TODO for now.
Signed-off-by: Flavio Cruz <flaviocruz@gmail.com>
|
|
This follows the example of aarch64.
gcc/:
* common/config/riscv/riscv-common.cc
(riscv_option_optimization_table)
[TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable
-fasynchronous-unwind-tables and -funwind-tables.
* config.gcc (riscv*-*-linux*): Define
TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
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|
The SYSROOT_SUFFIX_SPEC works even when multilib is disabled.
So when build no-multilib glibc toolchain and the options are
not same as MULTILIB_DEFAULTS, the sysroot will specify wrong
because the libc will not be installed as such.
This bug causes glibc regression test error:
https://sourceware.org/pipermail/libc-testresults/2023q1/010706.html
The error is:
/scratch/jmyers/glibc-bot/install/compilers/csky-linux-gnuabiv2/csky-glibc-linux-gnuabiv2/bin/ld: cannot find -lc: No such file or directory
gcc/
* config.gcc(csky-*-linux*): Define CSKY_ENABLE_MULTILIB
and only include 'csky/t-csky-linux' when enable multilib.
* config/csky/csky-linux-elf.h(SYSROOT_SUFFIX_SPEC): Don't
define it when disable multilib.
|
|
The patch fixes the build issue for arm-none-eabi target configured with
--with-multilib-list=aprofile,rmprofile, in which case the header file
arm/arm-mlib.h is being included more than once and the toolchain build
is failing (PR108505).
gcc/ChangeLog:
2023-01-24 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/108505
* config.gcc (tm_file): Move the variable out of loop.
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|
This patch adds the support for pacbti multlilib linking by making
"-mbranch-protection=none" as default multilib option for arm-none-eabi
target.
Eg 1.
If the passed command line flags are (without mbranch-protection):
a) -march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto
"-mbranch-protection=none" will be used in the multilib matching.
Eg 2.
If the passed command line flags are (with mbranch-protection):
a) -march=armv8.1-m.main+mve+pacbti -mfloat-abi=hard -mfpu=auto -mbranch-protection=pac-ret
"-mbranch-protection=standard" will be used in the multilib matching.
gcc/ChangeLog:
2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config.gcc ($tm_file): Update variable.
* config/arm/arm-mlib.h: Create new header file.
* config/arm/t-rmprofile (MULTI_ARCH_DIRS_RM): Rename mbranch-protection
multilib arch directory.
(MULTILIB_REUSE): Add multilib reuse rules.
(MULTILIB_MATCHES): Add multilib match rules.
gcc/testsuite/ChangeLog:
2023-01-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/multilib.exp (multilib_config "rmprofile"): Update
tests.
* gcc.target/arm/pac-12.c: New test.
* gcc.target/arm/pac-13.c: Likewise.
* gcc.target/arm/pac-14.c: Likewise.
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|
Hi all,
this patch enables Branch Target Identification Armv8.1-M Mechanism
[1].
This is achieved by using the bti pass made common with Aarch64.
The pass iterates through the instructions and adds the necessary BTI
instructions at the beginning of every function and at every landing
pads targeted by indirect jumps.
Best Regards
Andrea
[1]
<https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
gcc/ChangeLog
2022-04-07 Andrea Corallo <andrea.corallo@arm.com>
* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/aarch-common-protos.h: Declare
'aarch_bti_arch_check'.
* config/arm/arm.cc (aarch_bti_enabled) Update.
(aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c)
(aarch_gen_bti_j, aarch_bti_arch_check): New functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (VUNSPEC_BTI_NOP): New unspec.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Verify arch
compatibility.
(gate): Make use of 'aarch_bti_arch_check'.
* config/arm/arm-passes.def: New file.
* config/aarch64/aarch64.cc (aarch_bti_arch_check): New function.
gcc/testsuite/ChangeLog
2022-04-07 Andrea Corallo <andrea.corallo@arm.com>
* gcc.target/arm/bti-1.c: New testcase.
* gcc.target/arm/bti-2.c: Likewise.
|
|
backend
Hi all,
this patch splits and restructures the aarch64 bti pass code in order
to have it usable by the arm backend as well. These changes have no
functional impact.
Best Regards
Andrea
gcc/Changelog
* config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
'aarch-bti-insert.o'.
* config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
proto.
* config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
(aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
(aarch64_output_mi_thunk)
(aarch64_print_patchable_function_entry)
(aarch64_file_end_indicate_exec_stack): Update renamed function
calls to renamed functions.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
* config/aarch64/t-aarch64 (aarch-bti-insert.o): Update
target.
* config/aarch64/aarch64-bti-insert.cc: Delete.
* config/arm/aarch-bti-insert.cc: New file including and
generalizing code from aarch64-bti-insert.cc.
* config/arm/aarch-common-protos.h: Update.
|
|
Missed it before, it needs to be used when compiling non-multilib.
gcc/
* config.gcc (csky-*-*): Support --with-float=softfp.
|
|
|
|
This patch is to support VSETVL PASS for RVV support.
1.The optimization and performance is guaranteed LCM (Lazy code motion).
2.Base on RTL_SSA framework to gain better optimization chances.
3.Also we do VL/VTYPE, demand information backward propagation across
blocks by RTL_SSA reverse order in CFG.
4.It has been well and fully tested by about 200+ testcases for VLMAX
AVL situation (Only for VLMAX since we don't have an intrinsics to
test non-VLMAX).
5.Will support AVL model in the next patch.
gcc/ChangeLog:
* config.gcc: Add riscv-vsetvl.o.
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Add VSETVL PASS
location.
* config/riscv/riscv-protos.h (make_pass_vsetvl): New function.
(enum avl_type): New enum.
(get_ta): New function.
(get_ma): Ditto.
(get_avl_type): Ditto.
(calculate_ratio): Ditto.
(enum tail_policy): New enum.
(enum mask_policy): Ditto.
* config/riscv/riscv-v.cc (calculate_ratio): New function.
(emit_pred_op): change the VLMAX mov codgen.
(get_ta): New function.
(get_ma): Ditto.
(enum tail_policy): Change enum.
(get_prefer_tail_policy): New function.
(enum mask_policy): Change enum.
(get_prefer_mask_policy): New function.
* config/riscv/t-riscv: Add riscv-vsetvl.o
* config/riscv/vector.md: Adjust attribute and pattern for VSETVL
PASS.
(@vlmax_avl<mode>): Ditto.
(@vsetvl<mode>_no_side_effects): Delete.
(vsetvl_vtype_change_only): New MD pattern.
(@vsetvl_discard_result<mode>): Ditto.
* config/riscv/riscv-vsetvl.cc: New file.
* config/riscv/riscv-vsetvl.h: New file.
|
|
This patch implements the Solaris 11.[0-3] obsoletion just announced in
https://gcc.gnu.org/pipermail/gcc/2022-December/240322.html
Bootstrapped without regressions on Solaris 11.3 (i386-pc-solaris2.11,
sparc-sun-solaris2.11 without and with --enable-obsolete) and 11.4.
2022-12-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
gcc:
* config.gcc: Determine Solaris minor version.
Obsolete *-*-solaris2.11.[0-3]*.
* doc/install.texi (Specific, *-*-solaris2*): Document it.
|
|
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v<x> function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that tries to load
configuration and return an address of an exported object from it.
Define the function xtensa_get_config_v1 that uses xtensa_load_config
to get structure xtensa_config_v1, either dynamically configured or the
default.
Provide essential XCHAL_* configuration parameters as __XCHAL_* built-in
macros. This way it will be possible to use them in libgcc and libc
without need to patch libgcc or libc source for the specific xtensa core
configuration.
gcc/
* config.gcc (xtensa*-*-*): Add xtensa-dynconfig.o to extra_objs.
* config/xtensa/t-xtensa (TM_H): Add xtensa-dynconfig.h.
(xtensa-dynconfig.o): New rule.
* config/xtensa/xtensa-dynconfig.c: New file.
* config/xtensa/xtensa-protos.h (xtensa_get_config_strings): New
declaration.
* config/xtensa/xtensa.h (xtensa-config.h): Replace #include
with xtensa-dynconfig.h
(XCHAL_HAVE_MUL32_HIGH, XCHAL_HAVE_RELEASE_SYNC)
(XCHAL_HAVE_S32C1I, XCHAL_HAVE_THREADPTR)
(XCHAL_HAVE_FP_POSTINC): Drop definitions.
(TARGET_DIV32): Replace with __XCHAL_HAVE_DIV32.
(TARGET_CPU_CPP_BUILTINS): Add new 'builtin' variable and loop
through string array returned by the xtensa_get_config_strings
function call.
include/
* xtensa-dynconfig.h: New file.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_intel_cpu): Handle Grand Ridge.
* common/config/i386/i386-common.cc
(processor_names): Add grandridge.
(processor_alias_table): Ditto.
* common/config/i386/i386-cpuinfo.h:
(enum processor_types): Add INTEL_GRANDRIDGE.
* config.gcc: Add -march=grandridge.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Handle grandridge.
* config/i386/i386-c.cc (ix86_target_macros_internal):
Ditto.
* config/i386/i386-options.cc (m_GRANDRIDGE): New define.
(processor_cost_table): Add grandridge.
* config/i386/i386.h (enum processor_type):
Add PROCESSOR_GRANDRIDGE.
(PTA_GRANDRIDGE): Ditto.
* doc/extend.texi: Add grandridge.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv16.C: Add grandridge.
* gcc.target/i386/funcspec-56.inc: Handle new march.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect raoint.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET,
OPTION_MASK_ISA2_RAOINT_UNSET): New.
(ix86_handle_option): Handle -mraoint.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_RAOINT.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
raoint.
* config.gcc: Add raointintrin.h
* config/i386/cpuid.h (bit_RAOINT): New.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__RAOINT__.
* config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT).
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
Add -mraoint.
* config/i386/sync.md (rao_a<raointop><mode>): New define insn.
* config/i386/i386.opt: Add option -mraoint.
* config/i386/x86gprintrin.h: Include raointintrin.h.
* doc/extend.texi: Document raoint.
* doc/invoke.texi: Document -mraoint.
* doc/sourcebuild.texi: Document target raoint.
* config/i386/raointintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mraoint.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -mraoint.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add raoint target.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp: Add check_effective_target_raoint.
* gcc.target/i386/rao-helper.h: New test.
* gcc.target/i386/raoint-1.c: Ditto.
* gcc.target/i386/raoint-aadd-2.c: Ditto.
* gcc.target/i386/raoint-aand-2.c: Ditto.
* gcc.target/i386/raoint-aor-2.c: Ditto.
* gcc.target/i386/raoint-axor-2.c: Ditto.
* gcc.target/i386/x86gprintrin-1.c: Ditto.
* gcc.target/i386/x86gprintrin-2.c: Ditto.
* gcc.target/i386/x86gprintrin-3.c: Ditto.
* gcc.target/i386/x86gprintrin-4.c: Ditto.
* gcc.target/i386/x86gprintrin-5.c: Ditto.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_intel_cpu): Handle Granite Rapids.
* common/config/i386/i386-common.cc:
(processor_names): Add graniterapids.
(processor_alias_table): Ditto.
* common/config/i386/i386-cpuinfo.h
(enum processor_subtypes): Add INTEL_GRANTIERAPIDS.
* config.gcc: Add -march=graniterapids.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Handle graniterapids.
* config/i386/i386-c.cc (ix86_target_macros_internal):
Ditto.
* config/i386/i386-options.cc (m_GRANITERAPIDS): New.
(processor_cost_table): Add graniterapids.
* config/i386/i386.h (enum processor_type):
Add PROCESSOR_GRANITERAPIDS.
(PTA_GRANITERAPIDS): Ditto.
* doc/extend.texi: Add graniterapids.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv16.C: Add graniterapids.
* gcc.target/i386/funcspec-56.inc: Handle new march.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect PREFETCHI.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_PREFETCHI_SET,
OPTION_MASK_ISA2_PREFETCHI_UNSET): New.
(ix86_handle_option): Handle -mprefetchi.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Add FEATURE_PREFETCHI.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY
for prefetchi.
* config.gcc: Add prfchiintrin.h.
* config/i386/cpuid.h (bit_PREFETCHI): New.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (VOID, PCVOID, INT)
and DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal):
Define __PREFETCHI__.
* config/i386/i386-expand.cc: Handle new builtins.
* config/i386/i386-isa.def (PREFETCHI):
Add DEF_PTA(PREFETCHI).
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Handle prefetchi.
* config/i386/i386.md (prefetchi): New define_insn.
* config/i386/i386.opt: Add option -mprefetchi.
* config/i386/predicates.md (local_func_symbolic_operand):
New predicates.
* config/i386/x86gprintrin.h: Include prfchiintrin.h.
* config/i386/xmmintrin.h (enum _mm_hint): New enum for
prefetchi.
(_mm_prefetch): Handle the highest bit of enum.
* doc/extend.texi: Document prefetchi.
* doc/invoke.texi: Document -mprefetchi.
* doc/sourcebuild.texi: Document target prefetchi.
* config/i386/prfchiintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mprefetchi.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-13.c: Add -mprefetchi.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/x86gprintrin-1.c: Ditto.
* gcc.target/i386/x86gprintrin-2.c: Ditto.
* gcc.target/i386/x86gprintrin-3.c: Ditto.
* gcc.target/i386/x86gprintrin-4.c: Ditto.
* gcc.target/i386/x86gprintrin-5.c: Ditto.
* gcc.target/i386/prefetchi-1.c: New test.
* gcc.target/i386/prefetchi-2.c: Ditto.
* gcc.target/i386/prefetchi-3.c: Ditto.
* gcc.target/i386/prefetchi-4.c: Ditto.
Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
|
|
... after its deprecation in GCC 12.
* Makefile.def: Remove module 'liboffloadmic'.
* Makefile.in: Regenerate.
* configure.ac: Remove 'liboffloadmic' handling.
* configure: Regenerate.
contrib/
* gcc-changelog/git_commit.py (default_changelog_locations):
Remove 'liboffloadmic'.
* gcc_update (files_and_dependencies): Remove 'liboffloadmic'
files.
* update-copyright.py (GCCCmdLine): Remove 'liboffloadmic'
comment.
gcc/
* config.gcc [target *-intelmic-* | *-intelmicemul-*]: Remove.
* config/i386/i386-options.cc (ix86_omp_device_kind_arch_isa)
[ACCEL_COMPILER]: Remove.
* config/i386/intelmic-mkoffload.cc: Remove.
* config/i386/intelmic-offload.h: Likewise.
* config/i386/t-intelmic: Likewise.
* config/i386/t-omp-device: Likewise.
* configure.ac [target *-intelmic-* | *-intelmicemul-*]: Remove.
* configure: Regenerate.
* doc/install.texi (--enable-offload-targets=[...]): Update.
* doc/sourcebuild.texi: Remove 'liboffloadmic' documentation.
include/
* gomp-constants.h (GOMP_DEVICE_INTEL_MIC): Comment out.
(GOMP_VERSION_INTEL_MIC): Remove.
libgomp/
* libgomp-plugin.h (OFFLOAD_TARGET_TYPE_INTEL_MIC): Remove.
* libgomp.texi (OpenMP Context Selectors): Remove Intel MIC
documentation.
* plugin/configfrag.ac <enable_offload_targets>
[*-intelmic-* | *-intelmicemul-*]: Remove.
* configure: Regenerate.
* testsuite/lib/libgomp.exp (libgomp_init): Remove 'liboffloadmic'
handling.
(offload_target_to_openacc_device_type)
[$offload_target = *-intelmic*]: Remove.
(check_effective_target_offload_device_intel_mic)
(check_effective_target_offload_device_any_intel_mic): Remove.
* testsuite/libgomp.c-c++-common/on_device_arch.h
(device_arch_intel_mic, on_device_arch_intel_mic, any_device_arch)
(any_device_arch_intel_mic): Remove.
* testsuite/libgomp.c-c++-common/target-45.c: Remove
'offload_device_any_intel_mic' XFAIL.
* testsuite/libgomp.fortran/target10.f90: Likewise.
liboffloadmic/
* ChangeLog: Remove.
* Makefile.am: Likewise.
* Makefile.in: Likewise.
* aclocal.m4: Likewise.
* configure: Likewise.
* configure.ac: Likewise.
* configure.tgt: Likewise.
* doc/doxygen/config: Likewise.
* doc/doxygen/header.tex: Likewise.
* include/coi/common/COIEngine_common.h: Likewise.
* include/coi/common/COIEvent_common.h: Likewise.
* include/coi/common/COIMacros_common.h: Likewise.
* include/coi/common/COIPerf_common.h: Likewise.
* include/coi/common/COIResult_common.h: Likewise.
* include/coi/common/COISysInfo_common.h: Likewise.
* include/coi/common/COITypes_common.h: Likewise.
* include/coi/sink/COIBuffer_sink.h: Likewise.
* include/coi/sink/COIPipeline_sink.h: Likewise.
* include/coi/sink/COIProcess_sink.h: Likewise.
* include/coi/source/COIBuffer_source.h: Likewise.
* include/coi/source/COIEngine_source.h: Likewise.
* include/coi/source/COIEvent_source.h: Likewise.
* include/coi/source/COIPipeline_source.h: Likewise.
* include/coi/source/COIProcess_source.h: Likewise.
* liboffloadmic_host.spec.in: Likewise.
* liboffloadmic_target.spec.in: Likewise.
* plugin/Makefile.am: Likewise.
* plugin/Makefile.in: Likewise.
* plugin/aclocal.m4: Likewise.
* plugin/configure: Likewise.
* plugin/configure.ac: Likewise.
* plugin/libgomp-plugin-intelmic.cpp: Likewise.
* plugin/offload_target_main.cpp: Likewise.
* runtime/cean_util.cpp: Likewise.
* runtime/cean_util.h: Likewise.
* runtime/coi/coi_client.cpp: Likewise.
* runtime/coi/coi_client.h: Likewise.
* runtime/coi/coi_server.cpp: Likewise.
* runtime/coi/coi_server.h: Likewise.
* runtime/compiler_if_host.cpp: Likewise.
* runtime/compiler_if_host.h: Likewise.
* runtime/compiler_if_target.cpp: Likewise.
* runtime/compiler_if_target.h: Likewise.
* runtime/dv_util.cpp: Likewise.
* runtime/dv_util.h: Likewise.
* runtime/emulator/coi_common.h: Likewise.
* runtime/emulator/coi_device.cpp: Likewise.
* runtime/emulator/coi_device.h: Likewise.
* runtime/emulator/coi_host.cpp: Likewise.
* runtime/emulator/coi_host.h: Likewise.
* runtime/emulator/coi_version_asm.h: Likewise.
* runtime/emulator/coi_version_linker_script.map: Likewise.
* runtime/liboffload_error.c: Likewise.
* runtime/liboffload_error_codes.h: Likewise.
* runtime/liboffload_msg.c: Likewise.
* runtime/liboffload_msg.h: Likewise.
* runtime/mic_lib.f90: Likewise.
* runtime/offload.h: Likewise.
* runtime/offload_common.cpp: Likewise.
* runtime/offload_common.h: Likewise.
* runtime/offload_engine.cpp: Likewise.
* runtime/offload_engine.h: Likewise.
* runtime/offload_env.cpp: Likewise.
* runtime/offload_env.h: Likewise.
* runtime/offload_host.cpp: Likewise.
* runtime/offload_host.h: Likewise.
* runtime/offload_iterator.h: Likewise.
* runtime/offload_omp_host.cpp: Likewise.
* runtime/offload_omp_target.cpp: Likewise.
* runtime/offload_orsl.cpp: Likewise.
* runtime/offload_orsl.h: Likewise.
* runtime/offload_table.cpp: Likewise.
* runtime/offload_table.h: Likewise.
* runtime/offload_target.cpp: Likewise.
* runtime/offload_target.h: Likewise.
* runtime/offload_target_main.cpp: Likewise.
* runtime/offload_timer.h: Likewise.
* runtime/offload_timer_host.cpp: Likewise.
* runtime/offload_timer_target.cpp: Likewise.
* runtime/offload_trace.cpp: Likewise.
* runtime/offload_trace.h: Likewise.
* runtime/offload_util.cpp: Likewise.
* runtime/offload_util.h: Likewise.
* runtime/ofldbegin.cpp: Likewise.
* runtime/ofldend.cpp: Likewise.
* runtime/orsl-lite/include/orsl-lite.h: Likewise.
* runtime/orsl-lite/lib/orsl-lite.c: Likewise.
* runtime/orsl-lite/version.txt: Likewise.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features): Detect
amx-fp16.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET,
OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros.
(ix86_handle_option): Handle -mamx-fp16.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AMX_FP16.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
amx-fp16.
* config.gcc: Add amxfp16intrin.h.
* config/i386/cpuid.h (bit_AMX_FP16): New.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AMX_FP16__.
* config/i386/i386-isa.def: Add DEF_PTA for AMX_FP16.
* config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16.
(ix86_valid_target_attribute_inner_p): Add new ATTR.
(ix86_option_override_internal): Handle AMX-FP16.
* config/i386/i386.opt: Add -mamx-fp16.
* config/i386/immintrin.h: Include amxfp16intrin.h.
* doc/extend.texi: Document -mamx-fp16.
* doc/invoke.texi: Document amx-fp16.
* doc/sourcebuild.texi: Document amx_fp16.
* config/i386/amxfp16intrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mamx-fp16.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp: (check_effective_target_amx_fp16):
New proc.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/amx-check.h: Add AMX_FP16.
* gcc.target/i386/amx-helper.h: New file to support amx-fp16.
* gcc.target/i386/amxfp16-asmatt-1.c: New test.
* gcc.target/i386/amxfp16-asmintel-1.c: Ditto.
* gcc.target/i386/amxfp16-dpfp16ps-2.c: Ditto.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_intel_cpu):
Add Sierra Forest.
* common/config/i386/i386-common.cc
(processor_names): Add Sierra Forest.
(processor_alias_table): Ditto.
* common/config/i386/i386-cpuinfo.h
(enum processor_types): Add INTEL_SIERRAFOREST.
* config.gcc: Add -march=sierraforest.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Handle Sierra Forest.
* config/i386/i386-c.cc (ix86_target_macros_internal):
Ditto.
* config/i386/i386-options.cc (m_SIERRAFOREST): New define.
(processor_cost_table): Add sierra forest.
* config/i386/i386.h (enum processor_type):
Add PROCESSOR_SIERRA_FOREST.
(PTA_SIERRAFOREST): Ditto.
* doc/extend.texi: Add sierra forest.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv16.C: Add sierra forest.
* gcc.target/i386/funcspec-56.inc: Handle new march.
|
|
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect cmpccxadd.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_CMPCCXADD_SET,
OPTION_MASK_ISA2_CMPCCXADD_UNSET): New.
(ix86_handle_option): Handle -mcmpccxadd.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_CMPCCXADD.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
cmpccxadd.
* config.gcc: Add cmpccxaddintrin.h.
* config/i386/cpuid.h (bit_CMPCCXADD): New.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT)
and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__CMPCCXADD__.
* config/i386/i386-expand.cc (ix86_expand_special_args_builtin):
Add new parameter to indicate constant position.
Handle INT_FTYPE_PINT_INT_INT_INT
and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT.
* config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD).
* config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd.
(ix86_valid_target_attribute_inner_p): Handle cmpccxadd.
* config/i386/i386.opt: Add option -mcmpccxadd.
* config/i386/sync.md (cmpccxadd_<mode>): New define insn.
* config/i386/x86gprintrin.h: Include cmpccxaddintrin.h.
* doc/extend.texi: Document cmpccxadd.
* doc/invoke.texi: Document -mcmpccxadd.
* doc/sourcebuild.texi: Document target cmpccxadd.
* config/i386/cmpccxaddintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mcmpccxadd.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-13.c: Add -mcmpccxadd.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/x86gprintrin-1.c: Ditto.
* gcc.target/i386/x86gprintrin-2.c: Ditto.
* gcc.target/i386/x86gprintrin-3.c: Ditto.
* gcc.target/i386/x86gprintrin-4.c: Ditto.
* gcc.target/i386/x86gprintrin-5.c: Ditto.
* lib/target-supports.exp (check_effective_target_cmpccxadd):
New.
* gcc.target/i386/cmpccxadd-1.c: New test.
* gcc.target/i386/cmpccxadd-2.c: Ditto.
|
|
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVXNECONVERT_SET,
OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New.
(ix86_handle_option): Handle -mavxneconvert, unset
avxneconvert when avx2 is disabled.
* common/config/i386/i386-cpuinfo.h (processor_types): Add
FEATURE_AVXNECONVERT.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxneconvert.
* common/config/i386/cpuinfo.h (get_available_features):
Detect avxneconvert.
* config.gcc: Add avxneconvertintrin.h
* config/i386/avxneconvertintrin.h: New.
* config/i386/avx512bf16vlintrin.h (_mm256_cvtneps_pbh):
Unified builtin with avxneconvert.
(_mm_cvtneps_pbh): Ditto.
* config/i386/cpuid.h (bit_AVXNECONVERT): New.
* config/i386/i386-builtin-types.def: Add
DEF_POINTER_TYPE (PCV8HF, V8HF, CONST),
DEF_POINTER_TYPE (PCV8BF, V8BF, CONST),
DEF_POINTER_TYPE (PCV16HF, V16HF, CONST),
DEF_POINTER_TYPE (PCV16BF, V16BF, CONST),
DEF_FUNCTION_TYPE (V4SF, PCBFLOAT16),
DEF_FUNCTION_TYPE (V4SF, PCFLOAT16),
DEF_FUNCTION_TYPE (V8SF, PCBFLOAT16),
DEF_FUNCTION_TYPE (V8SF, PCFLOAT16),
DEF_FUNCTION_TYPE (V4SF, PCV8BF),
DEF_FUNCTION_TYPE (V4SF, PCV8HF),
DEF_FUNCTION_TYPE (V8SF, PCV16HF),
DEF_FUNCTION_TYPE (V8SF, PCV16BF),
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXNECONVERT__.
* config/i386/i386-expand.cc (ix86_expand_special_args_builtin):
Handle V4SF_FTYPE_PCBFLOAT16,V8SF_FTYPE_PCBFLOAT16, V4SF_FTYPE_PCFLOAT16,
V8SF_FTYPE_PCFLOAT16,V4SF_FTYPE_PCV8BF,
V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF.
* config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New.
* config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert.
(ix86_valid_target_attribute_inner_p): Handle avxneconvert.
* config/i386/i386.md: Add attr avx512bf16vl and avxneconvert.
* config/i386/i386.opt: Add option -mavxneconvert.
* config/i386/immintrin.h: Inculde avxneconvertintrin.h.
* config/i386/sse.md (vbcstnebf162ps_<mode>): New define_insn.
(vbcstnesh2ps_<mode>): Ditto.
(vcvtnee<bf16_ph>2ps_<mode>):Ditto.
(vcvtneo<bf16_ph>2ps_<mode>):Ditto.
(vcvtneps2bf16_v4sf): Ditto.
(*vcvtneps2bf16_v4sf): Ditto.
(vcvtneps2bf16_v8sf): Ditto.
* doc/invoke.texi: Document -mavxneconvert.
* doc/extend.texi: Document avxneconvert.
* doc/sourcebuild.texi: Document target avxneconvert.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx-check.h: Add avxneconvert check.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -mavxneconvert.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* lib/target-supports.exp:add check_effective_target_avxneconvert.
* gcc.target/i386/avx-ne-convert-1.c: New test.
* gcc.target/i386/avx-ne-convert-vbcstnebf162ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vbcstnesh2ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vcvtneebf162ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vcvtneeph2ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vcvtneobf162ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vcvtneoph2ps-2.c: Ditto.
* gcc.target/i386/avx-ne-convert-vcvtneps2bf16-2.c: Ditto.
* gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1.c: Rename..
* gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1a.c: To this.
* gcc.target/i386/avx512bf16vl-vcvtneps2bf16-1b.c: New test.
|
|
This splits up the targetdm sources so that each file only handles one
target platform.
Having all logic kept in the headers means that they could become out of
sync when a new target is added (loongarch*-*-linux*) or accidentally
broken if some headers in tm_file are changed about.
gcc/ChangeLog:
* config.gcc: Split out glibc-d.o into linux-d.o, kfreebsd-d.o,
kopensolaris-d.o, and gnu-d.o. Split out cygwin-d.o from winnt-d.o.
* config/arm/linux-eabi.h (EXTRA_TARGET_D_OS_VERSIONS): Remove.
* config/gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove.
* config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): Remove.
* config/i386/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Remove.
* config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Remove.
* config/i386/t-cygming: Add cygwin-d.o.
* config/i386/winnt-d.cc (winnt_d_os_builtins): Only add
MinGW-specific version condition.
* config/kfreebsd-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove.
* config/kopensolaris-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove.
* config/linux-android.h (ANDROID_TARGET_D_OS_VERSIONS): Remove.
* config/linux.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove.
* config/mips/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Remove.
* config/t-glibc: Remove glibc-d.o, add gnu-d.o, kfreebsd-d.o,
kopensolaris-d.o.
* config/t-linux: Add linux-d.o.
* config/glibc-d.cc: Remove file.
* config/gnu-d.cc: New file.
* config/i386/cygwin-d.cc: New file.
* config/kfreebsd-d.cc: New file.
* config/kopensolaris-d.cc: New file.
* config/linux-d.cc: New file.
|
|
gcc/ChangeLog:
* config.gcc (riscv*): Add riscv-v.o to extra_objs.
* config/riscv/constraints.md (vu): New constraint.
(vi): Ditto.
(Wc0): Ditto.
(Wc1): Ditto.
* config/riscv/predicates.md (vector_length_operand): New.
(reg_or_mem_operand): Ditto.
(vector_move_operand): Ditto.
(vector_mask_operand): Ditto.
(vector_merge_operand): Ditto.
* config/riscv/riscv-protos.h (riscv_regmode_natural_size) New.
(riscv_vector::const_vec_all_same_in_range_p): Ditto.
(riscv_vector::legitimize_move): Ditto.
(tail_policy): Ditto.
(mask_policy): Ditto.
* config/riscv/riscv-v.cc: New.
* config/riscv/riscv-vector-builtins-bases.cc
(vsetvl::expand): Refactor how LMUL encoding.
* config/riscv/riscv.cc (riscv_print_operand): Update how LMUL
print and mask operand print.
(riscv_regmode_natural_size): New.
* config/riscv/riscv.h (REGMODE_NATURAL_SIZE): New.
* config/riscv/riscv.md (mode): Add vector modes.
* config/riscv/t-riscv (riscv-v.o) New.
* config/riscv/vector-iterators.md: New.
* config/riscv/vector.md (vundefined<mode>): New.
(mov<mode>): New.
(*mov<mode>): New.
(@vsetvl<mode>_no_side_effects): New.
(@pred_mov<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/mov-1.c: New.
* gcc.target/riscv/rvv/base/mov-10.c: New.
* gcc.target/riscv/rvv/base/mov-11.c: New.
* gcc.target/riscv/rvv/base/mov-12.c: New.
* gcc.target/riscv/rvv/base/mov-13.c: New.
* gcc.target/riscv/rvv/base/mov-2.c: New.
* gcc.target/riscv/rvv/base/mov-3.c: New.
* gcc.target/riscv/rvv/base/mov-4.c: New.
* gcc.target/riscv/rvv/base/mov-5.c: New.
* gcc.target/riscv/rvv/base/mov-6.c: New.
* gcc.target/riscv/rvv/base/mov-7.c: New.
* gcc.target/riscv/rvv/base/mov-8.c: New.
* gcc.target/riscv/rvv/base/mov-9.c: New.
|
|
For R6+ target, it allows to configure gcc to use compact branches only
if avaiable.
gcc/ChangeLog:
* config.gcc: add -with-compact-branches=policy build option.
* doc/install.texi: Likewise.
* config/mips/mips.h: Likewise.
|
|
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4.
* common/config/i386/i386-common.cc (processor_names): Add znver4.
(processor_alias_table): Add znver4 and modularize old znvers.
* common/config/i386/i386-cpuinfo.h (processor_subtypes):
AMDFAM19H_ZNVER4.
* config.gcc (x86_64-*-* |...): Likewise.
* config/i386/driver-i386.cc (host_detect_local_cpu): Let
-march=native recognize znver4 cpus.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4.
* config/i386/i386-options.cc (m_ZNVER4): New definition.
(m_ZNVER): Include m_ZNVER4.
(processor_cost_table): Add znver4.
* config/i386/i386.cc (ix86_reassociation_width): Likewise.
* config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4.
(PTA_ZNVER1): New definition.
(PTA_ZNVER2): Likewise.
(PTA_ZNVER3): Likewise.
(PTA_ZNVER4): Likewise.
* config/i386/i386.md (define_attr "cpu"): Add znver4 and rename
md file.
* config/i386/x86-tune-costs.h (znver4_cost): New definition.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4.
(ix86_adjust_cost): Likewise.
* config/i386/znver1.md: Rename to znver.md.
* config/i386/znver.md: Add new reservations for znver4.
* doc/extend.texi: Add details about znver4.
* doc/invoke.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.target/i386/mv29.C: Likewise.
|
|
gcc/ChangeLog:
* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
(DEF_RVV_FUNCTION): Ditto.
(handle_pragma_vector): Add intrinsic framework.
* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.
* config/riscv/riscv.md: include vector.md.
* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins-bases.cc: New file.
* config/riscv/riscv-vector-builtins-bases.h: New file.
* config/riscv/riscv-vector-builtins-functions.def: New file.
* config/riscv/riscv-vector-builtins-shapes.cc: New file.
* config/riscv/riscv-vector-builtins-shapes.h: New file.
* config/riscv/riscv-vector-builtins-types.def: New file.
* config/riscv/vector.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.
|
|
gcc/ChangeLog:
* config.gcc: Add gt files since function_instance is GTY ((user)).
* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV intrinsic framework.
(riscv_builtin_decl): Ditto.
(riscv_expand_builtin): Ditto.
* config/riscv/riscv-protos.h (builtin_decl): New function.
(expand_builtin): Ditto.
(enum riscv_builtin_class): New enum to classify RVV intrinsic and RISC-V general built-in.
* config/riscv/riscv-vector-builtins.cc (class GTY): New declaration.
(struct registered_function_hasher): New struct.
(DEF_RVV_OP_TYPE): New macro.
(DEF_RVV_TYPE): Ditto.
(DEF_RVV_PRED_TYPE): Ditto.
(GTY): New declaration.
(add_attribute): New function.
(check_required_extensions): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_instance::function_instance): Ditto.
(function_instance::operator==): Ditto.
(function_instance::any_type_float_p): Ditto.
(function_instance::get_return_type): Ditto.
(function_instance::get_arg_type): Ditto.
(function_instance::hash): Ditto.
(function_instance::call_properties): Ditto.
(function_instance::reads_global_state_p): Ditto.
(function_instance::modifies_global_state_p): Ditto.
(function_instance::could_trap_p): Ditto.
(function_builder::function_builder): Ditto.
(function_builder::~function_builder): Ditto.
(function_builder::allocate_argument_types): Ditto.
(function_builder::register_function_group): Ditto.
(function_builder::append_name): Ditto.
(function_builder::finish_name): Ditto.
(function_builder::get_attributes): Ditto.
(function_builder::add_function): Ditto.
(function_builder::add_unique_function): Ditto.
(function_call_info::function_call_info): Ditto.
(function_expander::function_expander): Ditto.
(function_expander::add_input_operand): Ditto.
(function_expander::generate_insn): Ditto.
(registered_function_hasher::hash): Ditto.
(registered_function_hasher::equal): Ditto.
(builtin_decl): Ditto.
(expand_builtin): Ditto.
(gt_ggc_mx): Define for using GCC garbage collect.
(gt_pch_nx): Define for using GCC garbage collect.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_OP_TYPE): New macro.
(DEF_RVV_PRED_TYPE): Ditto.
(vbool64_t): Add suffix.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
(vint8mf8_t): Ditto.
(vuint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vuint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vuint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vuint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vuint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vuint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vuint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vuint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vuint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vuint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vuint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vuint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vuint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vuint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vuint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vuint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vuint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vuint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
(vv): Ditto.
(vx): Ditto.
(v): Ditto.
(wv): Ditto.
(wx): Ditto.
(x_x_v): Ditto.
(vf2): Ditto.
(vf4): Ditto.
(vf8): Ditto.
(vvm): Ditto.
(vxm): Ditto.
(x_x_w): Ditto.
(v_v): Ditto.
(v_x): Ditto.
(vs): Ditto.
(mm): Ditto.
(m): Ditto.
(vf): Ditto.
(vm): Ditto.
(wf): Ditto.
(vfm): Ditto.
(v_f): Ditto.
(ta): Ditto.
(tu): Ditto.
(ma): Ditto.
(mu): Ditto.
(tama): Ditto.
(tamu): Ditto.
(tuma): Ditto.
(tumu): Ditto.
(tam): Ditto.
(tum): Ditto.
* config/riscv/riscv-vector-builtins.h (GCC_RISCV_VECTOR_BUILTINS_H): New macro.
(RVV_REQUIRE_RV64BIT): Ditto.
(RVV_REQUIRE_ZVE64): Ditto.
(RVV_REQUIRE_ELEN_FP_32): Ditto.
(RVV_REQUIRE_ELEN_FP_64): Ditto.
(enum operand_type_index): New enum.
(DEF_RVV_OP_TYPE): New macro.
(enum predication_type_index): New enum.
(DEF_RVV_PRED_TYPE): New macro.
(enum rvv_base_type): New enum.
(struct rvv_builtin_suffixes): New struct.
(struct rvv_arg_type_info): Ditto.
(struct rvv_type_info): Ditto.
(struct rvv_op_info): Ditto.
(class registered_function): New class.
(class function_base): Ditto.
(class function_shape): Ditto.
(struct function_group_info): New struct.
(class GTY): New class.
(class function_builder): Ditto.
(class function_call_info): Ditto.
(function_call_info::function_returns_void_p): New function.
(class function_expander): New class.
(function_instance::operator!=): New function.
(function_expander::expand): Ditto.
(function_expander::add_input_operand): Ditto.
(function_base::call_properties): Ditto.
|
|
gcc/ChangeLog
* common/config/i386/cpuinfo.h (get_available_features): Detect
avxvnniint8.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVXVNNIINT8_SET): New.
(OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto.
(ix86_handle_option): Handle -mavxvnniint8.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVXVNNIINT8.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxvnniint8.
* config.gcc: Add avxvnniint8intrin.h.
* config/i386/avxvnniint8intrin.h: New file.
* config/i386/cpuid.h (bit_AVXVNNIINT8): New.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXVNNIINT8__.
* config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8.
(ix86_valid_target_attribute_inner_p): Handle avxvnniint8.
* config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New..
* config/i386/i386.opt: Add option -mavxvnniint8.
* config/i386/immintrin.h: Include avxvnniint8intrin.h.
* config/i386/sse.md (UNSPEC_VPMADDUBSWACCD
UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD,
UNSPEC_VPMADDWDACCSSD): Rename according to new style.
(vpdp<vpdotprodtype>_<mode>): New define_insn.
* doc/extend.texi: Document avxvnniint8.
* doc/invoke.texi: Document -mavxvnniint8.
* doc/sourcebuild.texi: Document target avxvnniint8.
gcc/testsuite/ChangeLog
* g++.dg/other/i386-2.C: Add -mavxvnniint8.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-check.h: Add avxvnniint8 check.
* gcc.target/i386/sse-12.c: Add -mavxvnniint8.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avxvnniint8): New.
* gcc.target/i386/avxvnniint8-1.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
|
|
gcc/
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET,
OPTION_MASK_ISA2_AVX2_UNSET): New macro.
(ix86_handle_option): Handle -mavxifma.
* common/config/i386/i386-cpuinfo.h (processor_types): Add
FEATURE_AVXIFMA.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxifma.
* common/config/i386/cpuinfo.h (get_available_features):
Detect avxifma.
* config.gcc: Add avxifmaintrin.h
* config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change
to macro.
(_mm_madd52hi_epu64): Likewise.
(_mm256_madd52lo_epu64): Likewise.
(_mm256_madd52hi_epu64): Likewise.
* config/i386/avxifmaintrin.h: New header.
* config/i386/cpuid.h (bit_AVXIFMA): New.
* config/i386/i386-builtin.def: Add new builtins, and correct
pattern names for AVX512IFMA.
* config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA
builtins like AVX-VNNI.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXIFMA__.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Relax ISA masks for AVXIFMA.
* config/i386/i386-isa.def: Add AVXIFMA.
* config/i386/i386-options.cc (isa2_opts): Add -mavxifma.
(ix86_valid_target_attribute_inner_p): Handle avxifma.
* config/i386/i386.md (isa): Add attr avxifma and avxifmavl.
* config/i386/i386.opt: Add option -mavxifma.
* config/i386/immintrin.h: Inculde avxifmaintrin.h.
* config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>):
Remove.
(vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove.
(vpamdd52huq<mode>_maskz): Rename to ...
(vpmadd52huq<mode>_maskz): ... this.
(vpamdd52luq<mode>_maskz): Rename to ...
(vpmadd52luq<mode>_maskz): ... this.
(vpmadd52<vpmadd52type><mode>): New define_insn.
(vpmadd52<vpmadd52type>v8di): Likewise.
(vpmadd52<vpmadd52type><mode>_maskz_1): Likewise.
(vpamdd52<vpmadd52type><mode>_mask): Rename to ...
(vpmadd52<vpmadd52type><mode>_mask): ... this.
* doc/invoke.texi: Document -mavxifma.
* doc/extend.texi: Document avxifma.
* doc/sourcebuild.texi: Document target avxifma.
gcc/testsuite/
* gcc.target/i386/avx-check.h: Add avxifma check.
* gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane..
* gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this.
* gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto.
* gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto.
* gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test.
* gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto.
* gcc.target/i386/avx-ifma-1.c: Ditto.
* gcc.target/i386/avx-ifma-2.c: Ditto.
* gcc.target/i386/avx-ifma-3.c: Ditto.
* gcc.target/i386/avx-ifma-4.c: Ditto.
* gcc.target/i386/avx-ifma-5.c: Ditto.
* gcc.target/i386/avx-ifma-6.c: Ditto.
* gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto.
* gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto.
* gcc.target/i386/sse-12.c: Add -mavxifma.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avxifma): New.
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