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- New option -misa-spec support: -misa-spec=[2.2|20190608|20191213] and
corresponding configuration option --with-isa-spec.
- Current default ISA spec set to 2.2, but we intend to bump this to
20191213 or later in next release.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c (riscv_ext_version): New.
(riscv_ext_version_table): Ditto.
(get_default_version): Ditto.
(riscv_subset_t::implied_p): New field.
(riscv_subset_t::riscv_subset_t): Init implied_p.
(riscv_subset_list::add): New.
(riscv_subset_list::handle_implied_ext): Pass riscv_subset_t
instead of separated argument.
(riscv_subset_list::to_string): Handle zifencei and zicsr, and
omit version if version is unknown.
(riscv_subset_list::parsing_subset_version): New argument `ext`,
remove default_major_version and default_minor_version, get
default version info via get_default_version.
(riscv_subset_list::parse_std_ext): Update argument for
parsing_subset_version calls.
Handle 2.2 ISA spec, always enable zicsr and zifencei, they are
included in baseline ISA in that time.
(riscv_subset_list::parse_multiletter_ext): Update argument for
`parsing_subset_version` and `add` calls.
(riscv_subset_list::parse): Adjust argument for
riscv_subset_list::handle_implied_ext call.
* config.gcc (riscv*-*-*): Handle --with-isa-spec=.
* config.in (HAVE_AS_MISA_SPEC): New.
(HAVE_AS_MARCH_ZIFENCEI): Ditto.
* config/riscv/riscv-opts.h (riscv_isa_spec_class): New.
(riscv_isa_spec): Ditto.
* config/riscv/riscv.h (HAVE_AS_MISA_SPEC): New.
(ASM_SPEC): Pass -misa-spec if gas supported.
* config/riscv/riscv.opt (riscv_isa_spec_class) New.
* configure.ac (HAVE_AS_MARCH_ZIFENCEI): New test.
(HAVE_AS_MISA_SPEC): Ditto.
* configure: Regen.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-9.c: New.
* gcc.target/riscv/arch-10.c: Ditto.
* gcc.target/riscv/arch-11.c: Ditto.
* gcc.target/riscv/attribute-6.c: Remove, we don't support G
with version anymore.
* gcc.target/riscv/attribute-8.c: Reorder arch string to fit canonical
ordering.
* gcc.target/riscv/attribute-9.c: We don't emit version for
unknown extensions now.
* gcc.target/riscv/attribute-11.c: Add -misa-spec=2.2 flags.
* gcc.target/riscv/attribute-12.c: Ditto.
* gcc.target/riscv/attribute-13.c: Ditto.
* gcc.target/riscv/attribute-14.c: Ditto.
* gcc.target/riscv/attribute-15.c: New.
* gcc.target/riscv/attribute-16.c: Ditto.
* gcc.target/riscv/attribute-17.c: Ditto.
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gcc/
* config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64}
as alias flags for --with-{cpu,arch,tune} on AArch64.
* doc/install.texi: Document new flags for aarch64.
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fixes a configure error on Arm64 when passing --with-tune=... to configure:
```
This target does not support --with-tune.
Valid --with options are: abi cpu arch
```
The missing flag sets target tuning to a different value than generic tuning.
gcc/
* config.gcc: Add --with-tune to AArch64 configure flags.
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2020-10-13 Hongtao Liu <hongtao.liu@intel.com>
Hongyu Wang <hongyu.wang@intel.com>
gcc/
* common/config/i386/cpuinfo.h (get_available_features):
Detect AVXVNNI.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA2_AVXVNNI_SET,
OPTION_MASK_ISA2_AVXVNNI_UNSET): New.
(OPTION_MASK_ISA2_AVX2_UNSET): Add AVXVNNI.
(ix86_hanlde_option): Handle -mavxvnni, unset avxvnni when
avx2 is disabled.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVXVNNI.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for avxvnni.
* config.gcc: Add avxvnniintrin.h.
* config/i386/avx512vnnivlintrin.h: Reimplement 128/256 bit non-mask
intrinsics with macros to support unified interface.
* config/i386/avxvnniintrin.h: New header file.
* config/i386/cpuid.h (bit_AVXVNNI): New.
* config/i386/i386-builtins.c (def_builtin): Handle AVXVNNI mask
for unified builtin.
* config/i386/i386-builtin.def (BDESC): Adjust AVX512VNNI
builtins for AVXVNNI.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__AVXVNNI__.
* config/i386/i386-expand.c (ix86_expand_builtin): Handle bisa
for AVXVNNI to support unified intrinsic name, since there is no
dependency between AVX512VNNI and AVXVNNI.
* config/i386/i386-options.c (isa2_opts): Add -mavxvnni.
(ix86_valid_target_attribute_inner_p): Handle avxnnni.
(ix86_option_override_internal): Ditto.
* config/i386/i386.h (TARGET_AVXVNNI, TARGET_AVXVNNI_P,
TARGET_AVXVNNI_P, PTA_AVXVNNI): New.
(PTA_SAPPHIRERAPIDS): Add AVX_VNNI.
(PTA_ALDERLAKE): Likewise.
* config/i386/i386.md ("isa"): Add avxvnni, avx512vnnivl.
("enabled"): Adjust for avxvnni and avx512vnnivl.
* config/i386/i386.opt: Add option -mavxvnni.
* config/i386/immintrin.h: Include avxvnniintrin.h.
* config/i386/sse.md (vpdpbusd_<mode>): Adjust for AVXVNNI.
(vpdpbusds_<mode>): Likewise.
(vpdpwssd_<mode>): Likewise.
(vpdpwssds_<mode>): Likewise.
(vpdpbusd_v16si): New.
(vpdpbusds_v16si): Likewise.
(vpdpwssd_v16si): Likewise.
(vpdpwssds_v16si): Likewise.
* doc/invoke.texi: Document -mavxvnni.
* doc/extend.texi: Document avxvnni.
* doc/sourcebuild.texi: Document target avxvnni.
gcc/testsuite/
* gcc.target/i386/avx512vl-vnni-1.c: Rename..
* gcc.target/i386/avx512vl-vnni-1a.c: To This.
* gcc.target/i386/avx512vl-vnni-1b.c: New test.
* gcc.target/i386/avx512vl-vnni-2.c: Ditto.
* gcc.target/i386/avx512vl-vnni-3.c: Ditto.
* gcc.target/i386/avx-vnni-1.c: Ditto.
* gcc.target/i386/avx-vnni-2.c: Ditto.
* gcc.target/i386/avx-vnni-3.c: Ditto.
* gcc.target/i386/avx-vnni-4.c: Ditto.
* gcc.target/i386/avx-vnni-5.c: Ditto.
* gcc.target/i386/avx-vnni-6.c: Ditto.
* gcc.target/i386/avx-vpdpbusd-2.c: Ditto.
* gcc.target/i386/avx-vpdpbusds-2.c: Ditto.
* gcc.target/i386/avx-vpdpwssd-2.c: Ditto.
* gcc.target/i386/avx-vpdpwssds-2.c: Ditto.
* gcc.target/i386/vnni_inline_error.c: Ditto.
* gcc.target/i386/avx512vnnivl-builtin.c: Ditto.
* gcc.target/i386/avxvnni-builtin.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -mavxvnni.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* lib/target-supports.exp (check_effective_target_avxvnni):
New proc.
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multi-lib settings.
- Able to configure complex multi-lib rule in configure time, without modify
any in-tree source.
- I was consider to implmenet this into `--with-multilib-list` option,
but I am not sure who will using that with riscv*-*-elf*, so I decide to
using another option name for that.
- --with-multilib-generator will pass arguments to multilib-generator, and
then using the generated multi-lib config file to build the toolchain.
e.g. Build riscv gcc, default arch/abi is rv64gc/lp64, and build multilib
for rv32imafd/ilp32 and rv32i/ilp32; rv32ic/ilp32 will reuse
rv32i/ilp32.
$ <GCC-SRC>/configure \
--target=riscv64-elf \
--with-arch=rv64gc --with-abi=lp64 \
--with-multilib-generator=rv32i-ilp32--c;rv32imafd-ilp32--
V3 Changes:
- Rename --with-multilib-config to --with-multilib-generator
- Check --with-multilib-generator and --with-multilib-list can't be used at
same time.
V2 Changes:
- Fix --with-multilib-config hanling on non riscv*-*-elf* triple.
gcc/ChangeLog:
* config.gcc (riscv*-*-*): Handle --with-multilib-generator.
* configure: Regen.
* configure.ac: Add --with-multilib-generator.
* config/riscv/multilib-generator: Exit when parsing arch string error.
* config/riscv/t-withmultilib-generator: New.
* doc/install.texi: Document --with-multilib-generator.
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This change extends the VxWorks support on intel CPUs to
VxWorks7r2 for x86_64 as well as x86, with a "mcmodel=large"
additional multilib for the 64bit configuration.
The support for fPIC is not functional yet for this model,
so we just don't add the corresponding multilib.
We extend the range of CPU families handled by TARGET_OS_CPP_BUILTINS,
accounting for the fact that archs older than PENTIUM4 are
not supported (any more) by VxWorks 7.
As we did for powerpc, we leverage VX_CPU_PREFIX to emit different
forms of definitions for different families of VxWorks as the system
headers's expectations has evolved between Vx 5, 6 and 7.
2020-10-27 Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc: Adjust the ix86/x86_64-wrs-vxworks filters
to apply to VxWorks 7 as well.
* config/i386/t-vxworks (MULTILIB_OPTIONS, MULTILIB_DIRNAMES):
Remove the fPIC multilib and add one for the large code model
on x86_64.
* config/i386/vxworks.h: Separate sections for TARGET_VXWORKS7,
other variants and common bits.
(TARGET_OS_CPP_BUILTINS): Augment to support a range of CPU
families. Leverage VX_CPU_PREFIX.
(CC1_SPEC): Add definition.
(STACK_CHECK_PROTECT): Use conditional expression instead of
heavier to read conditioned macro definitions.
libgcc/
* config.host: Adjust the ix86/x86_64-wrs-vxworks filters
to apply to VxWorks 7 as well.
Co-authored-by: Douglas Rupp <rupp@adacore.com>
Co-authored-by: Pat Bernardi <bernardi@adacore.com>
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gcc/ChangeLog
2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com>
Hongyu Wang <hongyu.wang@intel.com>
Hongtao Liu <hongtao.liu@intel.com>
* common/config/i386/cpuinfo.h (get_available_features):
Detect KL, AESKLE and WIDEKL features.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_KL_SET): New.
(OPTION_MASK_ISA_WIDEKL_SET): Likewise.
(OPTION_MASK_ISA_KL_UNSET): Likewise.
(OPTION_MASK_ISA_WIDEKL_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX2_UNSET): Likewise.
(OPTION_MASK_ISA2_AVX_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE4_UNSET): Likewise.
(OPTION_MASK_ISA2_SSSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE3_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE2_UNSET): Likewise.
(OPTION_MASK_ISA2_SSE_UNSET): Likewise.
(ix86_handle_option): Handle kl and widekl, add dependency chain
for KL and SSE2.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
(FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for KL, AESKLE and WIDEKL.
* config.gcc: Add keylockerintrin.h.
* doc/invoke.texi: Document new option -mkl and -mwidekl.
* doc/extend.texi: Document kl and widekl.
* config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New.
* config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID),
(UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT),
(UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New
function types.
* config/i386/i386-builtin.def: Add
__builtin_ia32_loadiwkey,
__builtin_ia32_aesdec128kl_u8,
__builtin_ia32_aesdec256kl_u8,
__builtin_ia32_aesenc128kl_u8,
__builtin_ia32_aesenc256kl_u8,
__builtin_ia32_aesdecwide128kl_u8,
__builtin_ia32_aesdecwide256kl_u8,
__builtin_ia32_aesencwide128kl_u8,
__builtin_ia32_aesencwide256kl_u8,
__builtin_ia32_encodekey128_u32,
__builtin_ia32_encodekey256_u32.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
kl and widekl.
* config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl.
(ix86_option_override_internal): Handle KL and WIDEKL.
(ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl.
* config/i386/i386-expand.c
(ix86_expand_builtin): Expand Keylocker Builtins.
* config/i386/i386.h (TARGET_KL): New.
(TARGET_KL_P): Likewise.
(TARGET_WIDEKL): Likewise.
(TARGET_WIDEKL_P): Likewise.
(PTA_KL): Likewise.
(PTA_WIDEKL): Likewise.
(PTA_TIGERLAKE): Add PTA_KL, PTA_WIDEKL.
(PTA_ALDERLAKE): Likewise.
* config/i386/i386.opt: Add new option mkl and mwidekl.
* config/i386/keylockerintrin.h: New header file for Keylocker.
* config/i386/immintrin.h: Include keylockerintrin.h.
* config/i386/predicates.md (encodekey128_operation): New
predicate.
(encodekey256_operation): Likewise.
(aeswidekl_operation): Likewise.
* config/i386/sse.md (UNSPECV_LOADIWKEY): New.
(UNSPECV_AESDEC128KLU8): Likewise.
(UNSPECV_AESENC128KLU8): Likewise.
(UNSPECV_AESDEC256KLU8): Likewise.
(UNSPECV_AESENC256KLU8): Likewise.
(UNSPECV_AESDECWIDE128KLU8): Likewise.
(UNSPECV_AESENCWIDE128KLU8): Likewise.
(UNSPECV_AESDECWIDE256KLU8): Likewise.
(UNSPECV_AESENCWIDE256KLU8): Likewise.
(UNSPECV_ENCODEKEY128U32): Likewise.
(UNSPECV_ENCODEKEY256U32): Likewise.
(encodekey128u32): New expander.
(encodekey256u32): Likewise.
(aes<aeswideklvariant>u8): Likewise.
(loadiwkey): New insn pattern.
(*encodekey128u32): Likewise.
(*encodekey256u32): Likewise.
(aes<aesklvariant>u8): Likewise.
(*aes<aeswideklvariant>u8): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/i386/keylocker-aesdec128kl.c: New test.
* gcc.target/i386/keylocker-aesdec256kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise.
* gcc.target/i386/keylocker-aesenc128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide128kl.c: Likewise.
* gcc.target/i386/keylocker-aesencwide256kl.c: Likewise.
* gcc.target/i386/keylocker-encodekey128.c: Likewise.
* gcc.target/i386/keylocker-encodekey256.c: Likewise.
* gcc.target/i386/keylocker-loadiwkey.c: Likewise.
* g++.dg/other/i386-2.C: Add -mkl and -mwidekl.
* g++.dg/other/i386-3.C: Likewise.
* gcc.target/i386/sse-12.c: Likewise.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-14.c: Likewise.
* gcc.target/i386/sse-22.c: Add kl and widekl.
* gcc.target/i386/sse-23.c: Likewise.
* gcc.target/i386/funcspec-56.inc: Add new target attribute test.
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> + {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
> + {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
> + 0, P_NONE},
> + {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
> + 0, P_NONE},
> + {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
> + 0, P_NONE},
> {"eden-x2", PROCESSOR_K8, CPU_K8,
> PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
> 0, P_NONE},
I have noticed that one can't configure gcc to default to these.
I've also found various other 32-bit or 64-bit -march= arguments for which
it wasn't possible to configure gcc to default to those.
The x86-64-v* the patch only allows in --with-arch_64=, because otherwise
it fails build miserably - as
./xgcc -B ./ -S -march=x86-64-v2 -m32 test.c
cc1: error: ‘x86-64-v2’ architecture level is only defined for the x86-64 psABI
when building 32-bit multilibs. Even if multilibs are disallowed, I think
the compiler still supports -m32 and so --with-arch_64= seems to be the only
option in which we can support that.
2020-10-22 Jakub Jelinek <jakub@redhat.com>
* config.gcc (x86_archs): Add samuel-2, nehemiah, c7 and esther.
(x86_64_archs): Add eden-x2, nano, nano-1000, nano-2000, nano-3000,
nano-x2, eden-x4, nano-x4, x86-64-v2, x86-64-v3 and x86-64-v4.
(i[34567]86-*-* | x86_64-*-*): Only allow x86-64-v* as argument
to --with-arch_64=.
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This change introduces support for the most recent versions
of VxWorks on PowerPC targets, for both 32 and 64 bit thanks
to a bi-arch setup.
The system compilers are essentially configured as Linux
toolchains with only a few specificities and we replicate
that model here.
The most visible specificities are the use of secureplt by
default, the pre-definition of some macros that the system
headers still rely on (_VX_CPU and _VX_CPU_FAMILY, for example),
and of course some variations related to the so VxWorks typical
kernel vs RTP mode distinction.
In addition to the introduction of config.gcc and libgcc
configuration chunks, much inspired by the linux ones, the
change
- Reworks rs6000/vxworks.h file to feature bits common to the
Vx6 and Vx7 port then a separate section for each, where the
Vx7 part is very short as we rely on the Linux definitions
for most things.
- Adjusts the CPU macro predefinitions in CPP_SPEC to resort
to "_VX_CPU" instead of "CPU" for Vx7, to better match the
more recent system headers expectations,
- Adds a cpu definition case for e6500.
- Changes to the use SUB3TARGET_OVERRIDE_OPTIONS instead of
SUBSUBTARGET_OVERRIDE_OPTIONS for specifics, so we don't
override the Linux's version of the latter for vx7.
2020-10-20 Douglas Rupp <rupp@adacore.com>
gcc/
* config.gcc (powerpc*-wrs-vxworks7r*): New case.
* config/rs6000/vxworks.h: Rework to handle VxWorks7.
Refactor as common bits + vx6 vs vx7 ones. For the
latter, rely essentially on the Linux configuration
and adjust CPU to _VX_CPU in CPP_SPEC. Add a case
for e6500. Use SUB3TARGET_OVERRIDE_OPTIONS for specifics
to preserve the Linux SUBSUBTARGET_OVERRIDE_OPTIONS
for vx7.
libgcc/
* config.host (powerpc*-wrs-vxworks7*): New case.
* configure.ac: Handle powerpc*-*-vxworks7* as
powerpc*-*-linux* for ppc-fp_type.
* configure: Regenerate.
Co-authored-by: Olivier Hainque <hainque@adacore.com>
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gcc/
* common/config/i386/cpuinfo.h (get_available_features):
Detect HRESET.
* common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET,
OPTION_MASK_ISA2_HRESET_UNSET): New macros.
(ix86_handle_option): Handle -mhreset.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_HRESET.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for hreset.
* config.gcc: Add hresetintrin.h
* config/i386/hresetintrin.h: New header file.
* config/i386/x86gprintrin.h: Include hresetintrin.h.
* config/i386/cpuid.h (bit_HRESET): New.
* config/i386/i386-builtin.def: Add new builtin.
* config/i386/i386-expand.c (ix86_expand_builtin):
Handle new builtin.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__HRESET__.
* config/i386/i386-options.c (isa2_opts): Add -mhreset.
(ix86_valid_target_attribute_inner_p): Handle hreset.
* config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P,
PTA_HRESET): New.
(PTA_ALDERLAKE): Add PTA_HRESET.
* config/i386/i386.opt: Add option -mhreset.
* config/i386/i386.md (UNSPECV_HRESET): New unspec.
(hreset): New define_insn.
* doc/invoke.texi: Document -mhreset.
* doc/extend.texi: Document hreset.
gcc/testsuite/
* gcc.target/i386/hreset-1.c: New test.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/x86gprintrin-1.c: Add -mhreset.
* gcc.target/i386/x86gprintrin-2.c: Ditto.
* gcc.target/i386/x86gprintrin-3.c: Ditto.
* gcc.target/i386/x86gprintrin-4.c: Add mhreset.
* gcc.target/i386/x86gprintrin-5.c: Ditto.
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2020-05-20 Hongtao Liu <hongtao.liu@intel.com>
gcc/
* common/config/i386/cpuinfo.h (get_available_features):
Detect UINTR.
* common/config/i386/i386-common.c (OPTION_MASK_ISA2_UINTR_SET
OPTION_MASK_ISA2_UINTR_UNSET): New.
(ix86_handle_option): Handle -muintr.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_UINTR.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY
for uintr.
* config.gcc: Add uintrintrin.h to extra_headers.
* config/i386/uintrintrin.h: New.
* config/i386/cpuid.h (bit_UINTR): New.
* config/i386/i386-builtin-types.def: Add new types.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Add
__builtin_ia32_testui.
* config/i386/i386-builtins.h (ix86_builtins): Add
IX86_BUILTIN_TESTUI.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__UINTR__.
* config/i386/i386-expand.c (ix86_expand_special_args_builtin):
Handle UINT8_FTYPE_VOID.
(ix86_expand_builtin): Handle IX86_BUILTIN_TESTUI.
* config/i386/i386-options.c (isa2_opts): Add -muintr.
(ix86_valid_target_attribute_inner_p): Handle UINTR.
(ix86_option_override_internal): Add TARGET_64BIT check for UINTR.
* config/i386/i386.h (TARGET_UINTR, TARGET_UINTR_P, PTA_UINTR): New.
(PTA_SAPPHIRRAPIDS): Add PTA_UINTR.
* config/i386/i386.opt: Add -muintr.
* config/i386/i386.md
(define_int_iterator UINTR_UNSPECV): New.
(define_int_attr uintr_unspecv): New.
(uintr_<uintr_unspecv>, uintr_senduipi, testui):
New define_insn patterns.
* config/i386/x86gprintrin.h: Include uintrintrin.h
* doc/invoke.texi: Document -muintr.
* doc/extend.texi: Document uintr.
gcc/testsuite/
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/uintr-1.c: New test.
* gcc.target/i386/uintr-2.c: Ditto.
* gcc.target/i386/uintr-3.c: Ditto.
* gcc.target/i386/uintr-4.c: Ditto.
* gcc.target/i386/uintr-5.c: Ditto.
* gcc.target/i386/x86gprintrin-1.c: Add -muintr for 64bit target.
* gcc.target/i386/x86gprintrin-2.c: Ditto.
* gcc.target/i386/x86gprintrin-3.c: Ditto.
* gcc.target/i386/x86gprintrin-4.c: Add muintr for 64bit target.
* gcc.target/i386/x86gprintrin-5.c: Ditto.
|
|
For sources which can't use any vector instructions, <x86intrin.h> and
<immintrin.h> cannot be included for compiler intrinsics:
$ echo "#include <x86intrin.h>" | gcc -S -O2 -mno-sse -mno-mmx -x c -
In file included from /usr/include/stdlib.h:1013,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/mm_malloc.h:27,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/xmmintrin.h:34,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:29,
from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32,
from <stdin>:1:
/usr/include/bits/stdlib-float.h: In function ‘atof’:
/usr/include/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled
26 | {
| ^
$
libgcc/config/i386/shadow-stack-unwind.h has a workaround:
/* NB: We need _get_ssp and _inc_ssp from <cetintrin.h>. But we can't
include <x86intrin.h> which ends up including <mm_malloc.h>, which
includes <stdlib.h> and <errno.h> unconditionally. But we can't
include any libc system headers unconditionally from libgcc. Avoid
including <mm_malloc.h> here by defining _IMMINTRIN_H_INCLUDED. */
#define _IMMINTRIN_H_INCLUDED
#include <cetintrin.h>
#undef _IMMINTRIN_H_INCLUDED
Add a standalone intrinsic header file, <x86gprintrin.h>, to provide
integer only intrinsics. All integer only intrinsics are placed in
<x86gprintrin.h>. <x86intrin.h> and <immintrin.h> simply include
<x86gprintrin.h>.
gcc/
PR target/97148
* config.gcc (extra_headers): Add x86gprintrin.h.
* config/i386/adxintrin.h: Check _X86GPRINTRIN_H_INCLUDED for
<x86gprintrin.h>.
* config/i386/bmi2intrin.h: Likewise.
* config/i386/bmiintrin.h: Likewise.
* config/i386/cetintrin.h: Likewise.
* config/i386/cldemoteintrin.h: Likewise.
* config/i386/clflushoptintrin.h: Likewise.
* config/i386/clwbintrin.h: Likewise.
* config/i386/enqcmdintrin.h: Likewise.
* config/i386/fxsrintrin.h: Likewise.
* config/i386/ia32intrin.h: Likewise.
* config/i386/lwpintrin.h: Likewise.
* config/i386/lzcntintrin.h: Likewise.
* config/i386/movdirintrin.h: Likewise.
* config/i386/pconfigintrin.h: Likewise.
* config/i386/pkuintrin.h: Likewise.
* config/i386/rdseedintrin.h: Likewise.
* config/i386/rtmintrin.h: Likewise.
* config/i386/serializeintrin.h: Likewise.
* config/i386/tbmintrin.h: Likewise.
* config/i386/tsxldtrkintrin.h: Likewise.
* config/i386/waitpkgintrin.h: Likewise.
* config/i386/wbnoinvdintrin.h: Likewise.
* config/i386/xsavecintrin.h: Likewise.
* config/i386/xsaveintrin.h: Likewise.
* config/i386/xsaveoptintrin.h: Likewise.
* config/i386/xsavesintrin.h: Likewise.
* config/i386/xtestintrin.h: Likewise.
* config/i386/immintrin.h: Include <x86gprintrin.h> instead of
<fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>,
<xsavesintrin.h>, <xsavecintrin.h>, <lzcntintrin.h>,
<bmiintrin.h>, <bmi2intrin.h>, <xtestintrin.h>, <cetintrin.h>,
<movdirintrin.h>, <sgxintrin.h, <pconfigintrin.h>,
<waitpkgintrin.h>, <cldemoteintrin.h>, <enqcmdintrin.h>,
<serializeintrin.h>, <tsxldtrkintrin.h>, <adxintrin.h>,
<clwbintrin.h>, <clflushoptintrin.h>, <wbnoinvdintrin.h> and
<pkuintrin.h>.
(_wbinvd): Moved to config/i386/x86gprintrin.h.
(_rdrand16_step): Likewise.
(_rdrand32_step): Likewise.
(_rdpid_u32): Likewise.
(_readfsbase_u32): Likewise.
(_readfsbase_u64): Likewise.
(_readgsbase_u32): Likewise.
(_readgsbase_u64): Likewise.
(_writefsbase_u32): Likewise.
(_writefsbase_u64): Likewise.
(_writegsbase_u32): Likewise.
(_writegsbase_u64): Likewise.
(_rdrand64_step): Likewise.
(_ptwrite64): Likewise.
(_ptwrite32): Likewise.
* config/i386/x86gprintrin.h: New file.
* config/i386/x86intrin.h: Include <x86gprintrin.h>. Don't
include <ia32intrin.h>, <lwpintrin.h>, <tbmintrin.h>,
<popcntintrin.h>, <mwaitxintrin.h> and <clzerointrin.h>.
gcc/testsuite/
* gcc.target/i386/avx-1.c (__builtin_ia32_lwpval32): New to
support <lwpintrin.h> included in <x86gprintrin.h>.
(__builtin_ia32_lwpval64): Likewise.
(__builtin_ia32_lwpins32): Likewise.
(__builtin_ia32_lwpins64): Likewise.
(__builtin_ia32_bextri_u32): New to support <tbmintrin.h>
included in <x86gprintrin.h>.
(__builtin_ia32_bextri_u64): Likewise.
* gcc.target/i386/x86gprintrin-1.c: New test.
* gcc.target/i386/x86gprintrin-2.c: Likewise.
* gcc.target/i386/x86gprintrin-3.c: Likewise.
* gcc.target/i386/x86gprintrin-4.c: Likewise.
* gcc.target/i386/x86gprintrin-4a.c: Likewise.
* gcc.target/i386/x86gprintrin-5.c: Likewise.
* gcc.target/i386/x86gprintrin-5a.c: Likewise.
* gcc.target/i386/x86gprintrin-5b.c: Likewise.
* gcc.target/i386/x86gprintrin-6.c: Likewise.
libgcc/
PR target/97148
* config/i386/shadow-stack-unwind.h: Include <x86gprintrin.h>
instead of <cetintrin.h>.
|
|
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease
AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud
AMX-BF16:tdpbf16ps
gcc/ChangeLog
* common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET,
OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET,
OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET,
OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET):
New marcos.
(ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16.
* common/config/i386/i386-cpuinfo.h (processor_types): Add
FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16.
* common/config/i386/cpuinfo.h (XSTATE_TILECFG,
XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro.
(get_available_features): Enable AMX features only if
their states are suoorited by OSXSAVE.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY
for amx-tile, amx-int8, amx-bf16.
* config.gcc: Add amxtileintrin.h, amxint8intrin.h,
amxbf16intrin.h to extra headers.
* config/i386/amxbf16intrin.h: New file.
* config/i386/amxint8intrin.h: Ditto.
* config/i386/amxtileintrin.h: Ditto.
* config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8):
New macro.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__AMX_TILE__, __AMX_INT8__, AMX_BF16__.
* config/i386/i386-options.c (ix86_target_string): Add
-mamx-tile, -mamx-int8, -mamx-bf16.
(ix86_option_override_internal): Handle AMX-TILE,
AMX-INT8, AMX-BF16.
* config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P,
TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P,
PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros.
* config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16.
* config/i386/immintrin.h: Include amxtileintrin.h,
amxint8intrin.h, amxbf16intrin.h.
* doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16.
* doc/extend.texi: Document amx-tile, amx-int8, amx-bf16.
* doc/sourcebuild.texi ((Effective-Target Keywords, Other
hardware attributes): Document amx_int8, amx_tile, amx_bf16.
gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_amx_tile,
check_effective_target_amx_int8,
check_effective_target_amx_bf16): New proc.
* g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/amx-check.h: New header file.
* gcc.target/i386/amxbf16-asmatt-1.c: New test.
* gcc.target/i386/amxint8-asmatt-1.c: New test.
* gcc.target/i386/amxtile-asmatt-1.c: Ditto.
* gcc.target/i386/amxbf16-asmintel-1.c: Ditto.
* gcc.target/i386/amxint8-asmintel-1.c: Ditto.
* gcc.target/i386/amxtile-asmintel-1.c: Ditto.
* gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto.
* gcc.target/i386/amxint8-dpbssd-2.c: Ditto.
* gcc.target/i386/amxint8-dpbsud-2.c: Ditto.
* gcc.target/i386/amxint8-dpbusd-2.c: Ditto.
* gcc.target/i386/amxint8-dpbuud-2.c: Ditto.
* gcc.target/i386/amxtile-2.c: Ditto.
|
|
gcc/ChangeLog:
* config.gcc (C-SKY): Set use_gcc_stdint=wrap for elf target.
|
|
BPF is an ELF-based target, so it definitely benefits from using
elfos.h. This patch makes the target to use it, and removes
superfluous definitions from bpf.h which are better defined in
elfos.h.
Note that BPF, despite being an ELF target, doesn't use DWARF. At
some point it will generate DWARF when generating xBPF (-mxbpf) and
BTF when generating plain eBPF, but for the time being it just
generates stabs.
2020-09-02 Jose E. Marchesi <jemarch@gnu.org>
gcc/
* config.gcc: Use elfos.h in bpf-*-* targets.
* config/bpf/bpf.h (MAX_OFILE_ALIGNMENT): Remove definition.
(COMMON_ASM_OP): Likewise.
(INIT_SECTION_ASM_OP): Likewise.
(FINI_SECTION_ASM_OP): Likewise.
(ASM_OUTPUT_SKIP): Likewise.
(ASM_OUTPUT_ALIGNED_COMMON): Likewise.
(ASM_OUTPUT_ALIGNED_LOCAL): Likewise.
|
|
gcc/ChangeLog:
2020-07-24 David Edelsohn <dje.gcc@gmail.com>
Clement Chigot <clement.chigot@atos.net>
* config.gcc (powerpc-ibm-aix7.1): Use t-aix64 and biarch64 for
cpu_is_64bit.
* config/rs6000/aix71.h (ASM_SPEC): Remove aix64 option.
(ASM_SPEC32): New.
(ASM_SPEC64): New.
(ASM_CPU_SPEC): Remove vsx and altivec options.
(CPP_SPEC_COMMON): Rename from CPP_SPEC.
(CPP_SPEC32): New.
(CPP_SPEC64): New.
(CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON..
(TARGET_DEFAULT): Use 64 bit mask if BIARCH.
(LIB_SPEC_COMMON): Rename from LIB_SPEC.
(LIB_SPEC32): New.
(LIB_SPEC64): New.
(LINK_SPEC_COMMON): Rename from LINK_SPEC.
(LINK_SPEC32): New.
(LINK_SPEC64): New.
(STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase.
(ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P.
(CPP_SPEC): Same.
(CPLUSPLUS_CPP_SPEC): Same.
(LIB_SPEC): Same.
(LINK_SPEC): Same.
(SUBTARGET_EXTRA_SPECS): Add new 32/64 specs.
* config/rs6000/aix72.h (TARGET_DEFAULT): Use 64 bit mask if BIARCH.
* config/rs6000/defaultaix64.h: Delete.
|
|
gcc/
* common/config/i386/cpuinfo.h
(get_intel_cpu): Handle sapphirerapids.
* common/config/i386/i386-common.c
(processor_names): Add sapphirerapids and alderlake.
(processor_alias_table): Add sapphirerapids and alderlake.
* common/config/i386/i386-cpuinfo.h
(processor_subtypes): Add INTEL_COREI7_ALDERLAKE and
INTEL_COREI7_ALDERLAKE.
* config.gcc: Add -march=sapphirerapids and alderlake.
* config/i386/driver-i386.c
(host_detect_local_cpu) Handle sapphirerapids and alderlake.
* config/i386/i386-c.c
(ix86_target_macros_internal): Handle sapphirerapids and alderlake.
* config/i386/i386-options.c
(m_SAPPHIRERAPIDS) : Define.
(m_ALDERLAKE): Ditto.
(m_CORE_AVX512) : Add m_SAPPHIRERAPIDS.
(processor_cost_table): Add sapphirerapids and alderlake.
(ix86_option_override_internal) Handle PTA_WAITPKG, PTA_ENQCMD,
PTA_CLDEMOTE, PTA_SERIALIZE, PTA_TSXLDTRK.
* config/i386/i386.h
(ix86_size_cost) : Define SAPPHIRERAPIDS and ALDERLAKE.
(processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and
PROCESSOR_ALDERLAKE.
(PTA_ENQCMD): New.
(PTA_CLDEMOTE): Ditto.
(PTA_SERIALIZE): Ditto.
(PTA_TSXLDTRK): New.
(PTA_SAPPHIRERAPIDS): Ditto.
(PTA_ALDERLAKE): Ditto.
(processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and
PROCESSOR_ALDERLAKE.
* doc/extend.texi: Add sapphirerapids and alderlake.
* doc/invoke.texi: Add sapphirerapids and alderlake.
gcc/testsuite/
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.target/i386/mv16.C: Handle new march
|
|
Update config.gcc so that we can use --with-cpu=power10.
Also remove "future" from the 64-bit check as Segher suggests.
* config.gcc: Identify power10 as a 64-bit processor and as valid
for --with-cpu and --with-tune.
|
|
This patch adds the ability to configure GCC on AIX to build as a
64 bit application and to build target libraries "FAT" libraries in both
32 bit and 64 bit mode.
The patch adds makefile fragment hooks to target libraries that allows
them to include target-specific rules. The target specific rules for
AIX place both 32 bit and 64 bit objects and shared objects
in archives at the top-level, not multilib subdirectories. The
multilibs are built in subdirectories, but must be combined during the
last parts of the target library build process. Because of the way
that GCC bootstrap works, the libraries must be combined during the
multiple stages of GCC bootstrap, not solely when installed in the
final destination, so the libraries are correct at the end of
each target library build stage, not solely an install recipe.
gcc/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* config.gcc: Use t-aix64, biarch64 and default64 for cpu_is_64bit.
* config/rs6000/aix72.h (ASM_SPEC): Remove aix64 option.
(ASM_SPEC32): New.
(ASM_SPEC64): New.
(ASM_CPU_SPEC): Remove vsx and altivec options.
(CPP_SPEC_COMMON): Rename from CPP_SPEC.
(CPP_SPEC32): New.
(CPP_SPEC64): New.
(CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON..
(TARGET_DEFAULT): Only define if not BIARCH.
(LIB_SPEC_COMMON): Rename from LIB_SPEC.
(LIB_SPEC32): New.
(LIB_SPEC64): New.
(LINK_SPEC_COMMON): Rename from LINK_SPEC.
(LINK_SPEC32): New.
(LINK_SPEC64): New.
(STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase.
(ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P.
(CPP_SPEC): Same.
(CPLUSPLUS_CPP_SPEC): Same.
(LIB_SPEC): Same.
(LINK_SPEC): Same.
(SUBTARGET_EXTRA_SPECS): Add new 32/64 specs.
* config/rs6000/defaultaix64.h: New file.
* config/rs6000/t-aix64: New file.
libgcc/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* config.host (extra_parts): Add crtcxa_64 and crtdbase_64.
* config/rs6000/t-aix-cxa: Explicitly compile 32 bit with -maix32
and 64 bit with -maix64.
* config/rs6000/t-slibgcc-aix: Remove extra @multilib_dir@ level.
Build and install AIX-style FAT libraries.
libgomp/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.
libstdc++-v3/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host (aix*): Define tmake_file.
* config/os/aix/t-aix: New file.
libatomic/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.tgt (powerpc-ibm-aix*): Define tmake_file.
* config/t-aix: New file.
libgfortran/ChangeLog
2020-06-21 David Edelsohn <dje.gcc@gmail.com>
* Makefile.am (tmake_file): Build and install AIX-style FAT libraries.
* Makefile.in: Regenerate.
* configure.ac (tmake_file): Substitute.
* configure: Regenerate.
* configure.host: Add system configury stanza. Define tmake_file.
* config/t-aix: New file.
|
|
In the removal of arm-wrs-vxworks, the default cpu was updated from arm8
to armv7-a, but this is not recognized as a valid -mcpu target. There
is however generic-armv7-a, which was likely the intended cpu that
should have been used instead.
gcc/ChangeLog:
PR target/95420
* config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a.
|
|
gcc/
* config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
* config/riscv/riscv-passes.def: New file.
* config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
* config/riscv/riscv-shorten-memrefs.c: New file.
* config/riscv/riscv.c (tree-pass.h): New include.
(riscv_compressed_reg_p): New Function
(riscv_compressed_lw_offset_p): Likewise.
(riscv_compressed_lw_address_p): Likewise.
(riscv_shorten_lw_offset): Likewise.
(riscv_legitimize_address): Attempt to convert base + large_offset
to compressible new_base + small_offset.
(riscv_address_cost): Make anticipated compressed load/stores
cheaper for code size than uncompressed load/stores.
(riscv_register_priority): Move compressed register check to
riscv_compressed_reg_p.
* config/riscv/riscv.h (C_S_BITS): Define.
(CSW_MAX_OFFSET): Define.
* config/riscv/riscv.opt (mshorten-memefs): New option.
* config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
(PASSES_EXTRA): Add riscv-passes.def.
* doc/invoke.texi: Document -mshorten-memrefs.
* config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
(TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
* sched-deps.c (attempt_change): Use old address if it is cheaper than
new address.
* target.def (new_address_profitable_p): New hook.
* targhooks.c (default_new_address_profitable_p): New function.
* targhooks.h (default_new_address_profitable_p): Declare.
gcc/testsuite/
* gcc.target/riscv/shorten-memrefs-1.c: New test.
* gcc.target/riscv/shorten-memrefs-2.c: New test.
* gcc.target/riscv/shorten-memrefs-3.c: New test.
* gcc.target/riscv/shorten-memrefs-4.c: New test.
* gcc.target/riscv/shorten-memrefs-5.c: New test.
* gcc.target/riscv/shorten-memrefs-6.c: New test.
* gcc.target/riscv/shorten-memrefs-7.c: New test.
|
|
Or really, move from the obsolete targets section, to
unsupported targets section, and remove crisv32-*-* and
cris-*-linux* from the rest.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
gcc:
* config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
|
|
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
* config.gcc: Add tsxldtrkintrin.h to extra_headers.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
TSXLDTRK.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__TSXLDTRK__.
* config/i386/i386-options.c (ix86_target_string): Add
-mtsxldtrk.
(ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
* config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
New.
* config/i386/i386.md (define_c_enum "unspec"): Add
UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
(TSXLDTRK): New define_int_iterator.
("<tsxldtrk>"): New define_insn.
* config/i386/i386.opt: Add -mtsxldtrk.
* config/i386/immintrin.h: Include tsxldtrkintrin.h.
* config/i386/tsxldtrkintrin.h: New.
* doc/invoke.texi: Document -mtsxldtrk.
gcc/testsuite/
* g++.dg/other/i386-2.c: Add -mtsxldtrk.
* g++.dg/other/i386-3.c: Likewise.
* gcc.target/i386/sse-12.c: Likewise.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-14.c: Likewise.
* gcc.target/i386/sse-22.c: Likewsie.
* gcc.target/i386/sse-23.c: Likewise.
* gcc.target/i386/tsxldtrk-1.c: New test.
* gcc.target/i386/funcspec-56.inc: Add target attribute tests
for tsxldtrk.
|
|
2020-03-04 Hongtao Liu <hongtao.liu@intel.com>
2020-03-04 Wei Xiao <wei3.xiao@intel.com>
gcc/Changelog:
* gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
(ix86_handle_option): Handle -mserialize.
* gcc/config.gcc (serializeintrin.h): New header file.
* gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit.
* gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect
-mserialize.
* gcc/config/i386/i386-builtin.def: Add new builtin.
* gcc/config/i386/i386-c.c (__SERIALIZE__): New macro.
* gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts):
Add -mserialize.
* (ix86_valid_target_attribute_inner_p): Add target attribute
* for serialize.
* gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
New macros.
* gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
(serialize): New define_insn.
* gcc/config/i386/i386.opt (mserialize): New option
* gcc/config/i386/immintrin.h: Include serailizeintrin.h.
* gcc/config/i386/serializeintrin.h: New header file.
* gcc/doc/invoke.texi: Add documents for -mserialize.
gcc/testsuite/Changelog
* gcc/testsuite/gcc.target/i386/serialize-1.c: New test.
* gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize.
* gcc/testsuite/g++.dg/other/i386-3.C: Ditto.
* gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto.
* gcc/testsuite/gcc.target/i386/sse-12.c: Ditto.
* gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.
* gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.
* gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.
* gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
|
|
Implement CDE intrinsics on MVE registers.
Other than the basics required for adding intrinsics this patch consists
of three changes.
** We separate out the MVE types and casts from the arm_mve.h header.
This is so that the types can be used in arm_cde.h without the need to include
the entire arm_mve.h header.
The only type that arm_cde.h needs is `uint8x16_t`, so this separation could be
avoided by using a `typedef` in this file.
Since the introduced intrinsics are all defined to act on the full range of MVE
types, declaring all such types seems intuitive since it will provide their
declaration to the user too.
This arm_mve_types.h header not only includes the MVE types, but also
the conversion intrinsics between them.
Some of the conversion intrinsics are needed for arm_cde.h, but most are
not. We include all conversion intrinsics to keep the definition of
such conversion functions all in one place, on the understanding that
extra conversion functions being defined when including `arm_cde.h` is
not a problem.
** We define the TARGET_RESOLVE_OVERLOADED_BUILTIN hook for the Arm backend.
This is needed to implement the polymorphism for the required intrinsics.
The intrinsics have no specialised version, and the resulting assembly
instruction for all different types should be exactly the same.
Due to this we have implemented these intrinsics via one builtin on one type.
All other calls to the intrinsic with different types are implicitly cast to
the one type that is defined, and hence are all expanded to the same RTL
pattern that is only defined for one machine mode.
** We seperate the initialisation of the CDE intrinsics from others.
This allows us to ensure that the CDE intrinsics acting on MVE registers
are only created when both CDE and MVE are available.
Only initialising these builtins when both features are available is
especially important since they require a type that is only initialised
when the target supports hard float. Hence trying to initialise these
builtins on a soft float target would cause an ICE.
Testing done:
Full bootstrap and regtest on arm-none-linux-gnueabihf
Regression test on arm-none-eabi
Ok for trunk?
gcc/ChangeLog:
2020-03-10 Matthew Malcomson <matthew.malcomson@arm.com>
* config.gcc (arm_mve_types.h): New extra_header for arm.
* config/arm/arm-builtins.c (arm_resolve_overloaded_builtin): New.
(arm_init_cde_builtins): New.
(arm_init_acle_builtins): Remove initialisation of CDE builtins.
(arm_init_builtins): Call arm_init_cde_builtins when target
supports CDE.
* config/arm/arm-c.c (arm_resolve_overloaded_builtin): New declaration.
(arm_register_target_pragmas): Initialise resolve_overloaded_builtin
hook to the implementation for the arm backend.
* config/arm/arm.h (ARM_MVE_CDE_CONST_1): New.
(ARM_MVE_CDE_CONST_2): New.
(ARM_MVE_CDE_CONST_3): New.
* config/arm/arm_cde.h (__arm_vcx1q_u8): New.
(__arm_vcx1qa): New.
(__arm_vcx2q): New.
(__arm_vcx2q_u8): New.
(__arm_vcx2qa): New.
(__arm_vcx3q): New.
(__arm_vcx3q_u8): New.
(__arm_vcx3qa): New.
* config/arm/arm_cde_builtins.def (vcx1q, vcx1qa, vcx2q, vcx2qa, vcx3q,
vcx3qa): New builtins defined.
* config/arm/arm_mve.h: Move typedefs and conversion intrinsics
to arm_mve_types.h header.
* config/arm/arm_mve_types.h: New file.
* config/arm/mve.md (arm_vcx1qv16qi, arm_vcx1qav16qi, arm_vcx2qv16qi,
arm_vcx2qav16qi, arm_vcx3qv16qi, arm_vcx3qav16qi): New patterns.
* config/arm/predicates.md (const_int_mve_cde1_operand,
const_int_mve_cde2_operand, const_int_mve_cde3_operand): New.
gcc/testsuite/ChangeLog:
2020-03-23 Matthew Malcomson <matthew.malcomson@arm.com>
Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/acle/cde-mve-error-1.c: New test.
* gcc.target/arm/acle/cde-mve-error-2.c: New test.
* gcc.target/arm/acle/cde-mve-error-3.c: New test.
* gcc.target/arm/acle/cde-mve-full-assembly.c: New test.
* gcc.target/arm/acle/cde-mve-tests.c: New test.
* lib/target-supports.exp (arm_v8_1m_main_cde_mve_fp): New check
effective.
(arm_v8_1m_main_cde_mve, arm_v8m_main_cde_fp): Use -mfpu=auto
so we only check configurations that make sense.
|
|
This patch is part of a series that adds support for the Arm Custom
Datapath Extension. It defines the options cdecp0-cdecp7 for CLI to
enable the CDE on corresponding coprocessor 0-7.
It also adds new target supports for CDE feature testsuite.
gcc/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
* config.gcc: Add arm_cde.h.
* config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
__ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
* config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
* config/arm/arm.c (arm_option_reconfigure_globals): Configure
arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
* config/arm/arm.h (TARGET_CDE): New macro.
* config/arm/arm_cde.h: New file.
* doc/invoke.texi: Document CDE options +cdecp[0-7].
* doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
supports option.
(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
gcc/testsuite/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/pragma_cde.c: New test.
* lib/target-supports.exp (arm_v8m_main_cde_ok): New target support
option.
(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
|
|
This patch creates the required framework for MVE ACLE intrinsics.
The following changes are done in this patch to support MVE ACLE intrinsics.
Header file arm_mve.h is added to source code, which contains the definitions of MVE ACLE intrinsics
and different data types used in MVE. Machine description file mve.md is also added which contains the
RTL patterns defined for MVE.
A new reigster "p0" is added which is used in by MVE predicated patterns. A new register class "VPR_REG"
is added and its contents are defined in REG_CLASS_CONTENTS.
The vec-common.md file is modified to support the standard move patterns. The prefix of neon functions
which are also used by MVE is changed from "neon_" to "simd_".
eg: neon_immediate_valid_for_move changed to simd_immediate_valid_for_move.
In the patch standard patterns mve_move, mve_store and move_load for MVE are added and neon.md and vfp.md
files are modified to support this common patterns.
Please refer to Arm reference manual [1] for more details.
[1] https://developer.arm.com/docs/ddi0553/latest
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config.gcc (arm_mve.h): Include mve intrinsics header file.
* config/arm/aout.h (p0): Add new register name for MVE predicated
cases.
* config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
common to Neon and MVE.
(ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
(arm_init_simd_builtin_types): Disable poly types for MVE.
(arm_init_neon_builtins): Move a check to arm_init_builtins function.
(arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
ARM_BUILTIN_NEON_LANE_CHECK.
(mve_dereference_pointer): Add function.
(arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
enabled.
(arm_expand_neon_builtin): Moved to arm_expand_builtin function.
(arm_expand_builtin): Moved from arm_expand_neon_builtin function.
* config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
with floating point enabled.
* config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
simd_immediate_valid_for_move.
(simd_immediate_valid_for_move): Renamed from
neon_immediate_valid_for_move function.
* config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
error if vfpv2 feature bit is disabled and mve feature bit is also
disabled for HARD_FLOAT_ABI.
(use_return_insn): Check to not push VFP regs for MVE.
(aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
as Neon.
(aapcs_vfp_allocate_return_reg): Likewise.
(thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
address operand for MVE.
(arm_rtx_costs_internal): MVE check to determine cost of rtx.
(neon_valid_immediate): Rename to simd_valid_immediate.
(simd_valid_immediate): Rename from neon_valid_immediate.
(simd_valid_immediate): MVE check on size of vector is 128 bits.
(neon_immediate_valid_for_move): Rename to
simd_immediate_valid_for_move.
(simd_immediate_valid_for_move): Rename from
neon_immediate_valid_for_move.
(neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
function.
(neon_make_constant): Modify call to neon_valid_immediate function.
(neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
for MVE.
(output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
(arm_compute_frame_layout): Calculate space for saved VFP registers for
MVE.
(arm_save_coproc_regs): Save coproc registers for MVE.
(arm_print_operand): Add case 'E' to print memory operands for MVE.
(arm_print_operand_address): Check to print register number for MVE.
(arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
(arm_modes_tieable_p): Check to allow structure mode for MVE.
(arm_regno_class): Add VPR_REGNUM check.
(arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
for APCS frame.
(arm_expand_epilogue): MVE check for enabling pop instructions in
epilogue.
(arm_print_asm_arch_directives): Modify function to disable print of
.arch_extension "mve" and "fp" for cases where MVE is enabled with
"SOFT FLOAT ABI".
(arm_vector_mode_supported_p): Check for modes available in MVE interger
and MVE floating point.
(arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
pointer support.
(arm_conditional_register_usage): Enable usage of conditional regsiter
for MVE.
(fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
(arm_declare_function_name): Modify function to disable print of
.arch_extension "mve" and "fp" for cases where MVE is enabled with
"SOFT FLOAT ABI".
* config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
when target general registers are required.
(TARGET_HAVE_MVE_FLOAT): Likewise.
(FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
for MVE.
(CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
which indicate this is not available for across function calls.
(FIRST_PSEUDO_REGISTER): Modify.
(VALID_MVE_MODE): Define valid MVE mode.
(VALID_MVE_SI_MODE): Define valid MVE SI mode.
(VALID_MVE_SF_MODE): Define valid MVE SF mode.
(VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
(VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
for MVE.
(IS_VPR_REGNUM): Macro to check for VPR_REG register.
(REG_ALLOC_ORDER): Add VPR_REGNUM entry.
(enum reg_class): Add VPR_REG entry.
(REG_CLASS_NAMES): Add VPR_REG entry.
* config/arm/arm.md (VPR_REGNUM): Define.
(conds): Check is_mve_type attrbiute to differentiate "conditional" and
"unconditional" instructions.
(arm_movsf_soft_insn): Modify RTL to not allow for MVE.
(movdf_soft_insn): Modify RTL to not allow for MVE.
(vfp_pop_multiple_with_writeback): Enable for MVE.
(include "mve.md"): Include mve.md file.
* config/arm/arm_mve.h: Add MVE intrinsics head file.
* config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
for vector predicated operands.
* config/arm/iterators.md (VNIM1): Define.
(VNINOTM1): Define.
(VHFBF_split): Define
* config/arm/mve.md: New file.
(mve_mov<mode>): Define RTL for move, store and load in MVE.
(mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
second operand.
* config/arm/neon.md (neon_immediate_valid_for_move): Rename with
simd_immediate_valid_for_move.
(neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
is common to MVE and NEON to vec-common.md file.
(vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
* config/arm/predicates.md (vpr_register_operand): Define.
* config/arm/t-arm: Add mve.md file.
* config/arm/types.md (mve_move): Add MVE instructions mve_move to
attribute "type".
(mve_store): Add MVE instructions mve_store to attribute "type".
(mve_load): Add MVE instructions mve_load to attribute "type".
(is_mve_type): Define attribute.
* config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
standard move patterns in MVE along with NEON and IWMMXT with mode
iterator VNIM1.
(mov<mode>): Modify RTL expand to support standard move patterns in NEON
and IWMMXT with mode iterator V8HF.
(movv8hf): Define RTL expand to support standard "movv8hf" pattern in
NEON and MVE.
* config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
simd_immediate_valid_for_move.
2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
* gcc.target/arm/mve/mve.exp: New file.
* lib/target-supports.exp
(check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check
armv8.1-m.main+mve.fp and returning corresponding options.
(check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call
check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of
MVE with floating point on the current target.
(add_options_for_arm_v8_1m_mve_fp): Proc to call
check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding
compiler options for MVE with floating point.
(check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and
return hard float-abi on success.
|
|
Building a zTPF cross currently fails when building libstdc++
complaining about the __UINTPTR_TYPE__ to be missing.
Fixed by including the glibc-stdint.h header.
2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
* config.gcc: Include the glibc-stdint.h header for zTPF.
|
|
2020-02-03 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config.gcc: Remove "carrizo" support.
* config/gcn/gcn-opts.h (processor_type): Likewise.
* config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
* config/gcn/gcn.opt (gpu_type): Likewise.
* config/gcn/t-omp-device: Likewise.
libgomp/
* plugin/plugin-gcn.c (EF_AMDGPU_MACH_AMDGCN_GFX801): Remove.
(gcn_gfx801_s): Remove.
(isa_hsa_name): Remove gfx801.
(isa_gcc_name): Remove gfx801/carizzo.
(isa_code): Remove gfx801.
|
|
I'm sorry to say that there's no incentive to maintain
crisv32-*-* and cris-*-linux* configurations beyond nostalgia,
(and I'm out of that for the moment). Support in the Linux
kernel for either applicable CRIS variant (CRIS v10 and CRIS
v32) is gone since 2018. Their related part of the cc0
transition workload would be noticable. Note that cris-elf
remains, but crisv32-elf and the CRIS v32 multilib will be
removed, at least for now.
I'm not completely happy about the message (the next-next line
after the context) "*** unless a maintainer comes forward"
because it'd have to be at an infinitesimal maintenance cost to
the cris-elf support. Still, I'm not bothered enough to add
another case construct or means for "planned obsolescence".
|
|
to ARM back-end [1/2]
gcc/ChangeLog:
2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config.gcc: Add arm_bf16.h.
* config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
(arm_simd_builtin_std_type): Add BFmode.
(arm_init_simd_builtin_types): Define element types for vector types.
(arm_init_bf16_types): New function.
(arm_init_builtins): Add arm_init_bf16_types function call.
* config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
* config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
* config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
(arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
(arm_vector_mode_supported_p): Add V4BF, V8BF.
(arm_mangle_type): Add __bf16.
* config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
arm_bf16_ptr_type_node.
* config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
define_split between ARM registers.
* config/arm/arm_bf16.h: New file.
* config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
* config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
(VQXMOV): Add V8BF.
* config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
* config/arm/vfp.md: Add BFmode to movhf patterns.
gcc/testsuite/ChangeLog:
2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* g++.dg/abi/mangle-neon.C: Add BF16 SIMD types.
* g++.dg/ext/arm-bf16/bf16-mangle-1.C: New test.
* gcc.target/arm/bfloat16_scalar_1_1.c: New test.
* gcc.target/arm/bfloat16_scalar_1_2.c: New test.
* gcc.target/arm/bfloat16_scalar_2_1.c: New test.
* gcc.target/arm/bfloat16_scalar_2_2.c: New test.
* gcc.target/arm/bfloat16_scalar_3_1.c: New test.
* gcc.target/arm/bfloat16_scalar_3_2.c: New test.
* gcc.target/arm/bfloat16_scalar_4.c: New test.
* gcc.target/arm/bfloat16_simd_1_1.c: New test.
* gcc.target/arm/bfloat16_simd_1_2.c: New test.
* gcc.target/arm/bfloat16_simd_2_1.c: New test.
* gcc.target/arm/bfloat16_simd_2_2.c: New test.
* gcc.target/arm/bfloat16_simd_3_1.c: New test.
* gcc.target/arm/bfloat16_simd_3_2.c: New test.
|
|
2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config.gcc: Add arm_bf16.h.
* config/aarch64/aarch64-builtins.c
(aarch64_simd_builtin_std_type): Add BFmode.
(aarch64_init_simd_builtin_types): Define element types for vector
types.
(aarch64_init_bf16_types): New function.
(aarch64_general_init_builtins): Add arm_init_bf16_types function call.
* config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
modes.
* config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
* config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
patterns.
* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
(AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
* config/aarch64/aarch64.c
(aarch64_classify_vector_mode): Add support for BF types.
(aarch64_gimplify_va_arg_expr): Add support for BF types.
(aarch64_vq_mode): Add support for BF types.
(aarch64_simd_container_mode): Add support for BF types.
(aarch64_mangle_type): Add support for BF scalar type.
* config/aarch64/aarch64.md: Add BFmode to movhf pattern.
* config/aarch64/arm_bf16.h: New file.
* config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
* config/aarch64/iterators.md: Add BF types to mode attributes.
(HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* g++.dg/abi/mangle-neon-aarch64.C: Add Bfloat SIMD types to test.
* g++.dg/ext/arm-bf16/bf16-mangle-aarch64-1.C: New test.
* gcc.target/aarch64/bfloat16_scalar_1.c: New test.
* gcc.target/aarch64/bfloat16_scalar_2.c: New test.
* gcc.target/aarch64/bfloat16_scalar_3.c: New test.
* gcc.target/aarch64/bfloat16_scalar_4.c: New test.
* gcc.target/aarch64/bfloat16_simd_1.c: New test.
* gcc.target/aarch64/bfloat16_simd_2.c: New test.
* gcc.target/aarch64/bfloat16_simd_3.c: New test.
From-SVN: r280129
|
|
This patch adds support for the SVE2 ACLE, The implementation
and tests follow the same pattern as the exiting SVE ACLE support.
2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
extra_objs.
* config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
aarch64-sve-builtins-sve2.h.
(aarch64-sve-builtins-sve2.o): New rule.
* config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
(AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
(AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
(TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
TARGET_SVE2_SM4.
* config/aarch64/aarch64-sve.md: Update comments with SVE2
instructions that are handled here.
(@cond_asrd<mode>): Generalize to...
(@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
(*cond_asrd<mode>_2): Generalize to...
(*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
(*cond_asrd<mode>_z): Generalize to...
(*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
* config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
(UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
(UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
pattern.
(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
(@aarch64_scatter_stnt<mode>): Likewise.
(@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
(@aarch64_mul_lane_<mode>): Likewise.
(@aarch64_sve_suqadd<mode>_const): Likewise.
(*<sur>h<addsub><mode>): Generalize to...
(@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
new pattern.
(@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
(*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
(*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
(@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
(@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
(@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
(@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
(*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
(@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
(@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_add_mul_lane_<mode>): Likewise.
(@aarch64_sve_sub_mul_lane_<mode>): Likewise.
(@aarch64_sve2_xar<mode>): Likewise.
(@aarch64_sve2_bcax<mode>): Likewise.
(*aarch64_sve2_eor3<mode>): Rename to...
(@aarch64_sve2_eor3<mode>): ...this.
(@aarch64_sve2_bsl<mode>): New expander.
(@aarch64_sve2_nbsl<mode>): Likewise.
(@aarch64_sve2_bsl1n<mode>): Likewise.
(@aarch64_sve2_bsl2n<mode>): Likewise.
(@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
(*aarch64_sve2_sra<mode>): Add MOVPRFX support.
(@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
(@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
(@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
(*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
(@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
(<su>mull<bt><Vwide>): Generalize to...
(@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
pattern.
(@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
(@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
(@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
(@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
(@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
(@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
(@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
(@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
(@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
(@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
(@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
(@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
(<SHRNB:r>shrnb<mode>): Generalize to...
(@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
new pattern.
(<SHRNT:r>shrnt<mode>): Generalize to...
(@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
new pattern.
(@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
(@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
(@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
(*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
(*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
(@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
(@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
(@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
(@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
(@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
(@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
(@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
(*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
(@aarch64_sve2_cvtnt<mode>): Likewise.
(@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
(@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
(*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
(@aarch64_sve2_cvtxnt<mode>): Likewise.
(@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
(@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
(*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
(@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
(@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
(*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
(@aarch64_sve2_pmul<mode>): Likewise.
(@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
(@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
(@aarch64_sve2_tbl2<mode>): Likewise.
(@aarch64_sve2_tbx<mode>): Likewise.
(@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
(@aarch64_sve2_histcnt<mode>): Likewise.
(@aarch64_sve2_histseg<mode>): Likewise.
(@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
(*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
(*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
(aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
(aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
(*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
(aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
(<su>mulh<r>s<mode>3): Update after above pattern name changes.
* config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
(SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
(SVE2_PMULL_PAIR_I): New mode iterators.
(UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
(UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
(UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
(UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
(UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
(UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
(UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
(UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
(UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
(UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
(UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
(UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
(UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
(UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
(UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
(UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
(UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
(UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
(UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
(UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
(UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
(UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
(UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
(UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
(UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
(UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
(UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
(UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
(UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
(UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
(UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
further down file.
(VNARROW, Ventype): New mode attributes.
(Vewtype): Handle VNx2DI. Fix typo in comment.
(VDOUBLE): New mode attribute.
(sve_lane_con): Handle VNx8HI.
(SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
(SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
(sve_int_op, sve_int_op_rev): Handle the above codes.
(sve_pred_int_rhs2_operand): Likewise.
(MULLBT, SHRNB, SHRNT): Delete.
(SVE_INT_SHIFT_IMM): New int iterator.
(SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
and UNSPEC_WHILEHS for TARGET_SVE2.
(SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
(SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
(SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
(SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
(SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
(SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
(SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
(SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
(SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
(SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
(SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
(SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
(SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
(SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
(SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
(SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
(SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
(optab): Handle the new unspecs.
(su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
and UNSPEC_RSHRNT.
(lr): Handle the new unspecs.
(bt): Delete.
(cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
(sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
(sve_int_qsub_op): New int attributes.
(sve_fp_op, rot): Handle the new unspecs.
* config/aarch64/aarch64-sve-builtins.h
(function_resolver::require_matching_pointer_type): Declare.
(function_resolver::resolve_unary): Add an optional boolean argument.
(function_resolver::finish_opt_n_resolution): Add an optional
type_suffix_index argument.
(gimple_folder::redirect_call): Declare.
(gimple_expander::prepare_gather_address_operands): Add an optional
bool parameter.
* config/aarch64/aarch64-sve-builtins.cc: Include
aarch64-sve-builtins-sve2.h.
(TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
(TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
(TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
(TYPES_hsd_integer): Use TYPES_hsd_signed.
(TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
(TYPES_s_unsigned): Likewise.
(TYPES_s_integer): Use TYPES_s_unsigned.
(TYPES_sd_signed, TYPES_sd_unsigned): New macros.
(TYPES_sd_integer): Use them.
(TYPES_d_unsigned): New macro.
(TYPES_d_integer): Use it.
(TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
(TYPES_cvt_narrow): Likewise.
(DEF_SVE_TYPES_ARRAY): Include the new types macros above.
(preds_mx): New variable.
(function_builder::add_overloaded_function): Allow the new feature
set to be more restrictive than the original one.
(function_resolver::infer_pointer_type): Remove qualifiers from
the pointer type before printing it.
(function_resolver::require_matching_pointer_type): New function.
(function_resolver::resolve_sv_displacement): Handle functions
that don't support 32-bit vector indices or svint32_t vector offsets.
(function_resolver::finish_opt_n_resolution): Take the inferred type
as a separate argument.
(function_resolver::resolve_unary): Optionally treat all forms in
the same way as normal merging functions.
(gimple_folder::redirect_call): New function.
(function_expander::prepare_gather_address_operands): Add an argument
that says whether scaled forms are available. If they aren't,
handle scaling of vector indices and don't add the extension and
scaling operands.
(function_expander::map_to_unspecs): If aarch64_sve isn't available,
fall back to using cond_* instead.
* config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
Split out the member variables into...
(rtx_code_function_base): ...this new base class.
(rtx_code_function_rotated): Inherit rtx_code_function_base.
(unspec_based_function): Split out the member variables into...
(unspec_based_function_base): ...this new base class.
(unspec_based_function_rotated): Inherit unspec_based_function_base.
(unspec_based_function_exact_insn): New class.
(unspec_based_add_function, unspec_based_add_lane_function)
(unspec_based_lane_function, unspec_based_pred_function)
(unspec_based_qadd_function, unspec_based_qadd_lane_function)
(unspec_based_qsub_function, unspec_based_qsub_lane_function)
(unspec_based_sub_function, unspec_based_sub_lane_function): New
typedefs.
(unspec_based_fused_function): New class.
(unspec_based_mla_function, unspec_based_mls_function): New typedefs.
(unspec_based_fused_lane_function): New class.
(unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
typedefs.
(CODE_FOR_MODE1): New macro.
(fixed_insn_function): New class.
(while_comparison): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
(binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
(binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
(load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
(load_gather_sv_restricted, shift_left_imm_long): Declare.
(shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
(shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
(shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
(store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
(ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
(ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
(unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
(unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
Also add an initial argument for unary_convert_narrowt, regardless
of the predication type.
(build_32_64): Allow loads and stores to specify MODE_none.
(build_sv_index64, build_sv_uint_offset): New functions.
(long_type_suffix): New function.
(binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
(binary_imm_long_base, load_gather_sv_base): Likewise.
(shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
(ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
(unary_narrowb_base, unary_narrowt_base): Likewise.
(binary_long_lane_def, binary_long_lane): New shape.
(binary_long_opt_n_def, binary_long_opt_n): Likewise.
(binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
(binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
(binary_to_uint_def, binary_to_uint): Likewise.
(binary_wide_def, binary_wide): Likewise.
(binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
(compare_def, compare): Likewise.
(compare_ptr_def, compare_ptr): Likewise.
(load_ext_gather_index_restricted_def,
load_ext_gather_index_restricted): Likewise.
(load_ext_gather_offset_restricted_def,
load_ext_gather_offset_restricted): Likewise.
(load_gather_sv_def): Inherit from load_gather_sv_base.
(load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
(shift_left_imm_def, shift_left_imm): Likewise.
(shift_left_imm_long_def, shift_left_imm_long): Likewise.
(shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
(store_scatter_index_restricted_def,
store_scatter_index_restricted): Likewise.
(store_scatter_offset_restricted_def,
store_scatter_offset_restricted): Likewise.
(tbl_tuple_def, tbl_tuple): Likewise.
(ternary_long_lane_def, ternary_long_lane): Likewise.
(ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
(ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
(ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
(ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
(ternary_qq_rotate_def, ternary_qq_rotate): New shape.
(ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
(ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
(ternary_uint_def, ternary_uint): Likewise.
(unary_convert): Fix typo in comment.
(unary_convert_narrowt_def, unary_convert_narrowt): New shape.
(unary_long_def, unary_long): Likewise.
(unary_narrowb_def, unary_narrowb): Likewise.
(unary_narrowt_def, unary_narrowt): Likewise.
(unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
(unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
(unary_to_int_def, unary_to_int): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
(unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
(svasrd_impl): Delete.
(svcadd_impl::expand): Handle integer operations too.
(svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
new functions to derive the unspec numbers.
(svmla_svmls_lane_impl): Replace with...
(svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
integer operations too.
(svwhile_impl): Rename to...
(svwhilelx_impl): ...this and inherit from while_comparison.
(svasrd): Use unspec_based_function.
(svmla_lane): Use svmla_lane_impl.
(svmls_lane): Use svmls_lane_impl.
(svrecpe, svrsqrte): Handle unsigned integer operations too.
(svwhilele, svwhilelt): Use svwhilelx_impl.
* config/aarch64/aarch64-sve-builtins-sve2.h: New file.
* config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
* config/aarch64/aarch64-sve-builtins.def: Include
aarch64-sve-builtins-sve2.def.
gcc/testsuite/
* g++.target/aarch64/sve/acle/general-c++/mul_lane_1.c: New test.
* g++.target/aarch64/sve2/acle: New directory.
* gcc.target/aarch64/pragma_cpp_predefs_3.c: New test.
* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_TYPE_CHANGE_Z)
(TEST_DUAL_ZD, TEST_TYPE_CHANGE_ZX, TEST_TBL2, TEST_TBL2_REV): New
macros.
* gcc.target/aarch64/sve/acle/general-c/binary_lane_1.c: Do not
expect an error saying that the function has no f32 form, but instead
expect an error about SVE2 being required if the current target
doesn't support SVE2.
* gcc.target/aarch64/sve/acle/general-c/ternary_lane_1.c: Likewise.
* gcc.target/aarch64/sve/acle/general-c/ternary_lane_rotate_1.c Likewise.
* gcc.target/aarch64/sve/acle/general-c/binary_long_lane_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_long_opt_n_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_narrowb_opt_n_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_narrowt_opt_n_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_wide_1.c,
* gcc.target/aarch64/sve/acle/general-c/binary_wide_opt_n_1.c,
* gcc.target/aarch64/sve/acle/general-c/compare_1.c,
* gcc.target/aarch64/sve/acle/general-c/compare_ptr_1.c,
* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_index_restricted_1.c,
* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_1.c,
* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_2.c,
* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_3.c,
* gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_4.c,
* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_1.c,
* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_2.c,
* gcc.target/aarch64/sve/acle/general-c/mul_lane_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_long_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_2.c,
* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_1.c,
* gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/store_scatter_index_restricted_1.c,
* gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_restricted_1.c,
* gcc.target/aarch64/sve/acle/general-c/tbl_tuple_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_long_lane_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_long_opt_n_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_qq_lane_rotate_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_qq_rotate_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_shift_right_imm_1.c,
* gcc.target/aarch64/sve/acle/general-c/ternary_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_convert_narrowt_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_narrowb_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_narrowb_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_narrowt_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_narrowt_to_uint_1.c,
* gcc.target/aarch64/sve/acle/general-c/unary_to_int_1.c: New tests.
* gcc.target/aarch64/sve2/bcax_1.c: Likewise.
* gcc.target/aarch64/sve2/acle: New directory.
From-SVN: r280060
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|
gcc/
PR target/92055
* config.gcc (tm_defines) [target=avr]: Support --with-libf7,
--with-double-comparison.
* doc/install.texi: Document them.
* config/avr/avr-c.c (avr_cpu_cpp_builtins)
<WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
<WITH_DOUBLE_COMPARISON>: New built-in defines.
* doc/invoke.texi (AVR Built-in Macros): Document them.
* config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
* config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
* config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
libgcc/
PR target/92055
* config.host (tmake_file) [target=avr]: Add t-libf7,
t-libf7-math, t-libf7-math-symbols as specified by --with-libf7=.
* config/avr/t-avrlibc: Don't copy libgcc.a if there are modules
depending on sizeof (double) or sizeof (long double).
* config/avr/libf7: New folder.
libgcc/config/avr/libf7/
PR target/92055
* t-libf7: New file.
* t-libf7-math: New file.
* t-libf7-math-symbols: New file.
* libf7-common.mk: New file.
* libf7-asm-object.mk: New file.
* libf7-c-object.mk: New file.
* asm-defs.h: New file.
* libf7.h: New file.
* libf7.c: New file.
* libf7-asm.sx: New file.
* libf7-array.def: New file.
* libf7-const.def: New file.
* libf7-constdef.h: New file.
* f7renames.sh: New script.
* f7wraps.sh: New script.
* f7-renames.h: New generated file.
* f7-wraps.h: New generated file.
From-SVN: r279994
|
|
From-SVN: r279813
|
|
On Vxworks 7, includers of stdint.h (which we currently "provide")
need yvals.h to have been included ahead.
Instead of altering the common stdint-gcc.h with unpleasant
vxworks specific bits to do that, we arrange to provide stdint-gcc.h
on its own along with a stdint.h wrapper which preincludes yvals.h
on vx7 then includes stdint-gcc.h.
2019-12-30 Olivier Hainque <hainque@adacore.com>
* config/vxworks/stdint.h: New file. Include _yvals.h
then stdint-gcc.h.
* config/t-vxworks: Arrange to install the stdint.h wrapper.
* config.gcc (*-*-vxworks*): Add stdint-gcc.h to $extra_headers
so it gets copied. Set use_gcc_stdint to request _not_ crafting
stdint.h through the common Makefile rules.
From-SVN: r279791
|
|
Starting from VxWorks 7, the system comes with a Dinkumware
environment which requires the inclusion of "yvals.h" before other
system headers. We provide wrapped versions of a few headers to
accommodate such constraints.
2019-12-30 Jerome Lambourg <lambourg@adaccore.com>
Olivier Hainque <hainque@adacore.com>
gcc/
* config/vxworks/_yvals.h: New file.
* config/vxworks/_yvals-wrapper.h: New file.
* gcc/config/vxworks/math.h: Use it to wrap the VxWorks
math.h header.
* gcc/config/vxworks/complex.h: Likewise.
* gcc/config/vxworks/setjmp.h: Likewise.
* gcc/config/vxworks/inttypes.h: Likewise.
* config.gcc (*-*-vxworks*): Add system header wrappers
to extra_headers.
(powerpc-*-vxworks*): Reuse the common extra_headers.
From-SVN: r279784
|
|
This changes introduces an internal API for VxWorks version checks
within runtime files, a prerequisite to a few fixes coming up for libstdc++
builds on more recent versions of the OS.
2019-12-30 Olivier Hainque <hainque@adacore.com>
gcc/
* config/vxworks/_vxworks-versions.h: New file.
* config.gcc (*-*-vxworks*): Add it to extra_headers.
libgcc/
* config/gthr-vxworks.h: Use _vxworks-versions.h.
* config/gthr-vxworks-tls.c: Likewise.
From-SVN: r279783
|
|
This patch modifies the C & C++ VxWorks compiler to predefine
the __STDC_ macros verified by gcc.dg/c99-predef-1.c in the testsuite.
2019-12-13 Joel Brobecker <brobecker@adacore.com>
* config.gcc <*-*-vxworks*>: Add vxworks-c.o to c_target_objs
and cxx_target_objs. Set target_has_targetcm to "yes". Add
vxworks-predef.h to extra_headers.
* config/t-vxworks (vxworks-c.o): New target.
* config/vxworks-c.c: New file.
* config/vxworks/vxworks-predef.h: New file.
From-SVN: r279781
|
|
contrib/ChangeLog:
2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config-list.mk: Add msp430-elfbare.
gcc/ChangeLog:
2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config.gcc: s/msp430*-*-*/msp430-*-*.
Handle msp430-*-elfbare.
* config/msp430/msp430-devices.c (TARGET_SUBDIR): Define.
(_MSPMKSTR): Define.
(__MSPMKSTR): Define.
(rest_of_devices_path): Use TARGET_SUBDIR value in string.
* config/msp430/msp430.c (msp430_option_override): Error if
-fuse-cxa-atexit is used when it has been disabled at configure time.
* config/msp430/t-msp430: Define TARGET_SUBDIR when building
msp430-devices.o.
* doc/install.texi: Document msp430-*-elf and msp430-*-elfbare.
* doc/invoke.texi: Update documentation about which path devices.csv is
searched for.
gcc/testsuite/ChangeLog:
2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* g++.dg/init/dso_handle1.C: Require cxa_atexit support.
* g++.dg/init/dso_handle2.C: Likewise.
* g++.dg/other/cxa-atexit1.C: Likewise.
* gcc.target/msp430/msp430.exp: Update csv-using-installed.c test to
handle msp430-elfbare configuration.
libgcc/ChangeLog:
2019-12-16 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config.host: s/msp430*-*-elf/msp430-*-elf*.
Override default "extra_parts" variable.
* configure: Regenerate.
* configure.ac: Disable TM clone registry by default for
msp430-elfbare.
From-SVN: r279442
|
|
2019-11-13 Jerome Lambourg <lambourg@adacore.com>
Doug Rupp <rupp@adacore.com>
Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc: Collapse the arm-vxworks entries into
a single arm-wrs-vxworks7* one, bpabi based. Update
the default cpu from arm8 to armv7-a
* config/arm/vxworks.h (CC1_SPEC): Simplify, knowing that
we always use ARM_UNWIND_INFO.
(DWARF2_UNWIND_INFO): Remove redefinition.
(ARM_TARGET2_DWARF_FORMAT): Likewise.
(VXWORKS_PERSONALITY): Define, to "llvm".
(VXWORKS_EXTRA_LIBS_RTP): Define, to "-lllvm".
libgcc/
* config.host: Collapse the arm-vxworks entries into
a single arm-wrs-vxworks7* one.
* config/arm/unwind-arm-vxworks.c: Update comments. Provide
__gnu_Unwind_Find_exidx and a weak dummy __cxa_type_match for
kernel modules, to be overriden by libstdc++ when we link with
it. Rely on externally provided __exidx_start/end.
Co-Authored-By: Doug Rupp <rupp@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>
From-SVN: r278253
|
|
2019-11-14 Doug Rupp <rupp@adacore.com>
Olivier Hainque <hainque@adacore.com>
Jerome Lambourg <lambourg@adacore.com>
gcc/
* config.gcc: Handle aarch64*-wrs-vxworks7*.
* config/aarch64/aarch64-vxworks.h: New file.
* config/aarch64/t-aarch64-vxworks: New file.
libgcc/
* config.host: Handle aarch64*-wrs-vxworks7*.
Co-Authored-By: Jerome Lambourg <lambourg@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>
From-SVN: r278251
|
|
2019-11-06 Pat Bernardi <bernardi@adacore.com>
Jerome Lambourg <lambourg@adacore.com>
Olivier Hainque <hainque@adacore.com>
gcc/
* config.gcc: Add comment to introduce the TARGET_VXWORKS
commong macro definitions, conveying VXWORKS7 or 64bit general
variations. Add a block to set gcc_cv_initfini_array
unconditionally to "yes" for VxWorks7.
config/vx-common.h (VXWORKS_CC1_SPEC): New macro, empty string
by default. Update some comments.
config/vxworks.h (VXWORKS_EXTRA_LIBS_RTP): New macro, empty by
default, to be added the end of VXWORKS_LIBS_RTP.
(VXWORKS_LIBS_RTP): Replace hardcoded part by VXWORKS_BASE_LIBS_RTP
and append VXWORKS_EXTRA_LIBS_RTP, both of which specific ports may
redefine.
(VXWORKS_NET_LIBS_RTP): Account for VxWorks7 specificities.
(VXWORKS_CC1_SPEC): Common base definition, with VxWorks7 variation
to account for the now available TLS abilities.
(TARGET_LIBC_HAS_FUNCTION): Account for VxWorks7 abilities.
(VXWORKS_HAVE_TLS): Likewise.
Co-Authored-By: Jerome Lambourg <lambourg@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>
From-SVN: r278247
|
|
gcc/
Support 64-bit double and 64-bit long double configurations.
PR target/92055
* config.gcc (tm_defines) [avr]: Set from --with-double=,
--with-long-double=.
* config/avr/t-multilib: Remove.
* config/avr/t-avr: Output of genmultilib.awk is now fully
dynamically generated and no more part of the repo.
(HAVE_DOUBLE_MULTILIB, HAVE_LONG_DOUBLE_MULTILIB): New variables.
Pass them down to...
* config/avr/genmultilib.awk: ...here and handle them.
* gcc/config/avr/avr.opt (-mdouble=, avr_double). New option and var.
(-mlong-double=, avr_long_double). New option and var.
* common/config/avr/avr-common.c (opts.h, diagnostic.h): Include.
(TARGET_OPTION_OPTIMIZATION_TABLE) <-mdouble=, -mlong-double=>:
Set default as requested by --with-double=
(TARGET_HANDLE_OPTION): Define to this...
(avr_handle_option): ...new hook worker.
* config/avr/avr.h (DOUBLE_TYPE_SIZE): Define to avr_double.
(LONG_DOUBLE_TYPE_SIZE): Define to avr_long_double.
(avr_double_lib): New proto for spec function.
(EXTRA_SPEC_FUNCTIONS) <double-lib>: Add.
(DRIVER_SELF_SPECS): Call %:double-lib.
* config/avr/avr.c (avr_option_override): Assert
sizeof(long double) >= sizeof(double) for the target.
* config/avr/avr-c.c (avr_cpu_cpp_builtins)
[__HAVE_DOUBLE_MULTILIB__, __HAVE_LONG_DOUBLE_MULTILIB__]
[__HAVE_DOUBLE64__, __HAVE_DOUBLE32__, __DEFAULT_DOUBLE__=]
[__HAVE_LONG_DOUBLE64__, __HAVE_LONG_DOUBLE32__]
[__HAVE_LONG_DOUBLE_IS_DOUBLE__, __DEFAULT_LONG_DOUBLE__=]:
New built-in define depending on --with-double=, --with-long-double=.
* config/avr/driver-avr.c (avr_double_lib): New spec function.
* doc/invoke.tex (AVR Options) <-mdouble=,-mlong-double=>: Doc.
* doc/install.texi (Cross-Compiler-Specific Options)
<--with-double=, --with-long-double=>: Doc.
libgcc/
Support 64-bit double and 64-bit long double configurations.
PR target/92055
* config/avr/t-avr (HOST_LIBGCC2_CFLAGS): Only add -DF=SF if
long double is a 32-bit type.
* config/avr/t-avrlibc: Copy double64 and long-double64
multilib(s) from the vanilla one.
* config/avr/t-copy-libgcc: New Makefile snip.
From-SVN: r277908
|
|
This patch adds support for arm_sve.h. I've tried to split all the
groundwork out into separate patches, so this is mostly adding new code
rather than changing existing code.
The C++ frontend seems to handle correct ACLE code without modification,
even in length-agnostic mode. The C frontend is close; the only correct
construct I know it doesn't handle is initialisation. E.g.:
svbool_t pg = svptrue_b8 ();
produces:
variable-sized object may not be initialized
although:
svbool_t pg; pg = svptrue_b8 ();
works fine. This can be fixed by changing:
{
/* A complete type is ok if size is fixed. */
- if (TREE_CODE (TYPE_SIZE (TREE_TYPE (decl))) != INTEGER_CST
+ if (!poly_int_tree_p (TYPE_SIZE (TREE_TYPE (decl)))
|| C_DECL_VARIABLE_SIZE (decl))
{
error ("variable-sized object may not be initialized");
in c/c-decl.c:start_decl.
Invalid code is likely to trigger ICEs, so this isn't ready for general
use yet. However, it seemed better to apply the patch now and deal with
diagnosing invalid code as a follow-up. For one thing, it means that
we'll be able to provide testcases for middle-end changes related
to SVE vectors, which has been a problem until now. (I already have
a series of such patches lined up.)
The patch includes some tests, but the main ones need to wait until the
PCS support has been applied.
2019-10-29 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
gcc/
* config.gcc (aarch64*-*-*): Add arm_sve.h to extra_headers.
Add aarch64-sve-builtins.o, aarch64-sve-builtins-shapes.o and
aarch64-sve-builtins-base.o to extra_objs. Add
aarch64-sve-builtins.h and aarch64-sve-builtins.cc to target_gtfiles.
* config/aarch64/t-aarch64 (aarch64-sve-builtins.o): New rule.
(aarch64-sve-builtins-shapes.o): Likewise.
(aarch64-sve-builtins-base.o): New rules.
* config/aarch64/aarch64-c.c (aarch64_pragma_aarch64): New function.
(aarch64_resolve_overloaded_builtin): Likewise.
(aarch64_check_builtin_call): Likewise.
(aarch64_register_pragmas): Install aarch64_resolve_overloaded_builtin
and aarch64_check_builtin_call in targetm. Register the GCC aarch64
pragma.
* config/aarch64/aarch64-protos.h (AARCH64_FOR_SVPRFOP): New macro.
(aarch64_svprfop): New enum.
(AARCH64_BUILTIN_SVE): New aarch64_builtin_class enum value.
(aarch64_sve_int_mode, aarch64_sve_data_mode): Declare.
(aarch64_fold_sve_cnt_pat, aarch64_output_sve_prefetch): Likewise.
(aarch64_output_sve_cnt_pat_immediate): Likewise.
(aarch64_output_sve_ptrues, aarch64_sve_ptrue_svpattern_p): Likewise.
(aarch64_sve_sqadd_sqsub_immediate_p, aarch64_sve_ldff1_operand_p)
(aarch64_sve_ldnf1_operand_p, aarch64_sve_prefetch_operand_p)
(aarch64_ptrue_all_mode, aarch64_convert_sve_data_to_pred): Likewise.
(aarch64_expand_sve_dupq, aarch64_replace_reg_mode): Likewise.
(aarch64_sve::init_builtins, aarch64_sve::handle_arm_sve_h): Likewise.
(aarch64_sve::builtin_decl, aarch64_sve::builtin_type_p): Likewise.
(aarch64_sve::mangle_builtin_type): Likewise.
(aarch64_sve::resolve_overloaded_builtin): Likewise.
(aarch64_sve::check_builtin_call, aarch64_sve::gimple_fold_builtin)
(aarch64_sve::expand_builtin): Likewise.
* config/aarch64/aarch64.c (aarch64_sve_data_mode): Make public.
(aarch64_sve_int_mode): Likewise.
(aarch64_ptrue_all_mode): New function.
(aarch64_convert_sve_data_to_pred): Make public.
(svprfop_token): New function.
(aarch64_output_sve_prefetch): Likewise.
(aarch64_fold_sve_cnt_pat): Likewise.
(aarch64_output_sve_cnt_pat_immediate): Likewise.
(aarch64_sve_move_pred_via_while): Use gen_while with UNSPEC_WHILE_LO
instead of gen_while_ult.
(aarch64_replace_reg_mode): Make public.
(aarch64_init_builtins): Call aarch64_sve::init_builtins.
(aarch64_fold_builtin): Handle AARCH64_BUILTIN_SVE.
(aarch64_gimple_fold_builtin, aarch64_expand_builtin): Likewise.
(aarch64_builtin_decl, aarch64_builtin_reciprocal): Likewise.
(aarch64_mangle_type): Call aarch64_sve::mangle_type.
(aarch64_sve_sqadd_sqsub_immediate_p): New function.
(aarch64_sve_ptrue_svpattern_p): Likewise.
(aarch64_sve_pred_valid_immediate): Check
aarch64_sve_ptrue_svpattern_p.
(aarch64_sve_ldff1_operand_p, aarch64_sve_ldnf1_operand_p)
(aarch64_sve_prefetch_operand_p, aarch64_output_sve_ptrues): New
functions.
* config/aarch64/aarch64.md (UNSPEC_LDNT1_SVE, UNSPEC_STNT1_SVE)
(UNSPEC_LDFF1_GATHER, UNSPEC_PTRUE, UNSPEC_WHILE_LE, UNSPEC_WHILE_LS)
(UNSPEC_WHILE_LT, UNSPEC_CLASTA, UNSPEC_UPDATE_FFR)
(UNSPEC_UPDATE_FFRT, UNSPEC_RDFFR, UNSPEC_WRFFR)
(UNSPEC_SVE_LANE_SELECT, UNSPEC_SVE_CNT_PAT, UNSPEC_SVE_PREFETCH)
(UNSPEC_SVE_PREFETCH_GATHER, UNSPEC_SVE_COMPACT, UNSPEC_SVE_SPLICE):
New unspecs.
* config/aarch64/iterators.md (SI_ONLY, DI_ONLY, VNx8HI_ONLY)
(VNx2DI_ONLY, SVE_PARTIAL, VNx8_NARROW, VNx8_WIDE, VNx4_NARROW)
(VNx4_WIDE, VNx2_NARROW, VNx2_WIDE, PRED_HSD): New mode iterators.
(UNSPEC_ADR, UNSPEC_BRKA, UNSPEC_BRKB, UNSPEC_BRKN, UNSPEC_BRKPA)
(UNSPEC_BRKPB, UNSPEC_PFIRST, UNSPEC_PNEXT, UNSPEC_CNTP, UNSPEC_SADDV)
(UNSPEC_UADDV, UNSPEC_FMLA, UNSPEC_FMLS, UNSPEC_FEXPA, UNSPEC_FTMAD)
(UNSPEC_FTSMUL, UNSPEC_FTSSEL, UNSPEC_COND_CMPEQ_WIDE): New unspecs.
(UNSPEC_COND_CMPGE_WIDE, UNSPEC_COND_CMPGT_WIDE): Likewise.
(UNSPEC_COND_CMPHI_WIDE, UNSPEC_COND_CMPHS_WIDE): Likewise.
(UNSPEC_COND_CMPLE_WIDE, UNSPEC_COND_CMPLO_WIDE): Likewise.
(UNSPEC_COND_CMPLS_WIDE, UNSPEC_COND_CMPLT_WIDE): Likewise.
(UNSPEC_COND_CMPNE_WIDE, UNSPEC_COND_FCADD90, UNSPEC_COND_FCADD270)
(UNSPEC_COND_FCMLA, UNSPEC_COND_FCMLA90, UNSPEC_COND_FCMLA180)
(UNSPEC_COND_FCMLA270, UNSPEC_COND_FMAX, UNSPEC_COND_FMIN): Likewise.
(UNSPEC_COND_FMULX, UNSPEC_COND_FRECPX, UNSPEC_COND_FSCALE): Likewise.
(UNSPEC_LASTA, UNSPEC_ASHIFT_WIDE, UNSPEC_ASHIFTRT_WIDE): Likewise.
(UNSPEC_LSHIFTRT_WIDE, UNSPEC_LDFF1, UNSPEC_LDNF1): Likewise.
(Vesize): Handle partial vector modes.
(self_mask, narrower_mask, sve_lane_con, sve_lane_pair_con): New
mode attributes.
(UBINQOPS, ANY_PLUS, SAT_PLUS, ANY_MINUS, SAT_MINUS): New code
iterators.
(s, paired_extend, inc_dec): New code attributes.
(SVE_INT_ADDV, CLAST, LAST): New int iterators.
(SVE_INT_UNARY): Add UNSPEC_RBIT.
(SVE_FP_UNARY, SVE_FP_UNARY_INT): New int iterators.
(SVE_FP_BINARY, SVE_FP_BINARY_INT): Likewise.
(SVE_COND_FP_UNARY): Add UNSPEC_COND_FRECPX.
(SVE_COND_FP_BINARY): Add UNSPEC_COND_FMAX, UNSPEC_COND_FMIN and
UNSPEC_COND_FMULX.
(SVE_COND_FP_BINARY_INT, SVE_COND_FP_ADD): New int iterators.
(SVE_COND_FP_SUB, SVE_COND_FP_MUL): Likewise.
(SVE_COND_FP_BINARY_I1): Add UNSPEC_COND_FMAX and UNSPEC_COND_FMIN.
(SVE_COND_FP_BINARY_REG): Add UNSPEC_COND_FMULX.
(SVE_COND_FCADD, SVE_COND_FP_MAXMIN, SVE_COND_FCMLA)
(SVE_COND_INT_CMP_WIDE, SVE_FP_TERNARY_LANE, SVE_CFP_TERNARY_LANE)
(SVE_WHILE, SVE_SHIFT_WIDE, SVE_LDFF1_LDNF1, SVE_BRK_UNARY)
(SVE_BRK_BINARY, SVE_PITER): New int iterators.
(optab): Handle UNSPEC_SADDV, UNSPEC_UADDV, UNSPEC_FRECPE,
UNSPEC_FRECPS, UNSPEC_RSQRTE, UNSPEC_RSQRTS, UNSPEC_RBIT,
UNSPEC_SMUL_HIGHPART, UNSPEC_UMUL_HIGHPART, UNSPEC_FMLA, UNSPEC_FMLS,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270,
UNSPEC_FEXPA, UNSPEC_FTSMUL, UNSPEC_FTSSEL, UNSPEC_COND_FCADD90,
UNSPEC_COND_FCADD270, UNSPEC_COND_FCMLA, UNSPEC_COND_FCMLA90,
UNSPEC_COND_FCMLA180, UNSPEC_COND_FCMLA270, UNSPEC_COND_FMAX,
UNSPEC_COND_FMIN, UNSPEC_COND_FMULX, UNSPEC_COND_FRECPX and
UNSPEC_COND_FSCALE.
(maxmin_uns): Handle UNSPEC_COND_FMAX and UNSPEC_COND_FMIN.
(binqops_op, binqops_op_rev, last_op): New int attributes.
(su): Handle UNSPEC_SADDV and UNSPEC_UADDV.
(fn, ab): New int attributes.
(cmp_op): Handle UNSPEC_COND_CMP*_WIDE and UNSPEC_WHILE_*.
(while_optab_cmp, brk_op, sve_pred_op): New int attributes.
(sve_int_op): Handle UNSPEC_SMUL_HIGHPART, UNSPEC_UMUL_HIGHPART,
UNSPEC_ASHIFT_WIDE, UNSPEC_ASHIFTRT_WIDE, UNSPEC_LSHIFTRT_WIDE and
UNSPEC_RBIT.
(sve_fp_op): Handle UNSPEC_FRECPE, UNSPEC_FRECPS, UNSPEC_RSQRTE,
UNSPEC_RSQRTS, UNSPEC_FMLA, UNSPEC_FMLS, UNSPEC_FEXPA, UNSPEC_FTSMUL,
UNSPEC_FTSSEL, UNSPEC_COND_FMAX, UNSPEC_COND_FMIN, UNSPEC_COND_FMULX,
UNSPEC_COND_FRECPX and UNSPEC_COND_FSCALE.
(sve_fp_op_rev): Handle UNSPEC_COND_FMAX, UNSPEC_COND_FMIN and
UNSPEC_COND_FMULX.
(rot): Handle UNSPEC_COND_FCADD* and UNSPEC_COND_FCMLA*.
(brk_reg_con, brk_reg_opno): New int attributes.
(sve_pred_fp_rhs1_operand, sve_pred_fp_rhs2_operand): Handle
UNSPEC_COND_FMAX, UNSPEC_COND_FMIN and UNSPEC_COND_FMULX.
(sve_pred_fp_rhs2_immediate): Handle UNSPEC_COND_FMAX and
UNSPEC_COND_FMIN.
(max_elem_bits): New int attribute.
(min_elem_bits): Handle UNSPEC_RBIT.
* config/aarch64/predicates.md (subreg_lowpart_operator): Handle
TRUNCATE as well as SUBREG.
(ascending_int_parallel, aarch64_simd_reg_or_minus_one)
(aarch64_sve_ldff1_operand, aarch64_sve_ldnf1_operand)
(aarch64_sve_prefetch_operand, aarch64_sve_ptrue_svpattern_immediate)
(aarch64_sve_qadd_immediate, aarch64_sve_qsub_immediate)
(aarch64_sve_gather_immediate_b, aarch64_sve_gather_immediate_h)
(aarch64_sve_gather_immediate_w, aarch64_sve_gather_immediate_d)
(aarch64_sve_sqadd_operand, aarch64_sve_gather_offset_b)
(aarch64_sve_gather_offset_h, aarch64_sve_gather_offset_w)
(aarch64_sve_gather_offset_d, aarch64_gather_scale_operand_b)
(aarch64_gather_scale_operand_h): New predicates.
* config/aarch64/constraints.md (UPb, UPd, UPh, UPw, Utf, Utn, vgb)
(vgd, vgh, vgw, vsQ, vsS): New constraints.
* config/aarch64/aarch64-sve.md: Add a note on the FFR handling.
(*aarch64_sve_reinterpret<mode>): Allow any source register
instead of requiring an exact match.
(*aarch64_sve_ptruevnx16bi_cc, *aarch64_sve_ptrue<mode>_cc)
(*aarch64_sve_ptruevnx16bi_ptest, *aarch64_sve_ptrue<mode>_ptest)
(aarch64_wrffr, aarch64_update_ffr_for_load, aarch64_copy_ffr_to_ffrt)
(aarch64_rdffr, aarch64_rdffr_z, *aarch64_rdffr_z_ptest)
(*aarch64_rdffr_ptest, *aarch64_rdffr_z_cc, *aarch64_rdffr_cc)
(aarch64_update_ffrt): New patterns.
(@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>)
(@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>)
(@aarch64_ld<fn>f1<mode>): New patterns.
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>)
(@aarch64_ldnt1<mode>): New patterns.
(gather_load<mode>): Use aarch64_sve_gather_offset_<Vesize> for
the scalar part of the address.
(mask_gather_load<SVE_S:mode>): Use aarch64_sve_gather_offset_w for the
scalar part of the addresse and add an alternative for handling
nonzero offsets.
(mask_gather_load<SVE_D:mode>): Likewise aarch64_sve_gather_offset_d.
(*mask_gather_load<mode>_sxtw, *mask_gather_load<mode>_uxtw)
(@aarch64_gather_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_gather_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>)
(*aarch64_gather_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_sxtw)
(*aarch64_gather_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_uxtw)
(@aarch64_ldff1_gather<SVE_S:mode>, @aarch64_ldff1_gather<SVE_D:mode>)
(*aarch64_ldff1_gather<mode>_sxtw, *aarch64_ldff1_gather<mode>_uxtw)
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>)
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_sxtw)
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_uxtw)
(@aarch64_sve_prefetch<mode>): New patterns.
(@aarch64_sve_gather_prefetch<SVE_I:mode><VNx4SI_ONLY:mode>)
(@aarch64_sve_gather_prefetch<SVE_I:mode><VNx2DI_ONLY:mode>)
(*aarch64_sve_gather_prefetch<SVE_I:mode><VNx2DI_ONLY:mode>_sxtw)
(*aarch64_sve_gather_prefetch<SVE_I:mode><VNx2DI_ONLY:mode>_uxtw)
(@aarch64_store_trunc<VNx8_NARROW:mode><VNx8_WIDE:mode>)
(@aarch64_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
(@aarch64_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
(@aarch64_stnt1<mode>): New patterns.
(scatter_store<mode>): Use aarch64_sve_gather_offset_<Vesize> for
the scalar part of the address.
(mask_scatter_store<SVE_S:mode>): Use aarch64_sve_gather_offset_w for
the scalar part of the addresse and add an alternative for handling
nonzero offsets.
(mask_scatter_store<SVE_D:mode>): Likewise aarch64_sve_gather_offset_d.
(*mask_scatter_store<mode>_sxtw, *mask_scatter_store<mode>_uxtw)
(@aarch64_scatter_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
(@aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
(*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_sxtw)
(*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_uxtw):
New patterns.
(vec_duplicate<mode>): Use QI as the mode of the input operand.
(extract_last_<mode>): Generalize to...
(@extract_<LAST:last_op>_<mode>): ...this.
(*<SVE_INT_UNARY:optab><mode>2): Rename to...
(@aarch64_pred_<SVE_INT_UNARY:optab><mode>): ...this.
(@cond_<SVE_INT_UNARY:optab><mode>): New expander.
(@aarch64_pred_sxt<SVE_HSDI:mode><SVE_PARTIAL:mode>): New pattern.
(@aarch64_cond_sxt<SVE_HSDI:mode><SVE_PARTIAL:mode>): Likewise.
(@aarch64_pred_cnot<mode>, @cond_cnot<mode>): New expanders.
(@aarch64_sve_<SVE_FP_UNARY_INT:optab><mode>): New pattern.
(@aarch64_sve_<SVE_FP_UNARY:optab><mode>): Likewise.
(*<SVE_COND_FP_UNARY:optab><mode>2): Rename to...
(@aarch64_pred_<SVE_COND_FP_UNARY:optab><mode>): ...this.
(@cond_<SVE_COND_FP_UNARY:optab><mode>): New expander.
(*<SVE_INT_BINARY_IMM:optab><mode>3): Rename to...
(@aarch64_pred_<SVE_INT_BINARY_IMM:optab><mode>): ...this.
(@aarch64_adr<mode>, *aarch64_adr_sxtw): New patterns.
(*aarch64_adr_uxtw_unspec): Likewise.
(*aarch64_adr_uxtw): Rename to...
(*aarch64_adr_uxtw_and): ...this.
(@aarch64_adr<mode>_shift): New expander.
(*aarch64_adr_shift_sxtw): New pattern.
(aarch64_<su>abd<mode>_3): Rename to...
(@aarch64_pred_<su>abd<mode>): ...this.
(<su>abd<mode>_3): Update accordingly.
(@aarch64_cond_<su>abd<mode>): New expander.
(@aarch64_<SBINQOPS:su_optab><optab><mode>): New pattern.
(@aarch64_<UBINQOPS:su_optab><optab><mode>): Likewise.
(*<su>mul<mode>3_highpart): Rename to...
(@aarch64_pred_<optab><mode>): ...this.
(@cond_<MUL_HIGHPART:optab><mode>): New expander.
(*cond_<MUL_HIGHPART:optab><mode>_2): New pattern.
(*cond_<MUL_HIGHPART:optab><mode>_z): Likewise.
(*<SVE_INT_BINARY_SD:optab><mode>3): Rename to...
(@aarch64_pred_<SVE_INT_BINARY_SD:optab><mode>): ...this.
(cond_<SVE_INT_BINARY_SD:optab><mode>): Add a "@" marker.
(@aarch64_bic<mode>, @cond_bic<mode>): New expanders.
(*v<ASHIFT:optab><mode>3): Rename to...
(@aarch64_pred_<ASHIFT:optab><mode>): ...this.
(@aarch64_sve_<SVE_SHIFT_WIDE:sve_int_op><mode>): New pattern.
(@cond_<SVE_SHIFT_WIDE:sve_int_op><mode>): New expander.
(*cond_<SVE_SHIFT_WIDE:sve_int_op><mode>_m): New pattern.
(*cond_<SVE_SHIFT_WIDE:sve_int_op><mode>_z): Likewise.
(@cond_asrd<mode>): New expander.
(*cond_asrd<mode>_2, *cond_asrd<mode>_z): New patterns.
(sdiv_pow2<mode>3): Expand to *cond_asrd<mode>_2.
(*sdiv_pow2<mode>3): Delete.
(@cond_<SVE_COND_FP_BINARY_INT:optab><mode>): New expander.
(*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_2): New pattern.
(*cond_<SVE_COND_FP_BINARY_INT:optab><mode>_any): Likewise.
(@aarch64_sve_<SVE_FP_BINARY:optab><mode>): New pattern.
(@aarch64_sve_<SVE_FP_BINARY_INT:optab><mode>): Likewise.
(*<SVE_COND_FP_BINARY_REG:optab><mode>3): Rename to...
(@aarch64_pred_<SVE_COND_FP_BINARY_REG:optab><mode>): ...this.
(@aarch64_pred_<SVE_COND_FP_BINARY_INT:optab><mode>): New pattern.
(cond_<SVE_COND_FP_BINARY:optab><mode>): Add a "@" marker.
(*add<SVE_F:mode>3): Rename to...
(@aarch64_pred_add<SVE_F:mode>): ...this and add alternatives
for SVE_STRICT_GP.
(@aarch64_pred_<SVE_COND_FCADD:optab><mode>): New pattern.
(@cond_<SVE_COND_FCADD:optab><mode>): New expander.
(*cond_<SVE_COND_FCADD:optab><mode>_2): New pattern.
(*cond_<SVE_COND_FCADD:optab><mode>_any): Likewise.
(*sub<SVE_F:mode>3): Rename to...
(@aarch64_pred_sub<SVE_F:mode>): ...this and add alternatives
for SVE_STRICT_GP.
(@aarch64_pred_abd<SVE_F:mode>): New expander.
(*fabd<SVE_F:mode>3): Rename to...
(*aarch64_pred_abd<SVE_F:mode>): ...this.
(@aarch64_cond_abd<SVE_F:mode>): New expander.
(*mul<SVE_F:mode>3): Rename to...
(@aarch64_pred_<SVE_F:optab><mode>): ...this and add alternatives
for SVE_STRICT_GP.
(@aarch64_mul_lane_<SVE_F:mode>): New pattern.
(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><mode>3): Rename and generalize
to...
(@aarch64_pred_<SVE_COND_FP_MAXMIN:optab><mode>): ...this.
(*<LOGICAL:optab><PRED_ALL:mode>3_ptest): New pattern.
(*<nlogical><PRED_ALL:mode>3): Rename to...
(aarch64_pred_<nlogical><PRED_ALL:mode>_z): ...this.
(*<nlogical><PRED_ALL:mode>3_cc): New pattern.
(*<nlogical><PRED_ALL:mode>3_ptest): Likewise.
(*<logical_nn><PRED_ALL:mode>3): Rename to...
(aarch64_pred_<logical_nn><mode>_z): ...this.
(*<logical_nn><PRED_ALL:mode>3_cc): New pattern.
(*<logical_nn><PRED_ALL:mode>3_ptest): Likewise.
(*fma<SVE_I:mode>4): Rename to...
(@aarch64_pred_fma<SVE_I:mode>): ...this.
(*fnma<SVE_I:mode>4): Rename to...
(@aarch64_pred_fnma<SVE_I:mode>): ...this.
(@aarch64_<sur>dot_prod_lane<vsi2qi>): New pattern.
(*<SVE_FP_TERNARY:optab><mode>4): Rename to...
(@aarch64_pred_<SVE_FP_TERNARY:optab><mode>): ...this.
(cond_<SVE_FP_TERNARY:optab><mode>): Add a "@" marker.
(@aarch64_<SVE_FP_TERNARY_LANE:optab>_lane_<mode>): New pattern.
(@aarch64_pred_<SVE_COND_FCMLA:optab><mode>): Likewise.
(@cond_<SVE_COND_FCMLA:optab><mode>): New expander.
(*cond_<SVE_COND_FCMLA:optab><mode>_4): New pattern.
(*cond_<SVE_COND_FCMLA:optab><mode>_any): Likewise.
(@aarch64_<FCMLA:optab>_lane_<mode>): Likewise.
(@aarch64_sve_tmad<mode>): Likewise.
(vcond_mask_<SVE_ALL:mode><vpred>): Add a "@" marker.
(*aarch64_sel_dup<mode>): Rename to...
(@aarch64_sel_dup<mode>): ...this.
(@aarch64_pred_cmp<cmp_op><SVE_I:mode>_wide): New pattern.
(*aarch64_pred_cmp<cmp_op><SVE_I:mode>_wide_cc): Likewise.
(*aarch64_pred_cmp<cmp_op><SVE_I:mode>_wide_ptest): Likewise.
(@while_ult<GPI:mode><PRED_ALL:mode>): Generalize to...
(@while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>): ...this.
(*while_ult<GPI:mode><PRED_ALL:mode>_cc): Generalize to.
(*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_cc): ...this.
(*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): New pattern.
(*fcm<cmp_op><mode>): Rename to...
(@aarch64_pred_fcm<cmp_op><mode>): ...this. Make operand order
match @aarch64_pred_cmp<cmp_op><SVE_I:mode>.
(*fcmuo<mode>): Rename to...
(@aarch64_pred_fcmuo<mode>): ...this. Make operand order
match @aarch64_pred_cmp<cmp_op><SVE_I:mode>.
(@aarch64_pred_fac<cmp_op><mode>): New expander.
(@vcond_mask_<PRED_ALL:mode><mode>): New pattern.
(fold_extract_last_<mode>): Generalize to...
(@fold_extract_<last_op>_<mode>): ...this.
(@aarch64_fold_extract_vector_<last_op>_<mode>): New pattern.
(*reduc_plus_scal_<SVE_I:mode>): Replace with...
(@aarch64_pred_reduc_<optab>_<mode>): ...this pattern, making the
DImode result explicit.
(reduc_plus_scal_<mode>): Update accordingly.
(*reduc_<optab>_scal_<SVE_I:mode>): Rename to...
(@aarch64_pred_reduc_<optab>_<SVE_I:mode>): ...this.
(*reduc_<optab>_scal_<SVE_F:mode>): Rename to...
(@aarch64_pred_reduc_<optab>_<SVE_F:mode>): ...this.
(*aarch64_sve_tbl<mode>): Rename to...
(@aarch64_sve_tbl<mode>): ...this.
(@aarch64_sve_compact<mode>): New pattern.
(*aarch64_sve_dup_lane<mode>): Rename to...
(@aarch64_sve_dup_lane<mode>): ...this.
(@aarch64_sve_dupq_lane<mode>): New pattern.
(@aarch64_sve_splice<mode>): Likewise.
(aarch64_sve_<perm_insn><mode>): Rename to...
(@aarch64_sve_<perm_insn><mode>): ...this.
(*aarch64_sve_ext<mode>): Rename to...
(@aarch64_sve_ext<mode>): ...this.
(aarch64_sve_<su>unpk<perm_hilo>_<SVE_BHSI:mode>): Add a "@" marker.
(*aarch64_sve_<optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>): Rename
to...
(@aarch64_sve_<optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>): ...this.
(*aarch64_sve_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
Rename to...
(@aarch64_sve_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
...this.
(@cond_<optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>): New expander.
(@cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>): Likewise.
(*cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>): New pattern.
(*aarch64_sve_<optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>): Rename
to...
(@aarch64_sve_<optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>): ...this.
(aarch64_sve_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>): Add
a "@" marker.
(@cond_<optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>): New expander.
(@cond_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>): Likewise.
(*cond_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>): New
pattern.
(*aarch64_sve_<optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>): Rename to...
(@aarch64_sve_<optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>): ...this.
(@cond_<optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>): New expander.
(*cond_<optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>): New pattern.
(aarch64_sve_<optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>): Add a
"@" marker.
(@cond_<optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>): New expander.
(*cond_<optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>): New pattern.
(aarch64_sve_punpk<perm_hilo>_<mode>): Add a "@" marker.
(@aarch64_brk<SVE_BRK_UNARY:brk_op>): New pattern.
(*aarch64_brk<SVE_BRK_UNARY:brk_op>_cc): Likewise.
(*aarch64_brk<SVE_BRK_UNARY:brk_op>_ptest): Likewise.
(@aarch64_brk<SVE_BRK_BINARY:brk_op>): Likewise.
(*aarch64_brk<SVE_BRK_BINARY:brk_op>_cc): Likewise.
(*aarch64_brk<SVE_BRK_BINARY:brk_op>_ptest): Likewise.
(@aarch64_sve_<SVE_PITER:sve_pred_op><mode>): Likewise.
(*aarch64_sve_<SVE_PITER:sve_pred_op><mode>_cc): Likewise.
(*aarch64_sve_<SVE_PITER:sve_pred_op><mode>_ptest): Likewise.
(aarch64_sve_cnt_pat): Likewise.
(@aarch64_sve_<ANY_PLUS:inc_dec><DI_ONLY:mode>_pat): Likewise.
(*aarch64_sve_incsi_pat): Likewise.
(@aarch64_sve_<SAT_PLUS:inc_dec><SI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx2DI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx4SI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx8HI_ONLY:mode>_pat): New expander.
(*aarch64_sve_<ANY_PLUS:inc_dec><VNx8HI_ONLY:mode>_pat): New pattern.
(@aarch64_sve_<ANY_MINUS:inc_dec><DI_ONLY:mode>_pat): Likewise.
(*aarch64_sve_decsi_pat): Likewise.
(@aarch64_sve_<SAT_MINUS:inc_dec><SI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx2DI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx4SI_ONLY:mode>_pat): Likewise.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx8HI_ONLY:mode>_pat): New expander.
(*aarch64_sve_<ANY_MINUS:inc_dec><VNx8HI_ONLY:mode>_pat): New pattern.
(@aarch64_pred_cntp<mode>): Likewise.
(@aarch64_sve_<ANY_PLUS:inc_dec><DI_ONLY:mode><PRED_ALL:mode>_cntp):
New expander.
(*aarch64_sve_<ANY_PLUS:inc_dec><DI_ONLY:mode><PRED_ALL:mode>_cntp)
(*aarch64_incsi<PRED_ALL:mode>_cntp): New patterns.
(@aarch64_sve_<SAT_PLUS:inc_dec><SI_ONLY:mode><PRED_ALL:mode>_cntp):
New expander.
(*aarch64_sve_<SAT_PLUS:inc_dec><SI_ONLY:mode><PRED_ALL:mode>_cntp):
New pattern.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx2DI_ONLY:mode>_cntp): New expander.
(*aarch64_sve_<ANY_PLUS:inc_dec><VNx2DI_ONLY:mode>_cntp): New pattern.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx4SI_ONLY:mode>_cntp): New expander.
(*aarch64_sve_<ANY_PLUS:inc_dec><VNx4SI_ONLY:mode>_cntp): New pattern.
(@aarch64_sve_<ANY_PLUS:inc_dec><VNx8HI_ONLY:mode>_cntp): New expander.
(*aarch64_sve_<ANY_PLUS:inc_dec><VNx8HI_ONLY:mode>_cntp): New pattern.
(@aarch64_sve_<ANY_MINUS:inc_dec><DI_ONLY:mode><PRED_ALL:mode>_cntp):
New expander.
(*aarch64_sve_<ANY_MINUS:inc_dec><DI_ONLY:mode><PRED_ALL:mode>_cntp)
(*aarch64_incsi<PRED_ALL:mode>_cntp): New patterns.
(@aarch64_sve_<SAT_MINUS:inc_dec><SI_ONLY:mode><PRED_ALL:mode>_cntp):
New expander.
(*aarch64_sve_<SAT_MINUS:inc_dec><SI_ONLY:mode><PRED_ALL:mode>_cntp):
New pattern.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx2DI_ONLY:mode>_cntp): New
expander.
(*aarch64_sve_<ANY_MINUS:inc_dec><VNx2DI_ONLY:mode>_cntp): New pattern.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx4SI_ONLY:mode>_cntp): New
expander.
(*aarch64_sve_<ANY_MINUS:inc_dec><VNx4SI_ONLY:mode>_cntp): New pattern.
(@aarch64_sve_<ANY_MINUS:inc_dec><VNx8HI_ONLY:mode>_cntp): New
expander.
(*aarch64_sve_<ANY_MINUS:inc_dec><VNx8HI_ONLY:mode>_cntp): New pattern.
* config/aarch64/arm_sve.h: New file.
* config/aarch64/aarch64-sve-builtins.h: Likewise.
* config/aarch64/aarch64-sve-builtins.cc: Likewise.
* config/aarch64/aarch64-sve-builtins.def: Likewise.
* config/aarch64/aarch64-sve-builtins-base.h: Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-base.def: Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise.
gcc/testsuite/
* g++.target/aarch64/sve/acle/aarch64-sve-acle.exp: New file.
* g++.target/aarch64/sve/acle/general-c++: New test directory.
* gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp: New file.
* gcc.target/aarch64/sve/acle/general: New test directory.
* gcc.target/aarch64/sve/acle/general-c: Likewise.
Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
From-SVN: r277563
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When using the -msave-restore flag we end up with calls to
_riscv_save_0 and _riscv_restore_0. These functions adjust the stack
and save or restore the return address. Due to grouping multiple
save/restore stub functions together the save/restore 0 calls actually
save s0, s1, s2, and the return address, but only the return address
actually matters. Leaf functions don't call the save/restore stubs,
so whenever we do see a call to the save/restore stubs, the store of
the return address is required.
If we look in gcc/config/riscv/riscv.c at the function
riscv_expand_prologue and riscv_expand_epilogue we can see that it
would be reasonably easy to adjust these functions to avoid the calls
to the save/restore stubs for those cases where we are about to call
_riscv_save_0 and _riscv_restore_0, however, the actual code size
saving this would give is debatable, with linker relaxation, the calls
to save/restore are often just 4-bytes, and can sometimes even be
2-bytes, while leaving the stack adjust and return address save inline
is always going to be 4-bytes.
The interesting case is when we call _riscv_save_0 and
_riscv_restore_0, and also have a frame that would (without
save/restore) have resulted in a tail call. In this case if we could
remove the save/restore calls, and restore the tail call then we would
get a real size saving.
The problem is that the choice of generating a tail call or not is
done during the gimple expand pass, at which point we don't know how
many registers we need to save (or restore).
The solution presented in this patch offers a partial solution to this
problem. By using the TARGET_MACHINE_DEPENDENT_REORG pass to
implement a very limited pattern matching we identify functions that
call _riscv_save_0 and _riscv_restore_0, and which could be converted
to make use of a tail call. These functions are then converted to the
non save/restore tail call form.
This should result in a code size reduction when compiling with -Os
and with the -msave-restore flag.
gcc/ChangeLog:
* config.gcc: Add riscv-sr.o to extra_objs for riscv.
* config/riscv/riscv-sr.c: New file.
* config/riscv/riscv.c (riscv_reorg): New function.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/riscv/riscv.h (SIBCALL_REG_P): Define.
(riscv_remove_unneeded_save_restore_calls): Declare.
* config/riscv/t-riscv (riscv-sr.o): New build rule.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-2.c: New file.
* gcc.target/riscv/save-restore-3.c: New file.
* gcc.target/riscv/save-restore-4.c: New file.
* gcc.target/riscv/save-restore-5.c: New file.
* gcc.target/riscv/save-restore-6.c: New file.
* gcc.target/riscv/save-restore-7.c: New file.
* gcc.target/riscv/save-restore-8.c: New file.
From-SVN: r277527
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So far z15 was identified as arch13. After the machine has been
announced we can now add the real name.
gcc/ChangeLog:
2019-10-10 Andreas Krebbel <krebbel@linux.ibm.com>
* common/config/s390/s390-common.c (PF_ARCH13): Rename to...
(PF_Z15): ... this.
* config.gcc: Add z15 as option for --with-arch and --with-tune
configure switches.
* config/s390/s390-c.c (s390_resolve_overloaded_builtin): Add
error reporting for unsupported builtins.
* config/s390/s390-opts.h (enum processor_type): Rename
PROCESSOR_8561_ARCH13 to PROCESSOR_8561_Z15.
* config/s390/8561.md: Rename arch13 to z15 throughout the file.
* config/s390/driver-native.c (s390_host_detect_local_cpu):
Likewise.
* config/s390/s390-builtins.def: Likewise.
* config/s390/s390.c (processor_table): Add z15 as option and keep arch13 as alternative.
(s390_expand_builtin): Add missing check for unsupported builtins.
(s390_canonicalize_comparison): Rename TARGET_ARCH13 to TARGET_Z15.
(s390_rtx_costs): Likewise.
(s390_get_sched_attrmask): Rename arch13 to z15.
(s390_get_unit_mask): Likewise.
(s390_is_fpd): Likewise.
(s390_is_fxd): Likewise.
* config/s390/s390.h (enum processor_flags): Likewise.
* config/s390/s390.md: Likewise.
* config/s390/vector.md: Likewise.
* config/s390/vx-builtins.md: Likewise.
* config/s390/s390.opt: Add z15 to processor_type value.
From-SVN: r276792
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From: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
Remove all -L directories from LINK_OS_EXTRA_SPEC32 and
LINK_OS_EXTRA_SPEC64 so that user directories specified at
build time have higher preference over the advance toolchain libraries.
Set MD_STARTFILE_PREFIX to $prefix/lib/ and MD_STARTFILE_PREFIX_1 to
$at/lib/ so that a compiler library has preference over the Advance
Toolchain libraries.
* config.gcc: Move -L usage from LINK_OS_EXTRA_SPEC32 and
LINK_OS_EXTRA_SPEC64 to MD_STARTFILE_PREFIX and
MD_STARTFILE_PREFIX_1 when using --with-advance-toolchain.
From-SVN: r276702
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2019-09-30 Andreas Tobler <andreast@gcc.gnu.org>
* config.gcc: Use the secure-plt on FreeBSD 13 and upwards for
32-bit PowerPC.
Define TARGET_FREEBSD32_SECURE_PLT for 64-bit PowerPC.
* config/rs6000/t-freebsd64: Make use of the above define and build
the 32-bit libraries with secure-plt.
From-SVN: r276295
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-mno-fdpic is provided
In FDPIC mode, we set -fPIE unless the user provides -fno-PIE, -fpie,
-fPIC or -fpic: indeed FDPIC code is PIC, but we want to generate code
for executables rather than shared libraries by default.
We also make sure to use the --fdpic assembler option, and select the
appropriate linker emulation.
At link time, we also default to -pie, unless we are generating a
shared library or a relocatable file (-r). Note that static link is
not supported as it requires specifying the dynamic linker because the
executable still has to relocate itself at startup.
We also force 'now' binding since lazy binding is not supported.
We should also apply the same behavior for -Wl,-Ur as for -r, but I
couldn't find how to describe that in the specs fragment.
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
gcc/
* config.gcc: Handle arm*-*-uclinuxfdpiceabi.
* config/arm/bpabi.h (TARGET_FDPIC_ASM_SPEC): New.
(SUBTARGET_EXTRA_ASM_SPEC): Use TARGET_FDPIC_ASM_SPEC.
* config/arm/linux-eabi.h (FDPIC_CC1_SPEC): New.
(CC1_SPEC): Use FDPIC_CC1_SPEC.
(MUSL_DYNAMIC_LINKER): Add -fdpic suffix when needed.
* config/arm/uclinuxfdpiceabi.h: New file.
libsanitizer/
* configure.tgt (arm*-*-*fdpiceabi): Sanitizers are
unsupported in this configuration.
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
From-SVN: r275565
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