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2021-04-12Add rocketlake to gcc.Cui,Lili1-1/+1
gcc/ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle rocketlake. * common/config/i386/i386-common.c (processor_names): Add rocketlake. (processor_alias_table): Add rocketlake. * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ROCKETLAKE. * config.gcc: Add -march=rocketlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle rocketlake. * config/i386/i386-options.c (m_ROCKETLAKE) : Define. (processor_cost_table): Add rocketlake cost. * config/i386/i386.h (ix86_size_cost) : Define TARGET_ROCKETLAKE. (processor_type) : Add PROCESSOR_ROCKETLAKE. (PTA_ROCKETLAKE): Ditto. * doc/extend.texi: Add rocketlake. * doc/invoke.texi: Add rocketlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march
2021-03-26d: Add windows support for D compiler [PR91595]Iain Buclaw1-0/+6
gcc/ChangeLog: PR d/91595 * config.gcc (*-*-cygwin*): Add winnt-d.o (*-*-mingw*): Likewise. * config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): New macro. * config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Likewise. * config/i386/t-cygming: Add winnt-d.o. * config/i386/winnt-d.c: New file.
2021-03-26d: Add openbsd support for D compiler [PR99691]Iain Buclaw1-0/+2
gcc/ChangeLog: PR d/99691 * config.gcc (*-*-openbsd*): Add openbsd-d.o. * config/t-openbsd: Add openbsd-d.o. * config/openbsd-d.c: New file.
2021-03-23RISC-V: Add riscv{32,64}be with big endian as defaultMarcus Comstedt1-0/+15
gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default endianness. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro.
2021-03-19Darwin : Fix build failure for powerpc-darwin8 [PR99661].Iain Sandoe1-1/+0
A hunk had been missed from r11-6417, fixed thus: gcc/ChangeLog: PR target/99661 * config.gcc (powerpc-*-darwin8): Delete the reference to the now removed darwin8.h.
2021-03-09RTEMS: Fix -Werror buildsSebastian Huber1-5/+5
Fix build errors due to warnings such as: gcc/config/v850/rtems.h:43: error: "RTEMS_STARTFILE_SPEC" redefined [-Werror] 43 | #define RTEMS_STARTFILE_SPEC "" The problem was that "gcc/config/rtems.h" was included before the architecture-specific "gcc/config/*/rtems.h" header file on some architectures. gcc/ * config.gcc (aarch64-*-rtems*): Include general rtems.h after the architecture-specific rtems.h. (aarch64-*-rtems*): Likewise. (arm*-*-rtems*): Likewise. (epiphany-*-rtems*): Likewise. (riscv*-*-rtems*): Likewise.
2021-03-02IBM Z: arch14: Add command line optionsAndreas Krebbel1-1/+1
Prepare GCC for a future architecture extension. gcc/ChangeLog: * common/config/s390/s390-common.c (processor_flags_table): New entry. * config.gcc: Enable arch14 for --with-arch and --with-tune. * config/s390/driver-native.c (s390_host_detect_local_cpu): Pick arch14 for unknown CPU models. * config/s390/s390-opts.h (enum processor_type): Add PROCESSOR_ARCH14. * config/s390/s390.c (s390_issue_rate): Add case for PROCESSOR_ARCH14. (s390_get_sched_attrmask): Likewise. (s390_get_unit_mask): Likewise. * config/s390/s390.h (enum processor_flags): Add PF_NNPA and PF_ARCH14. (TARGET_CPU_ARCH14, TARGET_CPU_ARCH14_P, TARGET_CPU_NNPA) (TARGET_CPU_NNPA_P, TARGET_ARCH14, TARGET_ARCH14_P, TARGET_NNPA) (TARGET_NNPA_P): New macro definitions. * config/s390/s390.md ("cpu_facility", "enabled"): Add arch14 and nnpa. * config/s390/s390.opt: Add PROCESSOR_ARCH14. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add check for nnpa facility.
2021-02-25Optimize pcrel access of globalsAaron Sawdey1-2/+6
This patch implements a RTL pass that looks for pc-relative loads of the address of an external variable using the PCREL_GOT relocation and a single load or store that uses that external address. Produced by a cast of thousands: * Michael Meissner * Peter Bergner * Bill Schmidt * Alan Modra * Segher Boessenkool * Aaron Sawdey gcc/ChangeLog: * config.gcc: Add rs6000-pcrel-opt.o. * config/rs6000/rs6000-pcrel-opt.c: New file. * config/rs6000/pcrel-opt.md: New file. * config/rs6000/predicates.md: Add d_form_memory predicate. * config/rs6000/rs6000-cpus.def: Add OPTION_MASK_PCREL_OPT. * config/rs6000/rs6000-passes.def: Add pass_pcrel_opt. * config/rs6000/rs6000-protos.h: Add reg_to_non_prefixed(), pcrel_opt_valid_mem_p(), output_pcrel_opt_reloc(), and make_pass_pcrel_opt(). * config/rs6000/rs6000.c (reg_to_non_prefixed): Make global. (rs6000_option_override_internal): Add pcrel-opt. (rs6000_delegitimize_address): Support pcrel-opt. (rs6000_opt_masks): Add pcrel-opt. (pcrel_opt_valid_mem_p): New function. (reg_to_non_prefixed): Make global. (rs6000_asm_output_opcode): Reset prepend_p_to_next_insn. (output_pcrel_opt_reloc): New function. * config/rs6000/rs6000.md (loads_extern_addr): New attr. (pcrel_extern_addr): Set loads_extern_addr. Add include for pcrel-opt.md. * config/rs6000/rs6000.opt: Add -mpcrel-opt. * config/rs6000/t-rs6000: Add rules for pcrel-opt.c and pcrel-opt.md. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pcrel-opt-inc-di.c: New test. * gcc.target/powerpc/pcrel-opt-ld-df.c: New test. * gcc.target/powerpc/pcrel-opt-ld-di.c: New test. * gcc.target/powerpc/pcrel-opt-ld-hi.c: New test. * gcc.target/powerpc/pcrel-opt-ld-qi.c: New test. * gcc.target/powerpc/pcrel-opt-ld-sf.c: New test. * gcc.target/powerpc/pcrel-opt-ld-si.c: New test. * gcc.target/powerpc/pcrel-opt-ld-vector.c: New test. * gcc.target/powerpc/pcrel-opt-st-df.c: New test. * gcc.target/powerpc/pcrel-opt-st-di.c: New test. * gcc.target/powerpc/pcrel-opt-st-hi.c: New test. * gcc.target/powerpc/pcrel-opt-st-qi.c: New test. * gcc.target/powerpc/pcrel-opt-st-sf.c: New test. * gcc.target/powerpc/pcrel-opt-st-si.c: New test. * gcc.target/powerpc/pcrel-opt-st-vector.c: New test.
2021-01-15aarch64: Add a minipass for fusing CC insns [PR88836]Richard Sandiford1-1/+1
This patch adds a small target-specific pass to remove redundant SVE PTEST instructions. There are two important uses of this: - Removing PTESTs after WHILELOs (PR88836). The original testcase no longer exhibits the problem due to more recent optimisations, but it can still be seen in simple cases like the one in the patch. It also shows up in 450.soplex. - Removing PTESTs after RDFFRs in ACLE code. This is just an interim “solution” for GCC 11. I hope to replace it with something generic and target-independent for GCC 12. However, the use cases above are very important for performance, so I'd rather not leave the bug unfixed for yet another release cycle. Since the pass is intended to be short-lived, I've not added a command-line option for it. The pass can be disabled using -fdisable-rtl-cc_fusion if necessary. Although what the pass does is independent of SVE, it's motivated only by SVE cases and doesn't trigger for any non-SVE test I've seen. I've therefore gated it on TARGET_SVE and restricted it to PTEST patterns. gcc/ PR target/88836 * config.gcc (aarch64*-*-*): Add aarch64-cc-fusion.o to extra_objs. * Makefile.in (RTL_SSA_H): New variable. * config/aarch64/t-aarch64 (aarch64-cc-fusion.o): New rule. * config/aarch64/aarch64-protos.h (make_pass_cc_fusion): Declare. * config/aarch64/aarch64-passes.def: Add pass_cc_fusion after pass_combine. * config/aarch64/aarch64-cc-fusion.cc: New file. gcc/testsuite/ PR target/88836 * gcc.target/aarch64/sve/acle/general/ldff1_8.c: New test. * gcc.target/aarch64/sve/ptest_1.c: Likewise.
2021-01-13Hurd: Enable ifunc by defaultSamuel Thibault1-1/+3
The binutils bugs seem to have been fixed. gcc/ * config.gcc [$target == *-*-gnu*]: Enable 'default_gnu_indirect_function'.
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2021-01-02Darwin, Simplify headers 4/5 : Remove redundant headers.Iain Sandoe1-9/+39
The darwinN.h headers (with the sole exception of darwin7.h, which contains a target macro definition) now only contain values that set fall-backs for cross-compilations, these can be provided from the config.gcc script which means we no longer need the darwinN.h - so delete them. gcc/ChangeLog: * config.gcc: Compute default version information from the configured target. Likewise defaults for ld64. * config/darwin10.h: Removed. * config/darwin12.h: Removed. * config/darwin9.h: Removed. * config/rs6000/darwin8.h: Removed.
2020-12-16rs6000: Add support for powerpc64le-unknown-freebsdPiotr Kubaj1-0/+4
This implements support for powerpc64le architecture on FreeBSD. Since we don't have powerpcle (32-bit), I did not add support for powerpcle here. This remains to be changed if there is powerpcle support in the future. 2020-12-15 Piotr Kubaj <pkubaj@FreeBSD.org> gcc/ * config.gcc (powerpc*le-*-freebsd*): Add. * configure.ac (powerpc*le-*-freebsd*): Ditto. * configure: Regenerate. * config/rs6000/freebsd64.h (ASM_SPEC_COMMON): Use ENDIAN_SELECT. (DEFAULT_ASM_ENDIAN): Add little endian support. (LINK_OS_FREEBSD_SPEC64): Ditto.
2020-12-15i386: Make -march=x86-64-v[234] behave more like other -march= optionsJakub Jelinek1-3/+1
If somebody has -march=x86-64-v2 (or -v3 or -v4) in $CFLAGS, $CXXFLAGS etc., then -m32 or -mabi=ms stops working. What is worse, if one configures gcc --with-arch-64=x86-64-v2 (or -v3 or -v4), then -mabi=ms stops working. I think that is a nightmare user experience. It is ok that x86-64-v[234] behave slightly different from other -march= options (in that they imply unless overridden -mtune=generic rather then -mtune= equal to the -march argument), but the error when one mixes it with -mabi=ms, or -m32 doesn't improve anything. It is true that the exact option set is only defined in the x86-64 psABI (IMHO that is a mistake too, we should copy that into the GCC documentation like we document it for any other -march= option), but there is no reason why that exact set of CPU features can't be used for other ABIs, it is just a set of CPU features. If we add micro-architecture levels to the 32-bit ABI (I doubt anyone wants to do that, but just hypothetically), then those micro-architecture levels wouldn't certainly be called x86-64-v* but perhaps i386-v*. In the tests, __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 can't be expected on -m32 not because the CPU feature wouldn't be set, but because the instruction is 64-bit only and 32-bit code doesn't have __int128 etc. support. 2020-12-15 Jakub Jelinek <jakub@redhat.com> * config/i386/i386-options.c (ix86_option_override_internal): Don't error on -march=x86-64-v[234] with -m32 or -mabi=ms. * config.gcc: Don't reject --with-arch=x86-64-v[234] or --with-arch_32=x86-64-v[234]. * doc/invoke.texi (-march=x86-64-v[234]): Document what the option does for other ABIs. * gcc.target/i386/x86-64-v2.c: Don't expect __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 to be defined with -m32. * gcc.target/i386/x86-64-v2-other.c: New test. * gcc.target/i386/x86-64-v2-msabi.c: New test. * gcc.target/i386/x86-64-v3.c: Fix a comment pasto. Don't expect __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 to be defined with -m32. * gcc.target/i386/x86-64-v3-other.c: New test. * gcc.target/i386/x86-64-v3-msabi.c: New test. * gcc.target/i386/x86-64-v4.c:Don't expect __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 to be defined with -m32. * gcc.target/i386/x86-64-v4-other.c: New test. * gcc.target/i386/x86-64-v4-msabi.c: New test.
2020-12-14disable --with-{cpu,arch,tune}-32Sebastian Pop1-10/+1
gcc/ * config.gcc (aarch64*-*-*): Remove --with-{cpu,arch,tune}-32 flags.
2020-12-14AArch64: Add support for --with-tuneWilco Dijkstra1-2/+13
Add support for --with-tune. Like --with-cpu and --with-arch, the argument is validated and transformed into a -mtune option to be processed like any other command-line option. --with-tune has no effect if a -mcpu or -mtune option is used. The validating code didn't allow --with-cpu=native, so explicitly allow that. Co-authored-by: Delia Burduv <delia.burduv@arm.com> Bootstrap OK, regress pass, OK to commit? 2020-09-03 Wilco Dijkstra <wdijkstr@arm.com> gcc/ * config.gcc (aarch64*-*-*): Add --with-tune. Support --with-cpu=native. * config/aarch64/aarch64.h (OPTION_DEFAULT_SPECS): Add --with-tune. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_tune_cortex_a76): New effective target test. * gcc.target/aarch64/with-tune-config.c: New test. * gcc.target/aarch64/with-tune-march.c: Likewise. * gcc.target/aarch64/with-tune-mcpu.c: Likewise. * gcc.target/aarch64/with-tune-mtune.c: Likewise.
2020-12-08PR target/98152: Checking python is available before usingKito Cheng1-1/+4
We'll try to canonicalize the arch string for --with-arch, and the script is written in python, however it will turns out GCC require python to build for RISC-V port, it's not expect as the GCC requirement. So this patch is made this as optional, detect python and only use it when it available, it won't break any functionality with out doing canonicalization, just might build one more redundant multi-lib. gcc/ChangeLog: PR target/98152 * config.gcc (riscv*-*-*): Checking python, python3 or python2 is available, and skip doing with_arch canonicalize if no python available.
2020-12-05X86_64: Enable support for next generation AMD Zen3 CPU.Venkataramanan Kumar1-1/+9
2020-12-03 Venkataramanan Kumar <Venkataramanan.Kumar@amd.com> Sharavan Kumar <Shravan.Kumar@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu) recognize znver3. * common/config/i386/i386-common.c (processor_names): Add znver3. (processor_alias_table): Add znver3 and AMDFAM19H entry. * common/config/i386/i386-cpuinfo.h (processor_types): Add AMDFAM19H. (processor_subtypes): AMDFAM19H_ZNVER3. * config.gcc (i[34567]86-*-linux* | ...): Likewise. * config/i386/driver-i386.c: (host_detect_local_cpu): Let -march=native recognize znver3 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add znver3. * config/i386/i386-options.c (m_znver3): New definition. (m_ZNVER): Include m_znver3. (processor_cost_table): Add znver3. * config/i386/i386.c (ix86_reassociation_width): Likewise. * config/i386/i386.h (TARGET_znver3): New definition. (enum processor_type): Add PROCESSOR_ZNVER3. * config/i386/i386.md (define_attr "cpu"): Add znver3. * config/i386/x86-tune-sched.c: (ix86_issue_rate): Likewise. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS: Likewise. * config/i386/znver1.md: Add new reservations for znver3. * doc/extend.texi: Add details about znver3. * doc/invoke.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv29.C: New file.
2020-12-03RISC-V: Canonicalize --with-archKito Cheng1-0/+1
- We would like to canonicalize the arch string for --with-arch for easier handling multilib, so split canonicalization part to a stand along script to shared the logic. gcc/ChangeLog: * config/riscv/multilib-generator (arch_canonicalize): Move code to arch-canonicalize, and call that script to canonicalize arch string. (canonical_order): Move code to arch-canonicalize. (LONG_EXT_PREFIXES): Ditto. (IMPLIED_EXT): Ditto. * config/riscv/arch-canonicalize: New. * config.gcc (riscv*-*-*): Canonicalize --with-arch.
2020-12-01x86: Add -mneeded for GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu1-2/+2
GCC 11 supports -march=x86-64-v[234] to enable x86 micro-architecture ISA levels: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97250 Binutils has been updated to support GNU_PROPERTY_X86_ISA_1_V[234] marker: https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/13 with commit b0ab06937385e0ae25cebf1991787d64f439bf12 Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri Oct 30 06:49:57 2020 -0700 x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE marker and commit 32930e4edbc06bc6f10c435dbcc63131715df678 Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri Oct 9 05:05:57 2020 -0700 x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker in x86 ELF binaries. Add -mneeded to emit GNU_PROPERTY_X86_ISA_1_NEEDED property to indicate the micro-architecture ISA level required to execute the binary. gcc/ * config.gcc: Replace cet.o with gnu-property.o. Replace i386/t-cet with i386/t-gnu-property. * config/i386/cet.c: Renamed to ... * config/i386/gnu-property.c: This. (emit_gnu_property): New function. (file_end_indicate_exec_stack_and_cet): Renamed to ... (file_end_indicate_exec_stack_and_gnu_property): This. Call emit_gnu_property to generate GNU_PROPERTY_X86_FEATURE_1_AND and GNU_PROPERTY_X86_ISA_1_NEEDED properties. * config/i386/i386.opt (mneeded): New. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): Renamed to ... (file_end_indicate_exec_stack_and_gnu_property): This. (TARGET_ASM_FILE_END): Updated. * config/i386/t-cet: Renamed to ... * config/i386/t-gnu-property: This. (cet.o): Renamed to ... (gnu-property.o): This. * doc/invoke.texi: Document -mneeded. gcc/testsuite/ * gcc.target/i386/x86-needed-1.c: New test. * gcc.target/i386/x86-needed-2.c: Likewise. * gcc.target/i386/x86-needed-3.c: Likewise.
2020-12-01RISC-V: Drop some commited accidentally code.Kito Cheng1-1/+0
gcc/ChangeLog: * config.gcc (riscv*-*-*): Drop some commited accidentally code.
2020-11-30d: Add freebsd support for D compiler and runtimeIain Buclaw1-0/+3
gcc/ChangeLog: PR d/87818 * config.gcc (*-*-freebsd*): Add freebsd-d.o and t-freebsd. * config/freebsd-d.c: New file. * config/t-freebsd: New file. libphobos/ChangeLog: PR d/87818 * configure.tgt: Add x86_64-*-freebsd* and i?86-*-freebsd* as supported targets.
2020-11-30RISC-V: Always define MULTILIB_DEFAULTSKito Cheng1-37/+3
- Define MULTILIB_DEFAULTS can reduce the total number of multilib if the default arch and ABI are listed in the multilib config. - This also simplify the implementation of --with-multilib-list. gcc/ChangeLog: * config.gcc (riscv*-*-*): Add TARGET_RISCV_DEFAULT_ABI and TARGET_RISCV_DEFAULT_ARCH to tm_defines. Remove including riscv/withmultilib.h for --with-multilib-list. * config/riscv/riscv.h (STRINGIZING): New. (__STRINGIZING): Ditto. (MULTILIB_DEFAULTS): Ditto. * config/riscv/withmultilib.h: Remove.
2020-11-29d: Add darwin support for D language front-endIain Buclaw1-0/+2
gcc/ChangeLog: * config.gcc (*-*-darwin*): Set d_target_objs and target_has_targetdm. * config/elfos.h (TARGET_D_MINFO_SECTION): New macro. (TARGET_D_MINFO_START_NAME): New macro. (TARGET_D_MINFO_END_NAME): New macro. * config/t-darwin: Add darwin-d.o. * doc/tm.texi: Regenerate. * doc/tm.texi.in (D language and ABI): Add @hook for TARGET_D_MINFO_SECTION, TARGET_D_MINFO_START_NAME, and TARGET_D_MINFO_END_NAME. * config/darwin-d.c: New file. gcc/d/ChangeLog: * d-target.def (d_minfo_section): New hook. (d_minfo_start_name): New hook. (d_minfo_end_name): New hook. * modules.cc: Include d-target.h. (register_moduleinfo): Update to use new targetdm hooks.
2020-11-18d: Add dragonflybsd support for D compiler and runtimeIain Buclaw1-0/+3
gcc/ChangeLog: * config.gcc (*-*-dragonfly*): Add dragonfly-d.o and t-dragonfly. * config/dragonfly-d.c: New file. * config/t-dragonfly: New file. libphobos/ChangeLog: * configure.tgt: Add *-*-dragonfly* as a supported target. * configure: Regenerate. * m4/druntime/os.m4 (DRUNTIME_OS_SOURCES): Add dragonfly* as a posix target.
2020-11-18RISC-V: Support version controling for ISA standard extensionsKito Cheng1-1/+16
- New option -misa-spec support: -misa-spec=[2.2|20190608|20191213] and corresponding configuration option --with-isa-spec. - Current default ISA spec set to 2.2, but we intend to bump this to 20191213 or later in next release. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_ext_version): New. (riscv_ext_version_table): Ditto. (get_default_version): Ditto. (riscv_subset_t::implied_p): New field. (riscv_subset_t::riscv_subset_t): Init implied_p. (riscv_subset_list::add): New. (riscv_subset_list::handle_implied_ext): Pass riscv_subset_t instead of separated argument. (riscv_subset_list::to_string): Handle zifencei and zicsr, and omit version if version is unknown. (riscv_subset_list::parsing_subset_version): New argument `ext`, remove default_major_version and default_minor_version, get default version info via get_default_version. (riscv_subset_list::parse_std_ext): Update argument for parsing_subset_version calls. Handle 2.2 ISA spec, always enable zicsr and zifencei, they are included in baseline ISA in that time. (riscv_subset_list::parse_multiletter_ext): Update argument for `parsing_subset_version` and `add` calls. (riscv_subset_list::parse): Adjust argument for riscv_subset_list::handle_implied_ext call. * config.gcc (riscv*-*-*): Handle --with-isa-spec=. * config.in (HAVE_AS_MISA_SPEC): New. (HAVE_AS_MARCH_ZIFENCEI): Ditto. * config/riscv/riscv-opts.h (riscv_isa_spec_class): New. (riscv_isa_spec): Ditto. * config/riscv/riscv.h (HAVE_AS_MISA_SPEC): New. (ASM_SPEC): Pass -misa-spec if gas supported. * config/riscv/riscv.opt (riscv_isa_spec_class) New. * configure.ac (HAVE_AS_MARCH_ZIFENCEI): New test. (HAVE_AS_MISA_SPEC): Ditto. * configure: Regen. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-9.c: New. * gcc.target/riscv/arch-10.c: Ditto. * gcc.target/riscv/arch-11.c: Ditto. * gcc.target/riscv/attribute-6.c: Remove, we don't support G with version anymore. * gcc.target/riscv/attribute-8.c: Reorder arch string to fit canonical ordering. * gcc.target/riscv/attribute-9.c: We don't emit version for unknown extensions now. * gcc.target/riscv/attribute-11.c: Add -misa-spec=2.2 flags. * gcc.target/riscv/attribute-12.c: Ditto. * gcc.target/riscv/attribute-13.c: Ditto. * gcc.target/riscv/attribute-14.c: Ditto. * gcc.target/riscv/attribute-15.c: New. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto.
2020-11-17add --with-{cpu,arch,tune}-{32,64} as alias flags for --with-{cpu,arch,tune}Sebastian Pop1-1/+19
gcc/ * config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64} as alias flags for --with-{cpu,arch,tune} on AArch64. * doc/install.texi: Document new flags for aarch64.
2020-11-17add --with-tune configure flagSebastian Pop1-3/+2
fixes a configure error on Arm64 when passing --with-tune=... to configure: ``` This target does not support --with-tune. Valid --with options are: abi cpu arch ``` The missing flag sets target tuning to a different value than generic tuning. gcc/ * config.gcc: Add --with-tune to AArch64 configure flags.
2020-11-11Support Intel AVX VNNIliuhongt1-2/+2
2020-10-13 Hongtao Liu <hongtao.liu@intel.com> Hongyu Wang <hongyu.wang@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect AVXVNNI. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AVXVNNI_SET, OPTION_MASK_ISA2_AVXVNNI_UNSET): New. (OPTION_MASK_ISA2_AVX2_UNSET): Add AVXVNNI. (ix86_hanlde_option): Handle -mavxvnni, unset avxvnni when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNI. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avxvnni. * config.gcc: Add avxvnniintrin.h. * config/i386/avx512vnnivlintrin.h: Reimplement 128/256 bit non-mask intrinsics with macros to support unified interface. * config/i386/avxvnniintrin.h: New header file. * config/i386/cpuid.h (bit_AVXVNNI): New. * config/i386/i386-builtins.c (def_builtin): Handle AVXVNNI mask for unified builtin. * config/i386/i386-builtin.def (BDESC): Adjust AVX512VNNI builtins for AVXVNNI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVXVNNI__. * config/i386/i386-expand.c (ix86_expand_builtin): Handle bisa for AVXVNNI to support unified intrinsic name, since there is no dependency between AVX512VNNI and AVXVNNI. * config/i386/i386-options.c (isa2_opts): Add -mavxvnni. (ix86_valid_target_attribute_inner_p): Handle avxnnni. (ix86_option_override_internal): Ditto. * config/i386/i386.h (TARGET_AVXVNNI, TARGET_AVXVNNI_P, TARGET_AVXVNNI_P, PTA_AVXVNNI): New. (PTA_SAPPHIRERAPIDS): Add AVX_VNNI. (PTA_ALDERLAKE): Likewise. * config/i386/i386.md ("isa"): Add avxvnni, avx512vnnivl. ("enabled"): Adjust for avxvnni and avx512vnnivl. * config/i386/i386.opt: Add option -mavxvnni. * config/i386/immintrin.h: Include avxvnniintrin.h. * config/i386/sse.md (vpdpbusd_<mode>): Adjust for AVXVNNI. (vpdpbusds_<mode>): Likewise. (vpdpwssd_<mode>): Likewise. (vpdpwssds_<mode>): Likewise. (vpdpbusd_v16si): New. (vpdpbusds_v16si): Likewise. (vpdpwssd_v16si): Likewise. (vpdpwssds_v16si): Likewise. * doc/invoke.texi: Document -mavxvnni. * doc/extend.texi: Document avxvnni. * doc/sourcebuild.texi: Document target avxvnni. gcc/testsuite/ * gcc.target/i386/avx512vl-vnni-1.c: Rename.. * gcc.target/i386/avx512vl-vnni-1a.c: To This. * gcc.target/i386/avx512vl-vnni-1b.c: New test. * gcc.target/i386/avx512vl-vnni-2.c: Ditto. * gcc.target/i386/avx512vl-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-1.c: Ditto. * gcc.target/i386/avx-vnni-2.c: Ditto. * gcc.target/i386/avx-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-4.c: Ditto. * gcc.target/i386/avx-vnni-5.c: Ditto. * gcc.target/i386/avx-vnni-6.c: Ditto. * gcc.target/i386/avx-vpdpbusd-2.c: Ditto. * gcc.target/i386/avx-vpdpbusds-2.c: Ditto. * gcc.target/i386/avx-vpdpwssd-2.c: Ditto. * gcc.target/i386/avx-vpdpwssds-2.c: Ditto. * gcc.target/i386/vnni_inline_error.c: Ditto. * gcc.target/i386/avx512vnnivl-builtin.c: Ditto. * gcc.target/i386/avxvnni-builtin.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxvnni. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp (check_effective_target_avxvnni): New proc.
2020-11-02RISC-V: Add configure option: --with-multilib-generator to flexible config ↵Kito Cheng1-5/+31
multi-lib settings. - Able to configure complex multi-lib rule in configure time, without modify any in-tree source. - I was consider to implmenet this into `--with-multilib-list` option, but I am not sure who will using that with riscv*-*-elf*, so I decide to using another option name for that. - --with-multilib-generator will pass arguments to multilib-generator, and then using the generated multi-lib config file to build the toolchain. e.g. Build riscv gcc, default arch/abi is rv64gc/lp64, and build multilib for rv32imafd/ilp32 and rv32i/ilp32; rv32ic/ilp32 will reuse rv32i/ilp32. $ <GCC-SRC>/configure \ --target=riscv64-elf \ --with-arch=rv64gc --with-abi=lp64 \ --with-multilib-generator=rv32i-ilp32--c;rv32imafd-ilp32-- V3 Changes: - Rename --with-multilib-config to --with-multilib-generator - Check --with-multilib-generator and --with-multilib-list can't be used at same time. V2 Changes: - Fix --with-multilib-config hanling on non riscv*-*-elf* triple. gcc/ChangeLog: * config.gcc (riscv*-*-*): Handle --with-multilib-generator. * configure: Regen. * configure.ac: Add --with-multilib-generator. * config/riscv/multilib-generator: Exit when parsing arch string error. * config/riscv/t-withmultilib-generator: New. * doc/install.texi: Document --with-multilib-generator.
2020-10-30Introduce support for vxworks7r2 on x86 and x86_64Olivier Hainque1-1/+1
This change extends the VxWorks support on intel CPUs to VxWorks7r2 for x86_64 as well as x86, with a "mcmodel=large" additional multilib for the 64bit configuration. The support for fPIC is not functional yet for this model, so we just don't add the corresponding multilib. We extend the range of CPU families handled by TARGET_OS_CPP_BUILTINS, accounting for the fact that archs older than PENTIUM4 are not supported (any more) by VxWorks 7. As we did for powerpc, we leverage VX_CPU_PREFIX to emit different forms of definitions for different families of VxWorks as the system headers's expectations has evolved between Vx 5, 6 and 7. 2020-10-27 Olivier Hainque <hainque@adacore.com> gcc/ * config.gcc: Adjust the ix86/x86_64-wrs-vxworks filters to apply to VxWorks 7 as well. * config/i386/t-vxworks (MULTILIB_OPTIONS, MULTILIB_DIRNAMES): Remove the fPIC multilib and add one for the large code model on x86_64. * config/i386/vxworks.h: Separate sections for TARGET_VXWORKS7, other variants and common bits. (TARGET_OS_CPP_BUILTINS): Augment to support a range of CPU families. Leverage VX_CPU_PREFIX. (CC1_SPEC): Add definition. (STACK_CHECK_PROTECT): Use conditional expression instead of heavier to read conditioned macro definitions. libgcc/ * config.host: Adjust the ix86/x86_64-wrs-vxworks filters to apply to VxWorks 7 as well. Co-authored-by: Douglas Rupp <rupp@adacore.com> Co-authored-by: Pat Bernardi <bernardi@adacore.com>
2020-10-29Enable GCC to support Intel Key Locker ISAliuhongt1-2/+2
gcc/ChangeLog 2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com> Hongyu Wang <hongyu.wang@intel.com> Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/cpuinfo.h (get_available_features): Detect KL, AESKLE and WIDEKL features. * common/config/i386/i386-common.c (OPTION_MASK_ISA_KL_SET): New. (OPTION_MASK_ISA_WIDEKL_SET): Likewise. (OPTION_MASK_ISA_KL_UNSET): Likewise. (OPTION_MASK_ISA_WIDEKL_UNSET): Likewise. (OPTION_MASK_ISA2_AVX2_UNSET): Likewise. (OPTION_MASK_ISA2_AVX_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_UNSET): Likewise. (OPTION_MASK_ISA2_SSSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE_UNSET): Likewise. (ix86_handle_option): Handle kl and widekl, add dependency chain for KL and SSE2. * common/config/i386/i386-cpuinfo.h (enum processor_features): (FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for KL, AESKLE and WIDEKL. * config.gcc: Add keylockerintrin.h. * doc/invoke.texi: Document new option -mkl and -mwidekl. * doc/extend.texi: Document kl and widekl. * config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New. * config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID), (UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT), (UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New function types. * config/i386/i386-builtin.def: Add __builtin_ia32_loadiwkey, __builtin_ia32_aesdec128kl_u8, __builtin_ia32_aesdec256kl_u8, __builtin_ia32_aesenc128kl_u8, __builtin_ia32_aesenc256kl_u8, __builtin_ia32_aesdecwide128kl_u8, __builtin_ia32_aesdecwide256kl_u8, __builtin_ia32_aesencwide128kl_u8, __builtin_ia32_aesencwide256kl_u8, __builtin_ia32_encodekey128_u32, __builtin_ia32_encodekey256_u32. * config/i386/i386-c.c (ix86_target_macros_internal): Handle kl and widekl. * config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl. (ix86_option_override_internal): Handle KL and WIDEKL. (ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl. * config/i386/i386-expand.c (ix86_expand_builtin): Expand Keylocker Builtins. * config/i386/i386.h (TARGET_KL): New. (TARGET_KL_P): Likewise. (TARGET_WIDEKL): Likewise. (TARGET_WIDEKL_P): Likewise. (PTA_KL): Likewise. (PTA_WIDEKL): Likewise. (PTA_TIGERLAKE): Add PTA_KL, PTA_WIDEKL. (PTA_ALDERLAKE): Likewise. * config/i386/i386.opt: Add new option mkl and mwidekl. * config/i386/keylockerintrin.h: New header file for Keylocker. * config/i386/immintrin.h: Include keylockerintrin.h. * config/i386/predicates.md (encodekey128_operation): New predicate. (encodekey256_operation): Likewise. (aeswidekl_operation): Likewise. * config/i386/sse.md (UNSPECV_LOADIWKEY): New. (UNSPECV_AESDEC128KLU8): Likewise. (UNSPECV_AESENC128KLU8): Likewise. (UNSPECV_AESDEC256KLU8): Likewise. (UNSPECV_AESENC256KLU8): Likewise. (UNSPECV_AESDECWIDE128KLU8): Likewise. (UNSPECV_AESENCWIDE128KLU8): Likewise. (UNSPECV_AESDECWIDE256KLU8): Likewise. (UNSPECV_AESENCWIDE256KLU8): Likewise. (UNSPECV_ENCODEKEY128U32): Likewise. (UNSPECV_ENCODEKEY256U32): Likewise. (encodekey128u32): New expander. (encodekey256u32): Likewise. (aes<aeswideklvariant>u8): Likewise. (loadiwkey): New insn pattern. (*encodekey128u32): Likewise. (*encodekey256u32): Likewise. (aes<aesklvariant>u8): Likewise. (*aes<aeswideklvariant>u8): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/keylocker-aesdec128kl.c: New test. * gcc.target/i386/keylocker-aesdec256kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise. * gcc.target/i386/keylocker-aesenc128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide256kl.c: Likewise. * gcc.target/i386/keylocker-encodekey128.c: Likewise. * gcc.target/i386/keylocker-encodekey256.c: Likewise. * gcc.target/i386/keylocker-loadiwkey.c: Likewise. * g++.dg/other/i386-2.C: Add -mkl and -mwidekl. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Add kl and widekl. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/funcspec-56.inc: Add new target attribute test.
2020-10-22x86: Allow configuring with --with-arch_64=x86-64-v[234]Jakub Jelinek1-2/+15
> + {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE}, > + {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE, > + 0, P_NONE}, > + {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE, > + 0, P_NONE}, > + {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE, > + 0, P_NONE}, > {"eden-x2", PROCESSOR_K8, CPU_K8, > PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, > 0, P_NONE}, I have noticed that one can't configure gcc to default to these. I've also found various other 32-bit or 64-bit -march= arguments for which it wasn't possible to configure gcc to default to those. The x86-64-v* the patch only allows in --with-arch_64=, because otherwise it fails build miserably - as ./xgcc -B ./ -S -march=x86-64-v2 -m32 test.c cc1: error: ‘x86-64-v2’ architecture level is only defined for the x86-64 psABI when building 32-bit multilibs. Even if multilibs are disallowed, I think the compiler still supports -m32 and so --with-arch_64= seems to be the only option in which we can support that. 2020-10-22 Jakub Jelinek <jakub@redhat.com> * config.gcc (x86_archs): Add samuel-2, nehemiah, c7 and esther. (x86_64_archs): Add eden-x2, nano, nano-1000, nano-2000, nano-3000, nano-x2, eden-x4, nano-x4, x86-64-v2, x86-64-v3 and x86-64-v4. (i[34567]86-*-* | x86_64-*-*): Only allow x86-64-v* as argument to --with-arch_64=.
2020-10-21Introduce vxworks7r2 support for ppc and ppc64Douglas Rupp1-0/+21
This change introduces support for the most recent versions of VxWorks on PowerPC targets, for both 32 and 64 bit thanks to a bi-arch setup. The system compilers are essentially configured as Linux toolchains with only a few specificities and we replicate that model here. The most visible specificities are the use of secureplt by default, the pre-definition of some macros that the system headers still rely on (_VX_CPU and _VX_CPU_FAMILY, for example), and of course some variations related to the so VxWorks typical kernel vs RTP mode distinction. In addition to the introduction of config.gcc and libgcc configuration chunks, much inspired by the linux ones, the change - Reworks rs6000/vxworks.h file to feature bits common to the Vx6 and Vx7 port then a separate section for each, where the Vx7 part is very short as we rely on the Linux definitions for most things. - Adjusts the CPU macro predefinitions in CPP_SPEC to resort to "_VX_CPU" instead of "CPU" for Vx7, to better match the more recent system headers expectations, - Adds a cpu definition case for e6500. - Changes to the use SUB3TARGET_OVERRIDE_OPTIONS instead of SUBSUBTARGET_OVERRIDE_OPTIONS for specifics, so we don't override the Linux's version of the latter for vx7. 2020-10-20 Douglas Rupp <rupp@adacore.com> gcc/ * config.gcc (powerpc*-wrs-vxworks7r*): New case. * config/rs6000/vxworks.h: Rework to handle VxWorks7. Refactor as common bits + vx6 vs vx7 ones. For the latter, rely essentially on the Linux configuration and adjust CPU to _VX_CPU in CPP_SPEC. Add a case for e6500. Use SUB3TARGET_OVERRIDE_OPTIONS for specifics to preserve the Linux SUBSUBTARGET_OVERRIDE_OPTIONS for vx7. libgcc/ * config.host (powerpc*-wrs-vxworks7*): New case. * configure.ac: Handle powerpc*-*-vxworks7* as powerpc*-*-linux* for ppc-fp_type. * configure: Regenerate. Co-authored-by: Olivier Hainque <hainque@adacore.com>
2020-10-15Enable Intel HRESET InstructionHongyu Wang1-2/+4
gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -mhreset. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add mhreset. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-10-15Enable gcc support for UINTRliuhongt1-2/+2
2020-05-20 Hongtao Liu <hongtao.liu@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect UINTR. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR_UNSET): New. (ix86_handle_option): Handle -muintr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_UINTR. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for uintr. * config.gcc: Add uintrintrin.h to extra_headers. * config/i386/uintrintrin.h: New. * config/i386/cpuid.h (bit_UINTR): New. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Add __builtin_ia32_testui. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_TESTUI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __UINTR__. * config/i386/i386-expand.c (ix86_expand_special_args_builtin): Handle UINT8_FTYPE_VOID. (ix86_expand_builtin): Handle IX86_BUILTIN_TESTUI. * config/i386/i386-options.c (isa2_opts): Add -muintr. (ix86_valid_target_attribute_inner_p): Handle UINTR. (ix86_option_override_internal): Add TARGET_64BIT check for UINTR. * config/i386/i386.h (TARGET_UINTR, TARGET_UINTR_P, PTA_UINTR): New. (PTA_SAPPHIRRAPIDS): Add PTA_UINTR. * config/i386/i386.opt: Add -muintr. * config/i386/i386.md (define_int_iterator UINTR_UNSPECV): New. (define_int_attr uintr_unspecv): New. (uintr_<uintr_unspecv>, uintr_senduipi, testui): New define_insn patterns. * config/i386/x86gprintrin.h: Include uintrintrin.h * doc/invoke.texi: Document -muintr. * doc/extend.texi: Document uintr. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/uintr-1.c: New test. * gcc.target/i386/uintr-2.c: Ditto. * gcc.target/i386/uintr-3.c: Ditto. * gcc.target/i386/uintr-4.c: Ditto. * gcc.target/i386/uintr-5.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Add -muintr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add muintr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-10-09x86: Add <x86gprintrin.h>H.J. Lu1-2/+2
For sources which can't use any vector instructions, <x86intrin.h> and <immintrin.h> cannot be included for compiler intrinsics: $ echo "#include <x86intrin.h>" | gcc -S -O2 -mno-sse -mno-mmx -x c - In file included from /usr/include/stdlib.h:1013, from /usr/lib/gcc/x86_64-redhat-linux/10/include/mm_malloc.h:27, from /usr/lib/gcc/x86_64-redhat-linux/10/include/xmmintrin.h:34, from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:29, from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32, from <stdin>:1: /usr/include/bits/stdlib-float.h: In function ‘atof’: /usr/include/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled 26 | { | ^ $ libgcc/config/i386/shadow-stack-unwind.h has a workaround: /* NB: We need _get_ssp and _inc_ssp from <cetintrin.h>. But we can't include <x86intrin.h> which ends up including <mm_malloc.h>, which includes <stdlib.h> and <errno.h> unconditionally. But we can't include any libc system headers unconditionally from libgcc. Avoid including <mm_malloc.h> here by defining _IMMINTRIN_H_INCLUDED. */ #define _IMMINTRIN_H_INCLUDED #include <cetintrin.h> #undef _IMMINTRIN_H_INCLUDED Add a standalone intrinsic header file, <x86gprintrin.h>, to provide integer only intrinsics. All integer only intrinsics are placed in <x86gprintrin.h>. <x86intrin.h> and <immintrin.h> simply include <x86gprintrin.h>. gcc/ PR target/97148 * config.gcc (extra_headers): Add x86gprintrin.h. * config/i386/adxintrin.h: Check _X86GPRINTRIN_H_INCLUDED for <x86gprintrin.h>. * config/i386/bmi2intrin.h: Likewise. * config/i386/bmiintrin.h: Likewise. * config/i386/cetintrin.h: Likewise. * config/i386/cldemoteintrin.h: Likewise. * config/i386/clflushoptintrin.h: Likewise. * config/i386/clwbintrin.h: Likewise. * config/i386/enqcmdintrin.h: Likewise. * config/i386/fxsrintrin.h: Likewise. * config/i386/ia32intrin.h: Likewise. * config/i386/lwpintrin.h: Likewise. * config/i386/lzcntintrin.h: Likewise. * config/i386/movdirintrin.h: Likewise. * config/i386/pconfigintrin.h: Likewise. * config/i386/pkuintrin.h: Likewise. * config/i386/rdseedintrin.h: Likewise. * config/i386/rtmintrin.h: Likewise. * config/i386/serializeintrin.h: Likewise. * config/i386/tbmintrin.h: Likewise. * config/i386/tsxldtrkintrin.h: Likewise. * config/i386/waitpkgintrin.h: Likewise. * config/i386/wbnoinvdintrin.h: Likewise. * config/i386/xsavecintrin.h: Likewise. * config/i386/xsaveintrin.h: Likewise. * config/i386/xsaveoptintrin.h: Likewise. * config/i386/xsavesintrin.h: Likewise. * config/i386/xtestintrin.h: Likewise. * config/i386/immintrin.h: Include <x86gprintrin.h> instead of <fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>, <xsavesintrin.h>, <xsavecintrin.h>, <lzcntintrin.h>, <bmiintrin.h>, <bmi2intrin.h>, <xtestintrin.h>, <cetintrin.h>, <movdirintrin.h>, <sgxintrin.h, <pconfigintrin.h>, <waitpkgintrin.h>, <cldemoteintrin.h>, <enqcmdintrin.h>, <serializeintrin.h>, <tsxldtrkintrin.h>, <adxintrin.h>, <clwbintrin.h>, <clflushoptintrin.h>, <wbnoinvdintrin.h> and <pkuintrin.h>. (_wbinvd): Moved to config/i386/x86gprintrin.h. (_rdrand16_step): Likewise. (_rdrand32_step): Likewise. (_rdpid_u32): Likewise. (_readfsbase_u32): Likewise. (_readfsbase_u64): Likewise. (_readgsbase_u32): Likewise. (_readgsbase_u64): Likewise. (_writefsbase_u32): Likewise. (_writefsbase_u64): Likewise. (_writegsbase_u32): Likewise. (_writegsbase_u64): Likewise. (_rdrand64_step): Likewise. (_ptwrite64): Likewise. (_ptwrite32): Likewise. * config/i386/x86gprintrin.h: New file. * config/i386/x86intrin.h: Include <x86gprintrin.h>. Don't include <ia32intrin.h>, <lwpintrin.h>, <tbmintrin.h>, <popcntintrin.h>, <mwaitxintrin.h> and <clzerointrin.h>. gcc/testsuite/ * gcc.target/i386/avx-1.c (__builtin_ia32_lwpval32): New to support <lwpintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_lwpval64): Likewise. (__builtin_ia32_lwpins32): Likewise. (__builtin_ia32_lwpins64): Likewise. (__builtin_ia32_bextri_u32): New to support <tbmintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_bextri_u64): Likewise. * gcc.target/i386/x86gprintrin-1.c: New test. * gcc.target/i386/x86gprintrin-2.c: Likewise. * gcc.target/i386/x86gprintrin-3.c: Likewise. * gcc.target/i386/x86gprintrin-4.c: Likewise. * gcc.target/i386/x86gprintrin-4a.c: Likewise. * gcc.target/i386/x86gprintrin-5.c: Likewise. * gcc.target/i386/x86gprintrin-5a.c: Likewise. * gcc.target/i386/x86gprintrin-5b.c: Likewise. * gcc.target/i386/x86gprintrin-6.c: Likewise. libgcc/ PR target/97148 * config/i386/shadow-stack-unwind.h: Include <x86gprintrin.h> instead of <cetintrin.h>.
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt1-2/+4
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto.
2020-09-16C-SKY: Set use_gcc_stdint=wrap for elf targetJojo R1-0/+1
gcc/ChangeLog: * config.gcc (C-SKY): Set use_gcc_stdint=wrap for elf target.
2020-09-02bpf: use elfos.hJose E. Marchesi1-0/+1
BPF is an ELF-based target, so it definitely benefits from using elfos.h. This patch makes the target to use it, and removes superfluous definitions from bpf.h which are better defined in elfos.h. Note that BPF, despite being an ELF target, doesn't use DWARF. At some point it will generate DWARF when generating xBPF (-mxbpf) and BTF when generating plain eBPF, but for the time being it just generates stabs. 2020-09-02 Jose E. Marchesi <jemarch@gnu.org> gcc/ * config.gcc: Use elfos.h in bpf-*-* targets. * config/bpf/bpf.h (MAX_OFILE_ALIGNMENT): Remove definition. (COMMON_ASM_OP): Likewise. (INIT_SECTION_ASM_OP): Likewise. (FINI_SECTION_ASM_OP): Likewise. (ASM_OUTPUT_SKIP): Likewise. (ASM_OUTPUT_ALIGNED_COMMON): Likewise. (ASM_OUTPUT_ALIGNED_LOCAL): Likewise.
2020-07-24aix: Support GCC64 for AIX 7.1.David Edelsohn1-2/+6
gcc/ChangeLog: 2020-07-24 David Edelsohn <dje.gcc@gmail.com> Clement Chigot <clement.chigot@atos.net> * config.gcc (powerpc-ibm-aix7.1): Use t-aix64 and biarch64 for cpu_is_64bit. * config/rs6000/aix71.h (ASM_SPEC): Remove aix64 option. (ASM_SPEC32): New. (ASM_SPEC64): New. (ASM_CPU_SPEC): Remove vsx and altivec options. (CPP_SPEC_COMMON): Rename from CPP_SPEC. (CPP_SPEC32): New. (CPP_SPEC64): New. (CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON.. (TARGET_DEFAULT): Use 64 bit mask if BIARCH. (LIB_SPEC_COMMON): Rename from LIB_SPEC. (LIB_SPEC32): New. (LIB_SPEC64): New. (LINK_SPEC_COMMON): Rename from LINK_SPEC. (LINK_SPEC32): New. (LINK_SPEC64): New. (STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase. (ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P. (CPP_SPEC): Same. (CPLUSPLUS_CPP_SPEC): Same. (LIB_SPEC): Same. (LINK_SPEC): Same. (SUBTARGET_EXTRA_SPECS): Add new 32/64 specs. * config/rs6000/aix72.h (TARGET_DEFAULT): Use 64 bit mask if BIARCH. * config/rs6000/defaultaix64.h: Delete.
2020-07-10Initial Sapphire Rapids and Alder Lake support from ISA r40Cui,Lili1-2/+2
gcc/ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle sapphirerapids. * common/config/i386/i386-common.c (processor_names): Add sapphirerapids and alderlake. (processor_alias_table): Add sapphirerapids and alderlake. * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ALDERLAKE and INTEL_COREI7_ALDERLAKE. * config.gcc: Add -march=sapphirerapids and alderlake. * config/i386/driver-i386.c (host_detect_local_cpu) Handle sapphirerapids and alderlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle sapphirerapids and alderlake. * config/i386/i386-options.c (m_SAPPHIRERAPIDS) : Define. (m_ALDERLAKE): Ditto. (m_CORE_AVX512) : Add m_SAPPHIRERAPIDS. (processor_cost_table): Add sapphirerapids and alderlake. (ix86_option_override_internal) Handle PTA_WAITPKG, PTA_ENQCMD, PTA_CLDEMOTE, PTA_SERIALIZE, PTA_TSXLDTRK. * config/i386/i386.h (ix86_size_cost) : Define SAPPHIRERAPIDS and ALDERLAKE. (processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and PROCESSOR_ALDERLAKE. (PTA_ENQCMD): New. (PTA_CLDEMOTE): Ditto. (PTA_SERIALIZE): Ditto. (PTA_TSXLDTRK): New. (PTA_SAPPHIRERAPIDS): Ditto. (PTA_ALDERLAKE): Ditto. (processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and PROCESSOR_ALDERLAKE. * doc/extend.texi: Add sapphirerapids and alderlake. * doc/invoke.texi: Add sapphirerapids and alderlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march
2020-06-23Allow --with-cpu=power10Aaron Sawdey1-2/+2
Update config.gcc so that we can use --with-cpu=power10. Also remove "future" from the 64-bit check as Segher suggests. * config.gcc: Identify power10 as a 64-bit processor and as valid for --with-cpu and --with-tune.
2020-06-21aix: Add GCC64 configuration and FAT target libraries.David Edelsohn1-1/+5
This patch adds the ability to configure GCC on AIX to build as a 64 bit application and to build target libraries "FAT" libraries in both 32 bit and 64 bit mode. The patch adds makefile fragment hooks to target libraries that allows them to include target-specific rules. The target specific rules for AIX place both 32 bit and 64 bit objects and shared objects in archives at the top-level, not multilib subdirectories. The multilibs are built in subdirectories, but must be combined during the last parts of the target library build process. Because of the way that GCC bootstrap works, the libraries must be combined during the multiple stages of GCC bootstrap, not solely when installed in the final destination, so the libraries are correct at the end of each target library build stage, not solely an install recipe. gcc/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * config.gcc: Use t-aix64, biarch64 and default64 for cpu_is_64bit. * config/rs6000/aix72.h (ASM_SPEC): Remove aix64 option. (ASM_SPEC32): New. (ASM_SPEC64): New. (ASM_CPU_SPEC): Remove vsx and altivec options. (CPP_SPEC_COMMON): Rename from CPP_SPEC. (CPP_SPEC32): New. (CPP_SPEC64): New. (CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON.. (TARGET_DEFAULT): Only define if not BIARCH. (LIB_SPEC_COMMON): Rename from LIB_SPEC. (LIB_SPEC32): New. (LIB_SPEC64): New. (LINK_SPEC_COMMON): Rename from LINK_SPEC. (LINK_SPEC32): New. (LINK_SPEC64): New. (STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase. (ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P. (CPP_SPEC): Same. (CPLUSPLUS_CPP_SPEC): Same. (LIB_SPEC): Same. (LINK_SPEC): Same. (SUBTARGET_EXTRA_SPECS): Add new 32/64 specs. * config/rs6000/defaultaix64.h: New file. * config/rs6000/t-aix64: New file. libgcc/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * config.host (extra_parts): Add crtcxa_64 and crtdbase_64. * config/rs6000/t-aix-cxa: Explicitly compile 32 bit with -maix32 and 64 bit with -maix64. * config/rs6000/t-slibgcc-aix: Remove extra @multilib_dir@ level. Build and install AIX-style FAT libraries. libgomp/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.tgt (powerpc-ibm-aix*): Define tmake_file. * config/t-aix: New file. libstdc++-v3/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.host (aix*): Define tmake_file. * config/os/aix/t-aix: New file. libatomic/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.tgt (powerpc-ibm-aix*): Define tmake_file. * config/t-aix: New file. libgfortran/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.host: Add system configury stanza. Define tmake_file. * config/t-aix: New file.
2020-06-02Fix unrecognised -mcpu target 'armv7-a' on arm-wrs-vxworks7Iain Buclaw1-1/+1
In the removal of arm-wrs-vxworks, the default cpu was updated from arm8 to armv7-a, but this is not recognized as a valid -mcpu target. There is however generic-armv7-a, which was likely the intended cpu that should have been used instead. gcc/ChangeLog: PR target/95420 * config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a.
2020-05-12RISC-V: Add shorten_memrefs pass.Craig Blackmore1-1/+1
gcc/ * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv. * config/riscv/riscv-passes.def: New file. * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare. * config/riscv/riscv-shorten-memrefs.c: New file. * config/riscv/riscv.c (tree-pass.h): New include. (riscv_compressed_reg_p): New Function (riscv_compressed_lw_offset_p): Likewise. (riscv_compressed_lw_address_p): Likewise. (riscv_shorten_lw_offset): Likewise. (riscv_legitimize_address): Attempt to convert base + large_offset to compressible new_base + small_offset. (riscv_address_cost): Make anticipated compressed load/stores cheaper for code size than uncompressed load/stores. (riscv_register_priority): Move compressed register check to riscv_compressed_reg_p. * config/riscv/riscv.h (C_S_BITS): Define. (CSW_MAX_OFFSET): Define. * config/riscv/riscv.opt (mshorten-memefs): New option. * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule. (PASSES_EXTRA): Add riscv-passes.def. * doc/invoke.texi: Document -mshorten-memrefs. * config/riscv/riscv.c (riscv_new_address_profitable_p): New function. (TARGET_NEW_ADDRESS_PROFITABLE_P): Define. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook. * sched-deps.c (attempt_change): Use old address if it is cheaper than new address. * target.def (new_address_profitable_p): New hook. * targhooks.c (default_new_address_profitable_p): New function. * targhooks.h (default_new_address_profitable_p): Declare. gcc/testsuite/ * gcc.target/riscv/shorten-memrefs-1.c: New test. * gcc.target/riscv/shorten-memrefs-2.c: New test. * gcc.target/riscv/shorten-memrefs-3.c: New test. * gcc.target/riscv/shorten-memrefs-4.c: New test. * gcc.target/riscv/shorten-memrefs-5.c: New test. * gcc.target/riscv/shorten-memrefs-6.c: New test. * gcc.target/riscv/shorten-memrefs-7.c: New test.
2020-05-09config.gcc: Remove support for crisv32-*-* and cris-*-linux*.Hans-Peter Nilsson1-26/+2
Or really, move from the obsolete targets section, to unsupported targets section, and remove crisv32-*-* and cris-*-linux* from the rest. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). gcc: * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt1-2/+4
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET, OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros. * config.gcc: Add tsxldtrkintrin.h to extra_headers. * config/i386/driver-i386.c (host_detect_local_cpu): Detect TSXLDTRK. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __TSXLDTRK__. * config/i386/i386-options.c (ix86_target_string): Add -mtsxldtrk. (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk. * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P): New. * config/i386/i386.md (define_c_enum "unspec"): Add UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK. (TSXLDTRK): New define_int_iterator. ("<tsxldtrk>"): New define_insn. * config/i386/i386.opt: Add -mtsxldtrk. * config/i386/immintrin.h: Include tsxldtrkintrin.h. * config/i386/tsxldtrkintrin.h: New. * doc/invoke.texi: Document -mtsxldtrk. gcc/testsuite/ * g++.dg/other/i386-2.c: Add -mtsxldtrk. * g++.dg/other/i386-3.c: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewsie. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/tsxldtrk-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add target attribute tests for tsxldtrk.
2020-05-06Enable GCC support for SERIALIZEliuhongt1-4/+6
2020-03-04 Hongtao Liu <hongtao.liu@intel.com> 2020-03-04 Wei Xiao <wei3.xiao@intel.com> gcc/Changelog: * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET, OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros. (ix86_handle_option): Handle -mserialize. * gcc/config.gcc (serializeintrin.h): New header file. * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit. * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect -mserialize. * gcc/config/i386/i386-builtin.def: Add new builtin. * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro. * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts): Add -mserialize. * (ix86_valid_target_attribute_inner_p): Add target attribute * for serialize. * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P): New macros. * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec. (serialize): New define_insn. * gcc/config/i386/i386.opt (mserialize): New option * gcc/config/i386/immintrin.h: Include serailizeintrin.h. * gcc/config/i386/serializeintrin.h: New header file. * gcc/doc/invoke.texi: Add documents for -mserialize. gcc/testsuite/Changelog * gcc/testsuite/gcc.target/i386/serialize-1.c: New test. * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize. * gcc/testsuite/g++.dg/other/i386-3.C: Ditto. * gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto. * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
2020-04-08[Arm] Implement CDE intrinsics for MVE registers.Matthew Malcomson1-1/+1
Implement CDE intrinsics on MVE registers. Other than the basics required for adding intrinsics this patch consists of three changes. ** We separate out the MVE types and casts from the arm_mve.h header. This is so that the types can be used in arm_cde.h without the need to include the entire arm_mve.h header. The only type that arm_cde.h needs is `uint8x16_t`, so this separation could be avoided by using a `typedef` in this file. Since the introduced intrinsics are all defined to act on the full range of MVE types, declaring all such types seems intuitive since it will provide their declaration to the user too. This arm_mve_types.h header not only includes the MVE types, but also the conversion intrinsics between them. Some of the conversion intrinsics are needed for arm_cde.h, but most are not. We include all conversion intrinsics to keep the definition of such conversion functions all in one place, on the understanding that extra conversion functions being defined when including `arm_cde.h` is not a problem. ** We define the TARGET_RESOLVE_OVERLOADED_BUILTIN hook for the Arm backend. This is needed to implement the polymorphism for the required intrinsics. The intrinsics have no specialised version, and the resulting assembly instruction for all different types should be exactly the same. Due to this we have implemented these intrinsics via one builtin on one type. All other calls to the intrinsic with different types are implicitly cast to the one type that is defined, and hence are all expanded to the same RTL pattern that is only defined for one machine mode. ** We seperate the initialisation of the CDE intrinsics from others. This allows us to ensure that the CDE intrinsics acting on MVE registers are only created when both CDE and MVE are available. Only initialising these builtins when both features are available is especially important since they require a type that is only initialised when the target supports hard float. Hence trying to initialise these builtins on a soft float target would cause an ICE. Testing done: Full bootstrap and regtest on arm-none-linux-gnueabihf Regression test on arm-none-eabi Ok for trunk? gcc/ChangeLog: 2020-03-10 Matthew Malcomson <matthew.malcomson@arm.com> * config.gcc (arm_mve_types.h): New extra_header for arm. * config/arm/arm-builtins.c (arm_resolve_overloaded_builtin): New. (arm_init_cde_builtins): New. (arm_init_acle_builtins): Remove initialisation of CDE builtins. (arm_init_builtins): Call arm_init_cde_builtins when target supports CDE. * config/arm/arm-c.c (arm_resolve_overloaded_builtin): New declaration. (arm_register_target_pragmas): Initialise resolve_overloaded_builtin hook to the implementation for the arm backend. * config/arm/arm.h (ARM_MVE_CDE_CONST_1): New. (ARM_MVE_CDE_CONST_2): New. (ARM_MVE_CDE_CONST_3): New. * config/arm/arm_cde.h (__arm_vcx1q_u8): New. (__arm_vcx1qa): New. (__arm_vcx2q): New. (__arm_vcx2q_u8): New. (__arm_vcx2qa): New. (__arm_vcx3q): New. (__arm_vcx3q_u8): New. (__arm_vcx3qa): New. * config/arm/arm_cde_builtins.def (vcx1q, vcx1qa, vcx2q, vcx2qa, vcx3q, vcx3qa): New builtins defined. * config/arm/arm_mve.h: Move typedefs and conversion intrinsics to arm_mve_types.h header. * config/arm/arm_mve_types.h: New file. * config/arm/mve.md (arm_vcx1qv16qi, arm_vcx1qav16qi, arm_vcx2qv16qi, arm_vcx2qav16qi, arm_vcx3qv16qi, arm_vcx3qav16qi): New patterns. * config/arm/predicates.md (const_int_mve_cde1_operand, const_int_mve_cde2_operand, const_int_mve_cde3_operand): New. gcc/testsuite/ChangeLog: 2020-03-23 Matthew Malcomson <matthew.malcomson@arm.com> Dennis Zhang <dennis.zhang@arm.com> * gcc.target/arm/acle/cde-mve-error-1.c: New test. * gcc.target/arm/acle/cde-mve-error-2.c: New test. * gcc.target/arm/acle/cde-mve-error-3.c: New test. * gcc.target/arm/acle/cde-mve-full-assembly.c: New test. * gcc.target/arm/acle/cde-mve-tests.c: New test. * lib/target-supports.exp (arm_v8_1m_main_cde_mve_fp): New check effective. (arm_v8_1m_main_cde_mve, arm_v8m_main_cde_fp): Use -mfpu=auto so we only check configurations that make sense.
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