aboutsummaryrefslogtreecommitdiff
path: root/gcc/config.gcc
AgeCommit message (Collapse)AuthorFilesLines
2008-03-03config.gcc: Add arm/t-arm-softfp and soft-fp/t-softfp to arm configs.Paul Brook1-1/+9
2008-03-03 Paul Brook <paul@codesourcery.com> gcc/ * config.gcc: Add arm/t-arm-softfp and soft-fp/t-softfp to arm configs. Add new --with-arch options. * config/arm/t-arm-softfp: New file. * config/arm/elf.h: Disable soft-fp routines on everything except ARMv6-M. * config/arm/ieee754-df.S: Rename L_* to L_arm_*. * config/arm/ieee754-sf.S: Ditto. * config/arm/t-arm-elf: Ditto. * config/arm/arm.c (FL_FOR_ARCH6M): Define. (all_architectures): Add armv6-m. (arm_output_mi_thunk): Add TARGET_THUMB1_ONLY thunks. * config/arm/lib1funcs.asm: Add __ARM_ARCH_6M__ conditionals. Include bpabi-v6m.S. * config/arm/arm.h (TARGET_THUMB1_ONLY): Define. (ARM_DECLARE_FUNCTION_NAME): Handle Thumb-1 only thunks. * config/arm/sfp-machine.h: New file. * config/arm/bpabi-v6m.S: New file. * config/arm/arm-cores.def: Add cortex-m1. * config/arm/arm-tune.md: Regenerate. * config/arm/libunwind.S: Add ARMv6-M implementation. * config/arm/bpabi.h: Add renames for soft-float routines. * doc/invoke.texi: Document -mcpu=cortex-m1 and -march=armv6-m. From-SVN: r132837
2008-02-24config.gcc (powerpc*-*-*): Add new cores e300c2 and e300c3.Edmar Wienskoski1-1/+1
2008-02-21 Edmar Wienskoski <edmar@freescale.com> * config.gcc (powerpc*-*-*): Add new cores e300c2 and e300c3. * config/rs6000/e300c2c3.md: New file. * config/rs6000/rs6000.c (processor_costs): Add new costs for e300c2 and e300c3. (rs6000_override_options): Add e300c2 and e300c3 cases to processor_target_table. Do not allow usage of Altivec or Spe with e300 cores. Initialize rs6000_cost for e300c2 and e300c3. (rs6000_issue_rate): Set issue rate for e300c2 and e300c3. * config/rs6000/rs6000.h (processor_type): Add PROCESSOR_PPCE300C2 and PROCESSOR_PPCE300C3. (ASM_CPU_SPEC): Add e300c2 and e300c3. * config/rs6000/rs6000.md (define_attr "cpu"): Add ppce300c2 and ppce300c3. Include e300c2c3.md. From-SVN: r132589
2008-01-29* config.gcc (i[34567]86-*-nto-qnx*): Remove deprecation.Joseph Myers1-1/+0
From-SVN: r131942
2008-01-27config.gcc (strongarm*-*, [...]): Mark obsolete.Joseph Myers1-0/+25
* config.gcc (strongarm*-*, ep9312*-*, xscale*-*, parisc*-*, m680[012]0-*, *-*-beos*, *-*-kaos*, *-*-linux*aout*, *-*-linux*libc1*, *-*-solaris2.[0-6], *-*-solaris2.[0-6].*, *-*-sysv*, *-*-windiss*, alpha*-*-unicosmk*, cris-*-aout, hppa1.1-*-pro*, hppa1.1-*-osf*, hppa1.1-*-bsd*, i[34567]86-sequent-ptx4*, i[34567]86-*-nto-qnx*, i[34567]86-*-sco3.2v5*, i[34567]86-*-uwin*, powerpc-*-chorusos*, vax-*-bsd*, vax-*-ultrix*): Mark obsolete. From-SVN: r131889
2008-01-26re PR target/34794 (build of gcc 4.2.2 fails on AIX 6.1 / ↵David Edelsohn1-1/+9
libstdc++-v3/libmath/stubs.c:47) PR target/34794 * config.gcc: Separate AIX 5.3 from AIX 6.1. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define __LONGDOUBLE128 too. * config/rs6000/aix61.h: New file. From-SVN: r131865
2008-01-25MAINTAINERS (c4x port): Remove.Joseph Myers1-36/+4
* MAINTAINERS (c4x port): Remove. contrib: * paranoia.cc (main): Remove handling of c4x_single and c4x_extended formats. gcc: * config/c4x: Remove directory. * config.gcc (crx-*, mt-*): Mark obsolete. (c4x-*, tic4x-*, c4x-*-rtems*, tic4x-*-rtems*, c4x-*, tic4x-*, h8300-*-rtemscoff*, ns32k-*-netbsdelf*, ns32k-*-netbsd*, sh-*-rtemscoff*): Remove cases. * defaults.h (C4X_FLOAT_FORMAT): Remove. * real.c (encode_c4x_single, decode_c4x_single, encode_c4x_extended, decode_c4x_extended, c4x_single_format, c4x_extended_format): Remove. * real.h (c4x_single_format, c4x_extended_format): Remove. * doc/extend.texi (interrupt, naked): Remove mention of attributes on C4x. (Pragmas): Remove comment about c4x pragmas. * doc/install.texi (c4x): Remove target-specific instructions. * doc/invoke.texi (TMS320C3x/C4x Options): Remove. * doc/md.texi (Machine Constraints): Remove C4x documentation. * doc/tm.texi (MEMBER_TYPE_FORCES_BLK, c_register_pragma): Do not refer to C4x source files as examples. (C4X_FLOAT_FORMAT): Remove documentation. gcc/testsuite: * gcc.dg/builtin-inf-1.c, gcc.dg/compare6.c, gcc.dg/sibcall-3.c, gcc.dg/sibcall-4.c, gcc.dg/torture/builtin-attr-1.c: Don't handle c4x-*-* targets. libgcc: * config.host (tic4x-*-*, c4x-*-rtems*, tic4x-*-rtems*, c4x-*, tic4x-*, h8300-*-rtemscoff*, ns32k-*-netbsdelf*, ns32k-*-netbsd*, sh-*-rtemscoff*): Remove cases. From-SVN: r131835
2007-12-15config.gcc: Make crisv32-* have cpu_type cris.Hans-Peter Nilsson1-1/+19
* config.gcc: Make crisv32-* have cpu_type cris. Handle crisv32-*-elf and crisv32-*-none like cris-*-elf and cris-*-none but without multilibs and with target_cpu_default=32. From-SVN: r130965
2007-11-08re PR target/16350 (gcc only understands little endian ARM systems)Bernhard Fischer1-0/+5
PR target/16350 * config.gcc: For arm*b-* define TARGET_BIG_ENDIAN_DEFAULT. * config/arm/linux-elf.h (TARGET_ENDIAN_DEFAULT): Define based on TARGET_BIG_ENDIAN_DEFAULT. Use for MULTILIB_DEFAULTS. (TARGET_DEFAULT): Set according to TARGET_ENDIAN_DEFAULT. (LINUX_TARGET_LINK_SPEC): Pass -mlittle-endian on to the assembler. * config/arm/linux-eabi.h (TARGET_LINKER_EMULATION): Set according to TARGET_BIG_ENDIAN_DEFAULT. (SUBTARGET_EXTRA_LINK_SPEC): Likewise. * gcc/config/arm/bpabi.h (TARGET_DEFAULT_MASK): Set according to TARGET_BIG_ENDIAN_DEFAULT. From-SVN: r129999
2007-11-05config.gcc (arm*-*-*): Set c_target_objs and cxx_target_objs.Paul Brook1-0/+2
2007-11-05 Paul Brook <paul@codesourcery.com> gcc/ * config.gcc (arm*-*-*): Set c_target_objs and cxx_target_objs. * config/arm/arm.c (arm_lang_output_object_attributes_hook): New. (arm_file_start): Don't set Tag_ABI_PCS_wchar_t. Call arm_lang_output_object_attributes_hook. * config/arm/arm.h (arm_lang_output_object_attributes_hook): Declare. (REGISTER_TARGET_PRAGMAS): Call arm_lang_object_attributes_init. * config/arm/arm-protos.h (arm_lang_object_attributes_init): Add prototype. * config/arm/t-arm.c (arm.o): New rule. * config/arm/arm-c.c: New file. From-SVN: r129904
2007-10-23config.gcc: For a FreeBSD target...Craig Rodrigues1-20/+2
* config.gcc: For a FreeBSD target, parse the value of ${target} to determine the value of FBSD_MAJOR, instead of adding an explicit check for every possible FreeBSD major version. From-SVN: r129590
2007-10-18Add Niagara-2 support.David S. Miller1-1/+1
2007-10-18 David S. Miller <davem@davemloft.net> Add Niagara-2 support. * doc/invoke.texi: Document -m{cpu,tune}=niagara2. * config.gcc: Add niagara2 to cpu and tune lists for sparc. * config/sparc/sparc.md (sparc_cpu_attr): Add niagara2. (include): Add inclusion of niagara2.md * config/sparc/sparc.c (niagara2_costs): New. (sparc_override_options): Add niagara2 entry to cpu_default[] and cpu_table[]. Set align_functions to 32 on Niagara2. Use niagara2_costs when PROCESSOR_NIAGARA2. Handle Niagara2 for PARAM_SIMULTANEOUS_PREFETCHES and PARAM_L1_CACHE_LINE_SIZE. (sparc_initialize_trampoline): Handle niagara2 like niagara. (sparc64_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. * config/sparc/sol2-bi.h: Handle TARGET_CPU_niagara2 and mcpu=niagara2 * config/sparc/sparc.h (TARGET_CPU_niagara2): Define. ({CPP,ASM}_CPU64_DEFAULT_SPEC): Set appropriately for TARGET_CPU_niagara2. (PROCESSOR_NIAGARA2): New. (REGISTER_MOVE_COST): Handle PROCESSOR_NIAGARA2. (BRANCH_COST): Likewise. * config/sparc/linux64.h: Handle TARGET_CPU_niagara2. * config/sparc/sol2.h: Likewise. * config/sparc/niagara2.md: New file. From-SVN: r129472
2007-10-18Because we merge score3 and score7 into the same backend,Chen Liqin1-1/+1
so make a lot of changes in the code structure. Changelog: * config.gcc : update score-*-elf(extra_objs). * config/score/mac.md : Remove. * config/score/misc.md : Remove. * config/score/score7.md : Remove. * config/score/score-mdaux.h : Remove. * config/score/score-mdaux.c : Remove. * config/score/score-version.h : Remove. * config/score/score-generic.md : New. * config/score/score3.h : New. * config/score/score3.c : New. * config/score/score7.h : New. * config/score/score7.c : New. * config/score/mul-div.S : add flush_cache score3 support. * config/score/elf.h : Fix some typos. * config/score/score.md : merge score3 and score7 pattern. * config/score/score.c : use to seperate which target it used. * config/score/score.h : use to seperate the target macro. * config/score/score.opt : remove -mmac option , add -mscore3, -mscore3d and -march OPTION support. From-SVN: r129431
2007-10-15* config.gcc (powerpc-ibm-aix5*): Install altivec.hDavid Edelsohn1-1/+1
From-SVN: r129348
2007-10-13aix53.h: New file.David Edelsohn1-1/+9
* config/rs6000/aix53.h: New file. * config/rs6000/aix{41,43,51,52}.h (TARGET_ALTIVEC): Define to 0. (TARGET_ALTIVEC_ABI): Same. * config/rs6000/aix.h (TARGET_ALTIVEC): Delete. (TARGET_ALTIVEC_ABI): Delete. * config.gcc (powerpc-ibm-aix5*): Rename to aix5.2. Add new stanza defaulting to aix5.3. From-SVN: r129285
2007-10-04* config.gcc: Remove USE_GAS for m68k targets.Kazu Hirata1-7/+7
From-SVN: r129005
2007-09-28config.gcc (bfin*-linux-uclibc*): Set extra_parts to "crtbegin.o crtbeginS.o ↵Jie Zhang1-14/+15
crtend.o crtendS.o". * config.gcc (bfin*-linux-uclibc*): Set extra_parts to "crtbegin.o crtbeginS.o crtend.o crtendS.o". * config/bfin/t-bfin-linux (crti.o): Don't build. (crtn.o): Likewise. (EXTRA_MULTILIB_PARTS): Remove crti.o and crtn.o. * config/bfin/t-bfin-uclinux (crti.o): Don't build. (crtn.o): Likewise. (EXTRA_MULTILIB_PARTS): Remove crti.o and crtn.o. From-SVN: r128860
2007-09-24config.gcc (powerpc*-*-*): --with-cpu=cell is a 64bit CPU.Andrew Pinski1-2/+2
2007-09-24 Andrew Pinski <andrew_pinski@playstation.sony.com> * config.gcc (powerpc*-*-*): --with-cpu=cell is a 64bit CPU. Allow --with-tune=cell and --with-cpu=cell. From-SVN: r128721
2007-09-19config.gcc (bfin*-linux-uclibc*): Add ./linux-sysroot-suffix.h to tm_file.Jie Zhang1-1/+1
* config.gcc (bfin*-linux-uclibc*): Add ./linux-sysroot-suffix.h to tm_file. * config/bfin/print-sysroot-suffix.sh: New. * config/bfin/t-bfin-elf (EXTRA_PARTS): Remove. (MULTILIB_OPTIONS, MULTILIB_DIRNAMES, MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Redefine with new multilibs. * config/bfin/t-bfin-uclinux (EXTRA_PARTS): Remove. (MULTILIB_OPTIONS, MULTILIB_DIRNAMES, MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Redefine with new multilibs. * config/bfin/t-bfin-linux (EXTRA_PARTS): Remove. (MULTILIB_OPTIONS, MULTILIB_DIRNAMES, MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Redefine with new multilibs. (linux-sysroot-suffix.h): New target. * config/bfin/bfin.opt (mcsync-anomaly): Use Var instead of Mask. (mspecld-anomaly): Likewise. * config/bfin/bfin-protos.h (enum bfin_cpu_type): Renamed from (enum bfin_cpu): ... this. Add BFIN_CPU_BF522, BFIN_CPU_BF525, BFIN_CPU_BF527, BFIN_CPU_BF538, BFIN_CPU_BF539, BFIN_CPU_BF542, BFIN_CPU_BF544, BFIN_CPU_BF548, and BFIN_CPU_BF549. (bfin_si_revision): Declare. (bfin_workarounds): Declare. (WA_SPECULATIVE_LOADS): Define. (ENABLE_WA_SPECULATIVE_LOADS): Define. (WA_SPECULATIVE_SYNCS): Define. (ENABLE_WA_SPECULATIVE_SYNCS): Define. * config/bfin/elf.h (STARTFILE_SPEC): Rename crt532.o to basiccrt.o. (LIB_SPEC): Add %s to the linker scripts. Use proper linker script for bf522, bf525, bf527, bf538, bf539, bf542, bf544, bf548, and bf549. * config/bfin/bfin.c (bfin_si_revision): Define. (bfin_workarounds): Define. (struct bfin_cpu): New. (bfin_cpus): New. (bfin_handle_option): Handle silicon revision part of -mcpu option. (override_options): Set bfin_workarounds. (length_for_loop): Replace TARGET_CSYNC_ANOMALY with ENABLE_WA_SPECULATIVE_SYNCS, TARGET_SPECLD_ANOMALY with ENABLE_WA_SPECULATIVE_LOADS. (bfin_reorg): Likewise. * config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define macros for bf522, bf525, bf527, bf538, bf539, bf542, bf544, bf548, and bf549. Define __SILICON_REVISION__ and __WORKAROUND_* macros if needed. Don't define __ID_SHARED_LIB__ when -msep-data. (TARGET_DEFAULT): Define as 0. (DRIVER_SELF_SPECS): Add -mcpu=bf532 if no -mcpu option. * doc/invoke.texi (Blackfin Options): Document silicon revision part of -mcpu option and it now accepts bf522, bf525, bf527, bf538, bf539, bf542, bf544, bf548, and bf549. Neither -mspecld-anomaly nor -mcsync-anomaly is enabled anymore. testsuite/ * gcc.target/bfin/bfin.exp: New. * gcc.target/bfin/{workarounds-any.c, workarounds-none.c, workarounds-1.c, workarounds-2.c, workarounds-3.c, workarounds-4.c, mcpu-bf522.c, mcpu-bf525.c, mcpu-bf527.c, mcpu-bf531.c, mcpu-bf532.c, mcpu-bf533.c, mcpu-bf534.c, mcpu-bf536.c, mcpu-bf537.c, mcpu-bf538.c, mcpu-bf539.c, mcpu-bf542.c, mcpu-bf544.c, mcpu-bf548.c, mcpu-bf549.c, mcpu-bf561.c, mcpu-default.c}: New tests. From-SVN: r128597
2007-09-14config.gcc (mips*-*-linux*): Recognise mipsisa32r2 and set MIPS_ISA_DEFAULT ↵Nigel Stephens1-3/+4
appropriately. gcc/ 2007-09-14 Nigel Stephens <nigel@mips.com> * config.gcc (mips*-*-linux*): Recognise mipsisa32r2 and set MIPS_ISA_DEFAULT appropriately. Don't make soft-float the default for mipsisa32-*-linux*. From-SVN: r128498
2007-09-14configure.ac (mips*-sde-elf*): New stanza.Richard Sandiford1-0/+16
* configure.ac (mips*-sde-elf*): New stanza. Add target-libiberty to $skipdirs and only disable gprof for newlib. Use the normal mips*-elf* handling in other respects. * configure: Regnerate. gcc/ 2007-xx-xx Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> Thiemo Seufer <ths@mips.com> Richard Sandiford <richard@codesourcery.com> * config.gcc (mips*-sde-elf*): Add support for the SDE C libraries. * configure.ac: Add a mipssde threading type. * configure: Regenerate. * config/mips/sdemtk.h: New file. * config/mips/t-sdemtk: Likewise. * config/mips/sdemtk.opt: Likewise. * gthr-mipssde.h: Likewise. * config/mips/sde.h (FUNCTION_PROFILER): Move to config/mips/sdemtk.h. * config/mips/mips.h (MIPS_SAVE_REG_FOR_PROFILING_P): New macro. (MIPS_ICACHE_SYNC): New macro, split from ... * config/mips/mips.md (clear_cache): ...here. * config/mips/mips.c (mips_save_reg_p): Check MIPS_SAVE_REG_FOR_PROFILING_P on profiled functions. (build_mips16_function_stub): Use targetm.strip_name_encoding. (build_mips16_call_stub): Likewise. libstdc++-v3/ 2007-xx-xx Thiemo Seufer <ths@mips.com> * crossconfig.m4 (mips*-sde-elf*): New stanza. * configure: Regenerate. From-SVN: r128495
2007-09-13Add AMD SSE5 support; Add iterator over function arguments; Add stdarg_p, ↵Michael Meissner1-2/+2
prototype_p, function_args_count functions From-SVN: r128455
2007-09-11invoke.texi: Document new MIPS -mllsc and -mno-llsc options.David Daney1-2/+21
* doc/invoke.texi: Document new MIPS -mllsc and -mno-llsc options. * doc/install.texi: Document new --with-llsc and --without-llsc options. * config.gcc: Handle --with-llsc and --without-llsc configure options. * config/mips/mips.md (sync, memory_barrier): Wrap sync instrunction in %| and %- operand codes. Depend on GENERATE_SYNC instead of ISA_HAS_SYNC. (sync_compare_and_swap<mode>, sync_add<mode>, sync_sub<mode>, sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>, sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>, sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>, sync_new_nand<mode>, sync_lock_test_and_set<mode>): Depend on GENERATE_LL_SC instead of ISA_HAS_LL_SC. * config/mips/mips.opt (mllsc): New option. * config/mips/mips.c (mips_llsc): Define variable. (mips_handle_option): Handle mllsc option. (override_options): Set mips_print_operand_punct for '|' and '-'. (print_operand): Add new %| and %- operand codes. * config/mips/mips.h (mips_llsc_setting): New enum type. (mips_llsc): Declare. (OPTION_DEFAULT_SPECS): Add llsc handling. (GENERATE_SYNC): New macro. (GENERATE_LL_SC): New macro. (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP, MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Wrap instructions in %| and %- operand codes. From-SVN: r128392
2007-09-06config.gcc (tm_file): Add linux.h for bfin*-uclinux*.Jie Zhang1-1/+3
* config.gcc (tm_file): Add linux.h for bfin*-uclinux*. (tm_defines): Define UCLIBC_DEFAULT to 1. (extra_options): Add linux.opt. * config/bfin/linux.h (CPLUSPLUS_CPP_SPEC): Don't define. (CRT_CALL_STATIC_FUNCTION): Likewise. (NO_IMPLICIT_EXTERN_C): Likewise. (TARGET_OS_CPP_BUILTINS): Define as LINUX_TARGET_OS_CPP_BUILTINS. * config/bfin/elf.h (OBJECT_FORMAT_ELF): Don't define. * config/bfin/uclinux.h (CPLUSPLUS_CPP_SPEC): Don't define. (ENDFILE_SPEC): Don't define. (LIB_SPEC): Likewise. (CRT_CALL_STATIC_FUNCTION): Likewise. (NO_IMPLICIT_EXTERN_C): Likewise. (LINUX_TARGET_OS_CPP_BUILTINS): Likewise. (TARGET_OS_CPP_BUILTINS): Define as LINUX_TARGET_OS_CPP_BUILTINS. From-SVN: r128163
2007-09-05cpuid.h: New file.Uros Bizjak1-2/+2
* gcc/config/i386/cpuid.h: New file. * gcc/config/i386/driver-i386.c: Include cpuid.h. (describe_cache): Shrink size and line strings to 100 bytes. (detect_caches_amd): Return "" for unsupported max_ext_level. Use __cpuid function. (detect_caches_intel): Return "" for unsupported max_level. Use __cpuid function. (host_detect_local_cpu): Change feature flag variables to unsigned int. Initialize only extended feature flag variables. Use __get_cpuid_max to determine max supported cpuid level. Use __cpuid function to determine supported features. Fix calculation of family id. Remove is_amd and check signature directly. Check for Geode signature. Handle family 4 id. [PROCESSOR_GENERIC32]: New default for unknown family id. Move cpu discovery code to other part of the function. [PROCESSOR_PENTIUM, PROCESSOR_K6, PROCESSOR_ATHLON]: Do not tune for sub-architecture. [PROCESSOR_PENTIUMPRO]: Simplify cpu discovery code. [PROCESSOR_K8]: Add k8-sse3 architecture. [PROCESSOR_GENERIC64]: Remove. * gcc/config/i386/x-i386 (driver-i386.o): Depend on cpuid.h. * gcc/config/i386/crtfastmath.c: Include cpuid.h. Use __get_cpuid to check for SSE and FXSAVE support. * gcc/config/i386/t-crtfm (crtfastmath.o): Depend on cpuid.h. Add -minline-all-stringops. * gcc/config.gcc (i[34567]86-*-*): Add cpuid.h to extra_headers. (x86_64-*-*): Ditto. testsuite/ChangeLog: * gcc.dg/i386-cpuid.h: Remove. * gcc.target/i386/mmx-check.h: Include cpuid.h. Use __get_cpuid. * gcc.target/i386/sse-check.h: Ditto. * gcc.target/i386/sse2-check.h: Ditto. * gcc.target/i386/sse3-check.h: Ditto. * gcc.target/i386/ssse3-check.h: Ditto. * gcc.target/i386/sse4_1-check.h: Ditto. * gcc.target/i386/sse4_2-check.h: Ditto. * gcc.target/i386/sse4a-check.h: Ditto. * gcc.dg/torture/pr16104-1.c: Ditto. * gcc.target/i386/mmx-4.c: Do not use NOINLINE. * gcc.target/i386/sse-6.c: Ditto. * gcc.target/i386/sse-7.c: Ditto. * g++.dg/other/i386-1.C: Include cpuid.h. (main): New function. Use __get_cpuid to check target fetaures. libgomp/ChangeLog: * testsuite/libgomp.c/atomic-1.c: Include cpuid.h for i386 targets. (main): Use __get_cpuid to get i386 target fetaures. * testsuite/libgomp.c/atomic-2.c: Include cpuid.h for x86_64 targets. (main): Use __get_cpuid to get x86_64 target fetaures. From-SVN: r128141
2007-09-04config.gcc (powerpc*-*-*): Install spu2vmx.h, vec_types.h, and si2vmx.h headers.Andrew Pinski1-1/+1
2007-09-04 Andrew Pinski <andrew_pinski@playstation.sony.com> * config.gcc (powerpc*-*-*): Install spu2vmx.h, vec_types.h, and si2vmx.h headers. * config/rs6000/spu2vmx.h: New header. * config/rs6000/si2vmx.h: New header. * config/rs6000/vec_types.h: New header. 2007-09-04 Andrew Pinski <andrew_pinski@playstation.sony.com> * g++.dg/other/spu2vmx-1.C: New test. From-SVN: r128118
2007-09-03config.gcc: Delete stanza for arm-semi-aof and armel-semi-aof targets.Zack Weinberg1-4/+0
* config.gcc: Delete stanza for arm-semi-aof and armel-semi-aof targets. * config/arm/arm-protos.h * config/arm/arm.c * config/arm/arm.h: Delete all #ifdef AOF_ASSEMBLER blocks; make all #ifndef AOF_ASSEMBLER blocks unconditional. Also delete aof_pic_label and remove mention of AOF in comments. * config/arm/arm.md: Delete patterns used only for AOF assembly. * config/arm/aof.h * config/arm/semiaof.h * config/arm/t-semi: Delete file. From-SVN: r128052
2007-08-31Support for PowerPC 750CL paired-single instructions David Edelsohn1-1/+6
Co-Authored-By: Revital Eres <eres@il.ibm.com> From-SVN: r127954
2007-08-30ppu_intrinsics.h: New file.Andrew Pinski1-1/+1
2007-08-30 Andrew Pinski <andrew_pinski@playstation.sony.com> * config/rs6000/ppu_intrinsics.h: New file. * config.gcc (powerpc*-*-* <extra_headers>): Install ppu_intrinsics.h. 2007-08-30 Andrew Pinski <andrew_pinski@playstation.sony.com> * gcc.target/powerpc/ppu-intrinsics.c: New testcase. From-SVN: r127934
2007-08-25config.gcc: Add x86_64-elf target.Hans Kester1-0/+5
* config.gcc : Add x86_64-elf target. From-SVN: r127798
2007-08-06re PR target/31868 (Non-Linux DWARF EH x86-64 targets have broken crtend.o)H.J. Lu1-2/+4
2007-08-06 H.J. Lu <hongjiu.lu@intel.com> Daniel Jacobowitz <dan@codesourcery.com> PR target/31868 * config.gcc (x86_64-*-freebsd*): Add i386/t-crtstuff to tmake_file. (x86_64-*-netbsd*): Likewise. (x86_64-*-linux*): Likewise. (x86_64-*-kfreebsd*-gnu): Likewise. (x86_64-*-knetbsd*-gnu): Likewise. (i[34567]86-*-solaris2.1[0-9]*): Likewise. * config/i386/t-linux64 (CRTSTUFF_T_CFLAGS): Removed. * config/i386/t-crtstuff (CRTSTUFF_T_CFLAGS): Update comments. Add -fno-asynchronous-unwind-tables. * config/t-freebsd (CRTSTUFF_T_CFLAGS_S): Add $(CRTSTUFF_T_CFLAGS). * config/t-libc-ok (CRTSTUFF_T_CFLAGS_S): Likewise. * config/t-lynx (CRTSTUFF_T_CFLAGS_S): Likewise. * config/t-netbsd (CRTSTUFF_T_CFLAGS_S): Likewise. * config/t-svr4 (CRTSTUFF_T_CFLAGS_S): Likewise. Co-Authored-By: Daniel Jacobowitz <dan@codesourcery.com> From-SVN: r127248
2007-08-012007-xx-xx Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> Thiemo...Nigel Stephens1-8/+23
gcc/ 2007-xx-xx Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> Thiemo Seufer <ths@mips.com> Chris Dearman <chris@mips.com> Richard Sandiford <richard@codesourcery.com> * config.gcc (mips*-sde-elf*): New stanza. (mipsisa32-*-elf*, mipsisa32el-*-elf*, mipsisa32r2-*-elf*) (mipsisa32r2el-*-elf*, mipsisa64-*-elf*, mipsisa64el-*-elf*) (mipsisa64sb1-*-elf*, mipsisa64sb1el-*-elf*, mips-*-elf*) (mipsel-*-elf*, mips64-*-elf*, mips64el-*-elf*, mips64orion-*-elf*) (mips64orionel-*-elf*, mips*-*-rtems*, mips-wrs-windiss) (mipstx39-*-elf*, mipstx39el-*-elf*): Add mips/t-libgcc-mips16 to tmake_file. * config/mips/sde.h: New file. * config/mips/t-libgcc-mips16: Likewise. * config/mips/t-sde: Likewise. * config/mips/linux.h (TARGET_OS_CPP_BUILTINS): Remove settings of _ABIN32, _ABI64, _ABIO32, _MIPS_SIM, _MIPS_SZLONG, _MIPS_SZPTR, _MIPS_FPSET and _MIPS_SZINT. * config/mips/iris.h (TARGET_OS_CPP_BUILTINS): Likewise. * config/mips/elfoabi.h (DRIVER_SELF_SPECS): Remove separate insertion of a default -mips option. Use MIPS_32BIT_OPTION_SPEC. * config/mips/t-isa3264 (LIB1ASMSRC, LIB1ASMFUNCS): Delete. * config/mips/t-r3900 (LIB1ASMSRC, LIB1ASMFUNCS): Likewise. * config/mips/t-elf (LIB1ASMSRC, LIB1ASMFUNCS): Likewise. * config/mips/mips.h (TARGET_CPU_CPP_BUITINS): Define _ABIO32, _ABIN32, _ABI64, _ABIO64, _MIPS_SIM, _MIPS_SZINT, _MIPS_SZLONG, _MIPS_SZPTR and _MIPS_FPSET. (MIPS_ISA_LEVEL_SPEC): Inject the default -mips option if no architecture is specified. (MIPS_32BIT_OPTION_SPEC): New macro. Co-Authored-By: Chris Dearman <chris@mips.com> Co-Authored-By: David Ung <davidu@mips.com> Co-Authored-By: Richard Sandiford <richard@codesourcery.com> Co-Authored-By: Thiemo Seufer <ths@mips.com> From-SVN: r127113
2007-07-26Change copyright header to refer to version 3 of the GNU General Public ↵Nick Clifton1-4/+3
License and to point readers at the COPYING3 file and the FSF's license web page. From-SVN: r126948
2007-07-25Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.Julian Brown1-2/+2
gcc/ * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi. * config.gcc (arm*-*-*): Add arm_neon.h to extra headers. (with_fpu): Allow --with-fpu=neon. * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/arm-modes.def (EI, OI, CI, XI): New modes. * config/arm/arm-protos.h (neon_immediate_valid_for_move) (neon_immediate_valid_for_logic, neon_output_logic_immediate) (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret) (neon_emit_pair_result_insn, neon_disambiguate_copy) (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad) (output_move_neon): Add prototypes. * config/arm/arm.c (FL_NEON): New flag for NEON processor capability. (all_fpus): Add FPUTYPE_NEON. (fp_model_for_fpu): Add NEON field. (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers. (arm_arg_partial_bytes): Allow NEON vectors to be passed partially in registers. (arm_legitimate_address_p): Don't support fancy addressing for NEON structure moves. (thumb2_legitimate_address_p): Likewise. (neon_valid_immediate): Recognize and prepare constants suitable for NEON instructions. (neon_immediate_valid_for_move): New function. Recognize and prepare immediates for NEON move instructions. (neon_immediate_valid_for_logic): New function. Recognize and prepare immediates for NEON logic instructions. (neon_output_logic_immediate): New function. Create asm string suitable for outputting immediate logic instructions. (neon_pairwise_reduce): New function. Implement reduction using pairwise operations. (neon_expand_vector_init): New function. Expand a (possibly non-constant) vector initialization. (neon_vector_mem_operand): New function. Memory operands supported for quad-word loads/stores to/from ARM or NEON registers. Don't allow base+offset addressing for core regs. (neon_struct_mem_operand): New function. Valid mems for NEON structure moves. (coproc_secondary_reload_class): Enable NEON registers to be loaded from neon_vector_mem_operand addresses without a secondary register. (add_minipool_forward_ref): Handle >8-byte minipool entries. (add_minipool_backward_ref): Likewise. (dump_minipool): Likewise. (push_minipool_fix): Likewise. (output_move_quad): New function. Output quad-word moves, loads and stores using ARM registers. (output_move_vfp): Add support for vectors in VFP (NEON) D registers. (output_move_neon): Output a NEON load/store to/from a quadword register. (arm_print_operand): Implement new codes: - 'c' for unadorned integers (without a # sign). - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian mode. - 'e', 'f' for the low and high D parts of a NEON Q register. - 'q' outputs a NEON Q register. - 'h' outputs ranges of D registers for VLDM/VSTM etc. - 'T' prints NEON opcode features from a coded bitmask. - 'F' is similar to T, but signed/unsigned codes both print as 'i'. - 't' is similar to T, but 'u' is printed instead of 'p'. - 'O' prints 'r' if NEON instruction should perform rounding (as specified by bitmask), else prints nothing. - '#' is a punctuation character to stop operand numbers from running together with following digits in the assembler strings for instructions (when using mode attributes). (arm_assemble_integer): Handle extra NEON vector modes. Permute constant vectors in big-endian mode, where necessary. (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers. Handle EI, OI, CI, XI modes. (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3) (ashrv2si3): Rename IWMMXT2_BUILTINs to... (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt) (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names. (neon_builtin_type_bits): Add enumeration, one bit for each vector type. (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP) (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros to turn v8qi, etc. into bits defined above. (neon_itype): New enumeration. Classifications of NEON builtins. (neon_builtin_datum): Define struct. Contains information about a single builtin (with multiple modes). (CF): Define helper macro for... (VAR1...VAR10): Define builtins with a type, name and 1-10 different modes. (neon_builtin_data): New array. Define information about builtins for use during initialization/expansion. (arm_init_neon_builtins): New function. (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is true. (neon_builtin_compare): New function. (locate_neon_builtin_icode): New function. Find an insn code for a builtin given a function code for that builtin. Also return type of builtin (NEON_BINOP, NEON_UNOP etc.). (builtin_arg): New enumeration. Types of arguments for builtins. (arm_expand_neon_args): New function. Expand a generic NEON builtin. Takes a variable argument list of builtin_arg types, terminated by NEON_ARG_STOP. (arm_expand_neon_builtin): New function. Expand a NEON builtin. (neon_reinterpret): New function. Expand NEON reinterpret intrinsic. (neon_emit_pair_result_insn): New function. Support returning pairs of vectors via a pointer. (neon_disambiguate_copy): New function. Set up operands for a multi-word copy such that registers do not get clobbered. (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >= ARM_BUILTIN_NEON_BASE. (arm_file_start): Set float-abi attribute for NEON. (arm_vector_mode_supported_p): Enable NEON vector modes. (arm_mangle_map_entry): New. (arm_mangle_map): New. (arm_mangle_vector_type): New. * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__ when appropriate. (TARGET_NEON): New macro. Target supports NEON. (fputype): Add FPUTYPE_NEON. (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used for vectorization based on command-line arg. (NEON_REGNO_OK_FOR_NREGS): Define. (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE) (VALID_NEON_STRUCT_MODE): Define. (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation. (arm_builtins): Add ARM_BUILTIN_NEON_BASE. * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec. (consttable_16): Add pattern for outputting 16-byte minipool entries. (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in vec-common.md). (vec-common.md, neon.md): Include md files. * config/arm/arm.opt (mvectorize-with-neon-quad): Add option. * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define. (memory_constraint "Ut", "Un", "Us"): Define. * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros. (MMX_char): New mode attribute. (addv8qi3, addv4hi3, addv2si3): Remove. Replace with... (*add<mode>3_iwmmxt): New insn pattern. (subv8qi3, subv4hi3, subv2si3): Remove. Replace with... (*sub<mode>3_iwmmxt): New insn pattern. (mulv4hi3): Rename to... (*mulv4hi3_iwmmxt): This. (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3) (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3) (uminv4hi3, uminv2si3): Remove. Replace with... (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt) (*umin<mode>3_iwmmxt): These. (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with... (ashr<mode>3_iwmmxt): This new pattern. (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with... (lshr<mode>3_iwmmxt): This new pattern. (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with... (ashl<mode>3_iwmmxt): This new pattern. * config/arm/neon-docgen.ml: New file. Generate documentation for intrinsics. * config/arm/neon-gen.ml: New file. Generate arm_neon.h header. * config/arm/arm_neon.h: New (autogenerated). * config/arm/neon-testgen.ml: New file. Generate NEON tests automatically. * config/arm/neon.md: New file. Define NEON instructions. * config/arm/neon.ml: New file. Abstract description of NEON instructions, used to generate arm_neon.h header, documentation and tests. * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md. * vec-common.md: New file. Shared parts for iWMMXt and NEON vector support. * doc/extend.texi (ARM Built-in Functions): Rename and remove extraneous comma. (ARM NEON Intrinsics): New subsection. * doc/arm-neon-intrinsics.texi: New (autogenerated). gcc/testsuite/ * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw. * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support. * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment. * lib/target-supports.exp (check_effective_target_arm_neon_ok) (check_effective_target_arm_neon_hw): New. * gcc.target/arm/neon/neon.exp: New file. * gcc.target/arm/neon/polytypes.c: New file. * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated). Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com> Co-Authored-By: Paul Brook <paul@codesourcery.com> From-SVN: r126911
2007-07-16re PR bootstrap/3456 (bootstrapping gcc-3.0 with threadmodel=posix fails on ↵Rainer Orth1-3/+3
IRIX64 6.5) gcc: PR bootstrap/3456 * config.gcc (mips-sgi-irix[56]*): Enable pthread support. * doc/install.texi (mips-sgi-irix6): pthread support works now. libstdc++-v3: PR bootstrap/3456 * testsuite/22_locale/locale/cons/12658_thread-1.cc: Enable on mips-sgi-irix6*. * testsuite/22_locale/locale/cons/12658_thread-2.cc: Likewise. * testsuite/thread/18185.cc: Likewise. * testsuite/thread/pthread1.cc: Likewise. * testsuite/thread/pthread2.cc: Likewise. * testsuite/thread/pthread3.cc: Likewise. * testsuite/thread/pthread4.cc: Likewise. * testsuite/thread/pthread5.cc: Likewise. * testsuite/thread/pthread6.cc: Likewise. * testsuite/thread/pthread7-rope.cc: Likewise. * testsuite/tr1/2_general_utilities/shared_ptr/thread/default_weaktoshared.cc: Likewise. * testsuite/tr1/2_general_utilities/shared_ptr/thread/mutex_weaktoshared.cc: Likewise. From-SVN: r126685
2007-07-13config.gcc: Add options for arch and tune on SPU.Sa Liu1-0/+17
2007-07-13 Sa Liu <saliu@de.ibm.com> * config.gcc: Add options for arch and tune on SPU. * config/spu/predicates.md: Add constant operands 0 and 1. * config/spu/spu-builtins.def: Add builtins for double precision floating point comparison: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1, spu_testsv. * config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with a CELLEDP target. * config/spu/spu-protos.h: Add new function prototypes. * config/spu/spu.c (spu_override_options): Check options -march and -mtune. (spu_comp_icode): Add comparison code for DFmode and vector mode. (spu_emit_branch_or_set): Use the new code for DFmode and vector mode comparison. (spu_const_from_int): New. Create a vector constant from 4 ints. (get_vec_cmp_insn): New. Get insn index of vector compare instruction. (spu_emit_vector_compare): New. Emit vector compare. (spu_emit_vector_cond_expr): New. Emit vector conditional expression. * config/spu/spu.h: Add options -march and -mtune. Define processor types PROCESSOR_CELL and PROCESSOR_CELLEDP. Define macro CANONICALIZE_COMPARISON. * config/spu/spu.md: Add new insns for double precision compare and double precision vector compare. Add vcond and smax/smin patterns to enable DFmode vector conditional expression. * config/spu/spu.opt: Add options -march and -mtune. * config/spu/spu_internals.h: Add builtins for CELLEDP target: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv. Add builtin for both CELL and CELLEDP targets: spu_testsv. * config/spu/spu_intrinsics.h: Add flag mnemonics for test special values. testsuite/ * gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test for V2DFmode vector conditional expression. * gcc.target/spu/dfcmeq.c: New. Test combination of abs and dfceq patterns. * gcc.target/spu/dfcmgt.c: New. Test combination of abs and dfcgt patterns. * gcc.target/spu/intrinsics-2.c: New. Test intrinsics for V2DFmode comparison and test special values. * lib/target-supports.exp: Switch on test for V2DFmode vector conditional expression. From-SVN: r126626
2007-07-13Index: gcc/ChangeLogGeoffrey Keating1-0/+6
2007-07-12 Geoffrey Keating <geoffk@apple.com> * ginclude/tgmath.h: New. * config.gcc: Use GCC's tgmath.h on non-glibc systems. * doc/sourcebuild.texi (Headers): Document use_gcc_tgmath. * configure.ac (STMP_FIXPROTO): Honor use_gcc_tgmath. * configure: Regenerate. Index: gcc/testsuite/ChangeLog 2007-07-11 Geoffrey Keating <geoffk@apple.com> * gcc.dg/c99-tgmath-1.c: New. * gcc.dg/c99-tgmath-2.c: New. * gcc.dg/c99-tgmath-3.c: New. * gcc.dg/c99-tgmath-4.c: New. From-SVN: r126613
2007-07-04config.gcc (arm-wrs-vxworks): Don't include svr4.h.Richard Sandiford1-1/+1
gcc/ * config.gcc (arm-wrs-vxworks): Don't include svr4.h. * config/vxworks.h (PTRDIFF_TYPE, SIZE_TYPE, TARGET_POSIX_IO): Define. * config/arm/vxworks.h (ASM_SPEC): Delete. (SUBTARGET_EXTRA_ASM_SPEC): Define. From-SVN: r126310
2007-07-03config.gcc (with_fpu): Allow --with-fpu=vfp3.Julian Brown1-1/+1
gcc/ * config.gcc (with_fpu): Allow --with-fpu=vfp3. * config/arm/aout.h (REGISTER_NAMES): Add D16-D31. * config/arm/aof.h (REGISTER_NAMES): Add D16-D31. * config/arm/arm.c (FL_VFPV3): New flag for VFPv3 processor capability. (all_fpus): Add FPUTYPE_VFP3. (fp_model_for_fpu): Add VFPv3 field. (arm_rtx_costs_1): Give cost to VFPv3 constants. (vfp3_const_double_index): New function. Return integer index of VFPv3 constant suitable for fconst[sd] insns, or -1 if constant isn't suitable. (vfp3_const_double_rtx): New function. True if VFPv3 is enabled and argument represents a valid RTX for a VFPv3 constant. (vfp_output_fldmd): Split fldmd with > 16 registers in the list into two instructions. (vfp_emit_fstmd): Similar, for fstmd. (arm_print_operand): Implement new code 'G' for VFPv3 floating-point constants, represented as integer indices. (arm_hard_regno_mode_ok): Use VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_DOUBLE macros. (arm_regno_class): Handle VFPv3 d0-d7, low, high register split. (arm_file_start): Set float-abi attribute for VFPv3, and output correct ".fpu" assembler directive. (arm_dbx_register_numbering): Add FIXME. * config/arm/arm.h (TARGET_VFP3): New macro. Target supports VFPv3. (fputype): Add FPUTYPE_VFP3. (FIXED_REGISTERS): Add 32 registers for D16-D31. (CALL_USED_REGISTERS): Likewise. (CONDITIONAL_REGISTER_USAGE): Add note about conditional definition of LAST_VFP_REGNUM. Make D16-D31 caller-saved, if present. (LAST_VFP_REGNUM): Extend available VFP registers for VFPv3. (D7_VFP_REGNUM): New. (LAST_LO_VFP_REGNUM, FIRST_HI_VFP_REGNUM, LAST_HI_VFP_REGNUM) (VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_SINGLE) (VFP_REGNO_OK_FOR_DOUBLE): Define new macros. (FIRST_PSEUDO_REGISTER): Shift up to 128 to accommodate VFPv3. (REG_ALLOC_ORDER): Adjust for VFPv3. (reg_class): Add VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_NAMES): Add entries corresponding to VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_CONTENTS): Likewise. Extend contents for VFP_REGS. (IS_VFP_CLASS): Define macro. (SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Use IS_VFP_CLASS. (REGISTER_MOVE_COST): Likewise. * config/arm/arm-protos.h (vfp3_const_double_rtx): Add prototype. * config/arm/vfp.md (VFPCC_REGNUM): Redefine as 127. (*arm_movsi_vfp, *thumb2_movsi_vfp, *movsfcc_vfp) (*thumb2_movsfcc_vfp, *abssf2_vfp, *negsf2_vfp, *addsf3_vfp) (*subsf3_vfp, *divsf_vfp, *mulsf_vfp, *mulsf3negsf_vfp) (*mulsf3addsf_vfp, *mulsf3subsf_vfp, *mulsf3negsfaddsf_vfp) (*extendsfdf2_vfp, *truncdfsf2_vfp, *truncsisf2_vfp) (*truncsidf2_vfp, fixuns_truncsfsi2, fixuns_truncdfsi2) (*floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2) (floatunssidf2, *sqrtsf2_vfp, *cmpsf_split_vfp) (*cmpsf_trap_split_vfp, *cmpsf_vfp, *cmpsf_trap_vfp): Use 't' where appropriate for single-word registers. (*movsf_vfp, *thumb2_movsf_vfp, *movdf_vfp, *thumb2_movdf_vfp): As above. Fix type attributes. * config/arm/constraints.md (register_contraint "t"): Define. (register_constraint "w"): Change to D0-D15, or D0-D31 for VFPv3/NEON. (register_constraint "x"): Define. (constraint "Dv"): Define. From-SVN: r126272
2007-07-02gcc/Richard Sandiford1-15/+26
* config.gcc (mipsisa32-*-elf*, mipsisa32el-*-elf*) (mipsisa32r2-*-elf*, mipsisa32r2el-*-elf*) (mipsisa64-*-elf*, mipsisa64el-*-elf*): Combine top-level stanzas. Use the first part of the triplet to set MIPS_ISA_DEFAULT. Remove redundant setting of MASK_FLOAT64 and MASK_64BIT for the 64-bit targets. Add support for *-elfoabi*. * config/mips/t-isa3264 (MULTILIB_OPTIONS, MULTILIB_DIRNAMES): Use different settings if $(tm_defines) does not select the EABI. (MULTILIB_EXCLUSIONS): Define in those circumstances. * config/mips/mips.h (MIPS_ISA_LEVEL_OPTION_SPEC): New macro. (MIPS_ARCH_OPTION_SPEC): Likewise. (MIPS_ISA_LEVEL_SPEC): Likewise. (OPTION_DEFAULT_SPECS): Use MIPS_ARCH_OPTION_SPEC. * config/mips/elfoabi.h: New file. From-SVN: r126195
2007-06-16config.gcc (i?86-*-darwin*): Add t-crtfm and t-crtpc.Eric Christopher1-2/+2
2007-06-15 Eric Christopher <echristo@apple.com> * config.gcc (i?86-*-darwin*): Add t-crtfm and t-crtpc. (x86_64-*-darwin*): Ditto. * config/i386/darwin.h (CRTEND_SPEC): New. Add support for above. From-SVN: r125754
2007-06-07Index: ChangeLogGeoffrey Keating1-0/+1
2007-06-06 Geoffrey Keating <geoffk@apple.com> Hui-May Chang <hm.chang@apple.com> * doc/invoke.texi (Darwin Options): Update documentation for -mmacosx-version-min. * config.gcc (*-*-darwin*): Set extra_gcc_objs. * config/darwin-driver.c: New file. * config/darwin.h (GCC_DRIVER_HOST_INITIALIZATION): New. * config/t-darwin (darwin-driver.o): New rule. * config/darwin-c.c (version_as_macro): Ignore low digit. Index: testsuite/ChangeLog 2007-06-06 Geoffrey Keating <geoffk@apple.com> * gcc.dg/darwin-minversion-3.c: New. Co-Authored-By: Hui-May Chang <hm.chang@apple.com> From-SVN: r125537
2007-06-06config.gcc (i?86-*-darwin*): Remove arch parameter.Eric Christopher1-2/+0
2007-06-06 Eric Christopher <echristo@apple.com> * config.gcc (i?86-*-darwin*): Remove arch parameter. (x86_64-*-darwin*): Ditto. * config/i386/darwin.h (TARGET_SUBTARGET32_ISA_DEFAULT): Define. (TARGET_SUBTARGET64_ISA_DEFAULT): Ditto. From-SVN: r125508
2007-05-31config.gcc (i[34567]86-*-*): Add nmmintrin.h to extra_headers.H.J. Lu1-2/+4
2007-05-31 H.J. Lu <hongjiu.lu@intel.com> * config.gcc (i[34567]86-*-*): Add nmmintrin.h to extra_headers. (x86_64-*-*): Likewise. * config/i386/i386.c (OPTION_MASK_ISA_MMX_UNSET): New. (OPTION_MASK_ISA_3DNOW_UNSET): Likewise. (OPTION_MASK_ISA_SSE_UNSET): Likewise. (OPTION_MASK_ISA_SSE2_UNSET): Likewise. (OPTION_MASK_ISA_SSE3_UNSET): Likewise. (OPTION_MASK_ISA_SSSE3_UNSET): Likewise. (OPTION_MASK_ISA_SSE4_1_UNSET): Likewise. (OPTION_MASK_ISA_SSE4_2_UNSET): Likewise. (OPTION_MASK_ISA_SSE4): Likewise. (OPTION_MASK_ISA_SSE4_UNSET): Likewise. (OPTION_MASK_ISA_SSE4A_UNSET): Likewise. (ix86_handle_option): Use OPTION_MASK_ISA_*_UNSET. Handle SSE4.2. (override_options): Support SSE4.2. (ix86_build_const_vector): Support SImode and DImode. (ix86_build_signbit_mask): Likewise. (ix86_expand_int_vcond): Support V2DImode. (IX86_BUILTIN_CRC32QI): New for SSE4.2. (IX86_BUILTIN_CRC32HI): Likewise. (IX86_BUILTIN_CRC32SI): Likewise. (IX86_BUILTIN_CRC32DI): Likewise. (IX86_BUILTIN_PCMPGTQ): Likewise. (bdesc_crc32): Likewise. (bdesc_sse_3arg): Likewise. (ix86_expand_crc32): Likewise. (ix86_init_mmx_sse_builtins): Support SSE4.2. (ix86_expand_builtin): Likewise. * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Define __SSE4_2__ for -msse4.2. * config/i386/i386.md (UNSPEC_CRC32): New for SSE4.2. (CRC32MODE): Likewise. (crc32modesuffix): Likewise. (crc32modeconstraint): Likewise. (sse4_2_crc32<mode>): Likewise. (sse4_2_crc32di): Likewise. * config/i386/i386.opt (msse4.2): New for SSE4.2. (msse4): Likewise. * config/i386/nmmintrin.h: New. The dummy SSE4.2 intrinsic header file. * config/i386/smmintrin.h: Add SSE4.2 intrinsics. * config/i386/sse.md (sse4_2_gtv2di3): New pattern for SSE4.2. (vcond<mode>): Use SSEMODEI instead of SSEMODE124. (vcondu<mode>): Likewise. * doc/extend.texi: Document SSE4.2 built-in functions. * doc/invoke.texi: Document -msse4.2/-msse4. From-SVN: r125236
2007-05-30config.gcc (arm-wrs-vxworks): Remove dbxelf.h from tm_file.Richard Sandiford1-1/+1
gcc/ * config.gcc (arm-wrs-vxworks): Remove dbxelf.h from tm_file. Add vx-common.h. Include vxworks.h between vx-common.h and arm/vxworks.h. * config/vx-common.h (DWARF2_UNWIND_INFO): Undefine before redefining. * config/vxworks.h (TARGET_ASM_CONSTRUCTOR): Likewise. (TARGET_ASM_DESTRUCTOR): Likewise. * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Check arm_arch_xscale instead of arm_is_xscale. Use VXWORKS_OS_CPP_BUILTINS. (OVERRIDE_OPTIONS, SUBTARGET_CPP_SPEC): Define. (CC1_SPEC): Add -tstrongarm. Line up backslashes. (VXWORKS_ENDIAN_SPEC): Define. (ASM_SPEC): Add VXWORKS_ENDIAN_SPEC. (LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Redefine to their VXWORKS_* equivalents. (LINK_SPEC): Likewise, but add VXWORKS_ENDIAN_SPEC. (ASM_FILE_START): Delete. (TARGET_VERSION): Reformat. (FPUTYPE_DEFAULT, FUNCTION_PROFILER): Define. (DEFAULT_STRUCTURE_SIZE_BOUNDARY): Define. * config/arm/t-vxworks (LIB1ASMSRC, LIB1ASMFUNCS): Define. (FPBIT, DPBIT): Define. (fp-bit.c, dp-bit.c): New rules. (MULTILIB_OPTIONS): Add strongarm, -mrtp and -mrtp/-fPIC multilibs. (MULTILIB_MATCHES, MULTILIB_EXCEPTIONS): Define. * config/arm/arm-protos.h (arm_emit_call_insn): Declare. * config/arm/arm.h: Include vxworks-dummy.h. * config/arm/arm.c (arm_elf_asm_constructor, arm_elf_asm_destructor): Mark with ATTRIBUTE_UNUSED. (arm_override_options): Do not allow VxWorks RTP PIC to be used for Thumb. Force r9 to be the PIC register for VxWorks RTPs and make it incompatible with -msingle-pic-base. (arm_function_ok_for_sibcall): Return false for calls that might go through a VxWorks PIC PLT entry. (require_pic_register): New function, split out from... (legitimize_pic_address): ...here. Do not use GOTOFF accesses for VxWorks RTPs. (arm_load_pic_register): Handle the VxWorks RTP initialization sequence. Use pic_reg as a shorthand for cfun->machine->pic_reg. (arm_emit_call_insn): New function. (arm_assemble_integer): Do not use GOTOFF accesses for VxWorks RTP. * config/arm/arm.md (UNSPEC_PIC_OFFSET): New unspec number. (pic_offset_arm): New pattern. (call, call_value): Use arm_emit_call_insn. (call_internal, call_value_internal): New expanders. * config/arm/lib1funcs.asm (__PLT__): Define to empty for VxWorks unless __PIC__. From-SVN: r125196
2007-05-26config.gcc: Add i386/t-fprules-softfp64 and soft-fp/t-softfp to x86-darwin ↵Eric Christopher1-1/+2
configurations. 2007-05-25 Eric Christopher <echristo@apple.com> * config.gcc: Add i386/t-fprules-softfp64 and soft-fp/t-softfp to x86-darwin configurations. * config/i386/t-darwin: Add softfp support. * config/i386/t-darwin64: Ditto. * config/i386/sfp-machine.h: If mach then don't use aliasing, emit a stub to call. From-SVN: r125085
2007-05-22config.gcc (i[34567]86-*-*): Add smmintrin.h to extra_headers.H.J. Lu1-2/+2
2007-05-22 H.J. Lu <hongjiu.lu@intel.com> Richard Henderson <rth@redhat.com> * config.gcc (i[34567]86-*-*): Add smmintrin.h to extra_headers. (x86_64-*-*): Likewise. * i386/i386-modes.def (V2QI): New. * config/i386/i386.c (ix86_handle_option): Handle SSE4.1 and SSE4A. (override_options): Support SSE4.1. (IX86_BUILTIN_BLENDPD): New for SSE4.1. (IX86_BUILTIN_BLENDPS): Likewise. (IX86_BUILTIN_BLENDVPD): Likewise. (IX86_BUILTIN_BLENDVPS): Likewise. (IX86_BUILTIN_PBLENDVB128): Likewise. (IX86_BUILTIN_PBLENDW128): Likewise. (IX86_BUILTIN_DPPD): Likewise. (IX86_BUILTIN_DPPS): Likewise. (IX86_BUILTIN_INSERTPS128): Likewise. (IX86_BUILTIN_MOVNTDQA): Likewise. (IX86_BUILTIN_MPSADBW128): Likewise. (IX86_BUILTIN_PACKUSDW128): Likewise. (IX86_BUILTIN_PCMPEQQ): Likewise. (IX86_BUILTIN_PHMINPOSUW128): Likewise. (IX86_BUILTIN_PMAXSB128): Likewise. (IX86_BUILTIN_PMAXSD128): Likewise. (IX86_BUILTIN_PMAXUD128): Likewise. (IX86_BUILTIN_PMAXUW128): Likewise. (IX86_BUILTIN_PMINSB128): Likewise. (IX86_BUILTIN_PMINSD128): Likewise. (IX86_BUILTIN_PMINUD128): Likewise. (IX86_BUILTIN_PMINUW128): Likewise. (IX86_BUILTIN_PMOVSXBW128): Likewise. (IX86_BUILTIN_PMOVSXBD128): Likewise. (IX86_BUILTIN_PMOVSXBQ128): Likewise. (IX86_BUILTIN_PMOVSXWD128): Likewise. (IX86_BUILTIN_PMOVSXWQ128): Likewise. (IX86_BUILTIN_PMOVSXDQ128): Likewise. (IX86_BUILTIN_PMOVZXBW128): Likewise. (IX86_BUILTIN_PMOVZXBD128): Likewise. (IX86_BUILTIN_PMOVZXBQ128): Likewise. (IX86_BUILTIN_PMOVZXWD128): Likewise. (IX86_BUILTIN_PMOVZXWQ128): Likewise. (IX86_BUILTIN_PMOVZXDQ128): Likewise. (IX86_BUILTIN_PMULDQ128): Likewise. (IX86_BUILTIN_PMULLD128): Likewise. (IX86_BUILTIN_ROUNDPD): Likewise. (IX86_BUILTIN_ROUNDPS): Likewise. (IX86_BUILTIN_ROUNDSD): Likewise. (IX86_BUILTIN_ROUNDSS): Likewise. (IX86_BUILTIN_PTESTZ): Likewise. (IX86_BUILTIN_PTESTC): Likewise. (IX86_BUILTIN_PTESTNZC): Likewise. (IX86_BUILTIN_VEC_EXT_V16QI): Likewise. (IX86_BUILTIN_VEC_SET_V2DI): Likewise. (IX86_BUILTIN_VEC_SET_V4SF): Likewise. (IX86_BUILTIN_VEC_SET_V4SI): Likewise. (IX86_BUILTIN_VEC_SET_V16QI): Likewise. (bdesc_ptest): New. (bdesc_sse_3arg): Likewise. (bdesc_2arg): Likewise. (bdesc_1arg): Likewise. (ix86_init_mmx_sse_builtins): Support SSE4.1. Handle SSE builtins with 3 args. (ix86_expand_sse_4_operands_builtin): New. (ix86_expand_unop_builtin): Support 2 arg builtins with a constant smaller than 8 bits as the 2nd arg. (ix86_expand_sse_ptest): New. (ix86_expand_builtin): Support SSE4.1. Support 3 arg SSE builtins. (ix86_expand_vector_set): Support SSE4.1. (ix86_expand_vector_extract): Likewise. * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Define __SSE4_1__ for -msse4.1. * config/i386/i386.md (UNSPEC_BLENDV): New for SSE4.1. (UNSPEC_INSERTPS): Likewise. (UNSPEC_DP): Likewise. (UNSPEC_MOVNTDQA): Likewise. (UNSPEC_MPSADBW): Likewise. (UNSPEC_PHMINPOSUW): Likewise. (UNSPEC_PTEST): Likewise. (UNSPEC_ROUNDP): Likewise. (UNSPEC_ROUNDS): Likewise. * config/i386/i386.opt (msse4.1): New for SSE4.1. * config/i386/predicates.md (const_pow2_1_to_2_operand): New. (const_pow2_1_to_32768_operand): Likewise. * config/i386/smmintrin.h: New. The SSE4.1 intrinsic header file. * config/i386/sse.md (*vec_setv4sf_sse4_1): New pattern for SSE4.1. (sse4_1_insertps): Likewise. (*sse4_1_extractps): Likewise. (sse4_1_ptest): Likewise. (sse4_1_mulv2siv2di3): Likewise. (*sse4_1_mulv4si3): Likewise. (*sse4_1_smax<mode>3): Likewise. (*sse4_1_umax<mode>3): Likewise. (*sse4_1_smin<mode>3): Likewise. (*sse4_1_umin<mode>3): Likewise. (sse4_1_eqv2di3): Likewise. (*sse4_1_pinsrb): Likewise. (*sse4_1_pinsrd): Likewise. (*sse4_1_pinsrq): Likewise. (*sse4_1_pextrb): Likewise. (*sse4_1_pextrb_memory): Likewise. (*sse4_1_pextrw_memory): Likewise. (*sse4_1_pextrq): Likewise. (sse4_1_blendpd): Likewise. (sse4_1_blendps): Likewise. (sse4_1_blendvpd): Likewise. (sse4_1_blendvps): Likewise. (sse4_1_dppd): Likewise. (sse4_1_dpps): Likewise. (sse4_1_movntdqa): Likewise. (sse4_1_mpsadbw): Likewise. (sse4_1_packusdw): Likewise. (sse4_1_pblendvb): Likewise. (sse4_1_pblendw): Likewise. (sse4_1_phminposuw): Likewise. (sse4_1_extendv8qiv8hi2): Likewise. (*sse4_1_extendv8qiv8hi2): Likewise. (sse4_1_extendv4qiv4si2): Likewise. (*sse4_1_extendv4qiv4si2): Likewise. (sse4_1_extendv2qiv2di2): Likewise. (*sse4_1_extendv2qiv2di2): Likewise. (sse4_1_extendv4hiv4si2): Likewise. (*sse4_1_extendv4hiv4si2): Likewise. (sse4_1_extendv2hiv2di2): Likewise. (*sse4_1_extendv2hiv2di2): Likewise. (sse4_1_extendv2siv2di2): Likewise. (*sse4_1_extendv2siv2di2): Likewise. (sse4_1_zero_extendv8qiv8hi2): Likewise. (*sse4_1_zero_extendv8qiv8hi2): Likewise. (sse4_1_zero_extendv4qiv4si2): Likewise. (*sse4_1_zero_extendv4qiv4si2): Likewise. (sse4_1_zero_extendv2qiv2di2): Likewise. (*sse4_1_zero_extendv2qiv2di2): Likewise. (sse4_1_zero_extendv4hiv4si2): Likewise. (*sse4_1_zero_extendv4hiv4si2): Likewise. (sse4_1_zero_extendv2hiv2di2): Likewise. (*sse4_1_zero_extendv2hiv2di2): Likewise. (sse4_1_zero_extendv2siv2di2): Likewise. (*sse4_1_zero_extendv2siv2di2): Likewise. (sse4_1_roundpd): Likewise. (sse4_1_roundps): Likewise. (sse4_1_roundsd): Likewise. (sse4_1_roundss): Likewise. (mulv4si3): Don't expand for SSE4.1. (smax<mode>3): Likewise. (umaxv4si3): Likewise. (uminv16qi3): Likewise. (umin<mode>3): Likewise. (umaxv8hi3): Rewrite. Only enabled for SSE4.1. * doc/extend.texi: Document SSE4.1 built-in functions. * doc/invoke.texi: Document -msse4.1. Co-Authored-By: Richard Henderson <rth@redhat.com> From-SVN: r124945
2007-05-16README: Update for new files.Uros Bizjak1-2/+2
* soft-fp/README: Update for new files. * soft-fp/floattisf.c: New file. * soft-fp/floattidf.c: New file. * soft-fp/floattitf.c: New file. * soft-fp/floatuntisf.c: New file. * soft-fp/floatuntidf.c: New file. * soft-fp/floatuntitf.c: New file. * soft-fp/fixsfti.c: New file. * soft-fp/fixdfti.c: New file. * soft-fp/fixtfti.c: New file. * soft-fp/fixunssfti.c: New file. * soft-fp/fixunsdfti.c: New file. * soft-fp/fixunstfti.c: New file. * soft-fp/extendxftf.c: New file. * soft-fp/trunctfxf.c: New file. * libgcc-std.ver (__extendxftf2): Added to GCC_4.3.0 section. (__trunctfxf2): Ditto. * config/i386/libgcc-x86_64-glibc.ver (__addtf3, __divtf3, __eqtf2, __extenddftf2, __extendsftf2, __fixtfdi, __fixtfsi, __fixtfti, __fixunstfdi, __fixunstfsi, __fixunstfti, __floatditf, __floatsitf, __floattitf, __floatunditf, __floatunsitf, __floatuntitf, __getf2, __letf2, __multf3, __negtf2, __subtf3, __trunctfdf2, __trunctfsf2, __unordtf2): Exclude and add to GCC_4.3.0 section for x86_64 targets. * config/i386/t-fprules-softfp64: New file. * config/i386/sfp-machine.h: New file. * config.gcc (x86_64-*-linux*, x86_64-*-kfreebsd*-gnu, x86_64-*-knetbsd*-gnu): Add i386/t-fprules-softfp64 and soft-fp/t-softfp to tmake_file. (i[34567]86-*-linux*, i[34567]86-*-kfreebsd*-gnu, i[34567]86-*-knetbsd*-gnu): Ditto for --enable-targets=all. * config/i386/t-linux64 (softfp_wrap_start): New. (softfp_wrap_end): New. * config/i386/i386.c (ix86_scalar_mode_supported): TFmode is supported for TARGET_64BIT. testsuite/ChangeLog: * gcc.dg/torture/fp-int-convert-float128.c: Do not xfail for i?86-*-* and x86_64-*-* targets. * gcc.dg/torture/fp-int-convert-float128-timode.c: Ditto. From-SVN: r124775
2007-05-10config.gcc (sparc-wrs-vxworks): New target.Richard Sandiford1-0/+4
gcc/ * config.gcc (sparc-wrs-vxworks): New target. * config/sparc/vxworks.h, config/sparc/t-vxworks: New files. * config/sparc/sparc-protos.h (sparc_emit_call_insn): Declare. * config/sparc/sparc.h: Include vxworks-dummy.h. (PRINT_OPERAND_ADDRESS): Extend SYMBOL_REF handling to include LABEL_REFs too. * config/sparc/sparc.c (sparc_expand_move): Don't assume that _GLOBAL_OFFSET_TABLE_ - label_ref is a link-time constant on VxWorks. (legitimize_pic_address): Handle LABEL_REFs like SYMBOL_REFs on VxWorks. (load_pic_register): Use gen_vxworks_load_got for VxWorks. (sparc_emit_call_insn): New function. (sparc_function_ok_for_sibcall): Restrict sibcalls to locally-binding functions when generating VxWorks PIC. * config/sparc/sparc.md (vxworks_load_got): New pattern. (call, call_value): Use sparc_emit_call_insn instead of emit_call_insn. libgcc/ * config.host (sparc-wrs-vxworks): New target. From-SVN: r124595
2007-04-25config.gcc (sh-wrs-vxworks): Don't include dbxelf.h.Richard Sandiford1-1/+1
gcc/ * config.gcc (sh-wrs-vxworks): Don't include dbxelf.h. Include sh/elf.h, vx-common.h and vxworks.h. * config/sh/sh.h: Include config/vxworks-dummy.h. (SUBTARGET_OVERRIDE_OPTIONS): Define. (OVERRIDE_OPTIONS): Use it. * config/sh/sh.md (GOTaddr2picreg): Add suport for VxWorks RTPs. (vxworks_picreg): New pattern. * config/sh/vxworks.h (TARGET_OS_CPP_BUILTINS): Use VXWORKS_OS_CPP_BUILTINS. (LIB_SPEC, LINK_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Redefine to their VXWORKS_* equivalents. (SUBTARGET_OVERRIDE_OPTIONS, SUBTARGET_CPP_SPEC): Define. (SUBTARGET_LINK_EMUL_SUFFIX, FUNCTION_PROFILER): Define. * config/sh/lib1funcs.asm (NO_FPSCR_VALUES): Define for VxWorks PIC. (set_fpscr, ic_invalidate): Add VxWorks PIC sequences. * config/sh/t-vxworks (MULTILIB_OPTIONS): Add m4a, -mrtp and -mrtp/-fPIC multilibs. (MULTILIB_EXCEPTIONS): Generalize globs accordingly. (MULTILIB_MATCHES, EXTRA_MULTILIB_PARTS): Define. (MULTILIB_OSDIRNAMES): Delete. From-SVN: r124145
2007-04-14config.gcc: Recognize fido.Kazu Hirata1-6/+34
gcc/ * config.gcc: Recognize fido. * config/m68k/m68k-devices.def (fidoa): New. * config/m68k/m68k.h (TARGET_CPU_CPP_BUILTINS): Define __mfido__. (FL_FIDOA, TARGET_FIDOA): New. * config/m68k/m68k.opt (mfidoa): New. libgcc/ * config.host: Recognize fido. From-SVN: r123811
generated by cgit v1.1 at 2025-09-03 18:00:06 +0000