aboutsummaryrefslogtreecommitdiff
path: root/gcc/common
AgeCommit message (Expand)AuthorFilesLines
2021-04-12Add rocketlake to gcc.Cui,Lili3-2/+13
2021-04-12Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2Cui,Lili1-0/+1
2021-03-24i386: fix -march=amd crashMartin Liska1-1/+1
2021-03-23RISC-V: Add riscv{32,64}be with big endian as defaultMarcus Comstedt1-0/+5
2021-03-09arm: fix bootstrap failure following automatic mode selection patchRichard Earnshaw1-1/+1
2021-03-03arm: Ignore --with-mode when CPU only supports one instruction set.Richard Earnshaw1-6/+43
2021-03-02IBM Z: arch14: Add command line optionsAndreas Krebbel1-0/+4
2021-01-28RISC-V: Fix -march option parsing when extension exists.Xing GUO1-3/+1
2021-01-14i386: Resolve variable shadowing in i386-options.c [PR98671]Uros Bizjak1-1/+1
2021-01-08RISC-V: Implement new style of architecture extension test macros.Kito Cheng1-0/+5
2021-01-08RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.hKito Cheng1-66/+1
2021-01-04Update copyright years.Jakub Jelinek57-57/+57
2020-12-11Fix feature check for HRESET/AVX_VNNI/UINTRHongyu1-10/+15
2020-12-05X86_64: Enable support for next generation AMD Zen3 CPU.Venkataramanan Kumar3-1/+34
2020-11-18RISC-V: Support version controling for ISA standard extensionsKito Cheng1-72/+215
2020-11-18RISC-V: Support zicsr and zifencei extension for -march.Kito Cheng1-0/+6
2020-11-18RISC-V: Handle implied extension in canonical ordering.Kito Cheng1-5/+172
2020-11-11Support Intel AVX VNNIliuhongt4-1/+23
2020-11-06RISC-V: Mark non-export symbol static and const in riscv-common.cKito Cheng1-2/+2
2020-11-02RISC-V: Check multiletter extension has more than 1 letterKito Cheng1-0/+8
2020-10-29Enable GCC to support Intel Key Locker ISAliuhongt4-18/+93
2020-10-27RISC-V: Refine riscv_parse_arch_stringKito Cheng1-33/+51
2020-10-15RISC-V: Add support for -mcpu option.Kito Cheng1-5/+86
2020-10-15Enable Intel HRESET InstructionHongyu Wang4-0/+20
2020-10-15Enable gcc support for UINTRliuhongt4-0/+19
2020-10-01PR target/97250: i386: Add support for x86-64-v2, x86-64-v3, x86-64-v4 levels...Florian Weimer1-3/+7
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt4-0/+72
2020-09-17If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx.liuhongt1-2/+3
2020-09-10aarch64: Add support for Armv8-RAlex Coplan1-2/+5
2020-09-08MSP430: Use enums to handle -mcpu= valuesJozef Lawrynowicz1-23/+3
2020-08-28Fix: AVX512VP2INTERSECT should imply AVX512DQ.liuhongt1-2/+2
2020-08-19x86: Detect Rocket Lake and Alder LakeH.J. Lu1-0/+10
2020-07-10Initial Sapphire Rapids and Alder Lake support from ISA r40Cui,Lili3-0/+16
2020-07-01RISC-V: Preserve arch version info during normalizing arch stringKito Cheng1-24/+46
2020-06-24x86: Remove brand ID check for Intel processorsH.J. Lu1-7/+5
2020-06-24x86: Add Cooper Lake detection with AVX512BF16H.J. Lu1-1/+9
2020-06-24x86: Share _isa_names_table and use cpuinfo.hH.J. Lu1-0/+163
2020-06-24x86: Move cpuinfo.h from libgcc to common/config/i386H.J. Lu2-0/+942
2020-06-24x86: Fold arch_names_table into processor_alias_tableH.J. Lu2-90/+283
2020-06-08[arm] (header usage fix) include c++ algorithm header via system.hChristophe Lyon1-1/+1
2020-05-21Add outline-atomics to target attribute.Martin Liska1-0/+4
2020-05-19RISC-V: Handle implied extension for -march parser.Kito Cheng1-10/+75
2020-05-19RISC-V: Update march parserKito Cheng1-20/+20
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt1-0/+15
2020-05-06Enable GCC support for SERIALIZEliuhongt1-0/+15
2020-04-29[gcn] Set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282]Thomas Schwinge1-0/+9
2020-04-27rs6000: enable -fweb for small loops unrollingguojiufu1-3/+3
2020-04-03AArch64: Fix options canonicalization for assemblerTamar Christina1-1/+16
2020-03-16[ARM][GCC][2/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni1-1/+2
2020-02-20Remove trailing | in help message.Martin Liska1-3/+3
generated by cgit v1.1 at 2024-11-11 10:44:55 +0000