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2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay1-0/+2
The Reduced Tiny core does not support indirect addressing with offset, which basically means that every indirect memory access with a size of more than one byte is effectively POST_INC or PRE_DEC. The lack of that addressing mode is currently handled by pretending to support it, and then let the insn printers add and subtract again offsets as needed. For example, the following C code int vars[10]; void inc_var2 (void) { ++vars[2]; } is compiled to: ldi r30,lo8(vars) ; 14 [c=4 l=2] *movhi/4 ldi r31,hi8(vars) subi r30,lo8(-(4)) ; 15 [c=8 l=6] *movhi/2 sbci r31,hi8(-(4)) ld r20,Z+ ld r21,Z subi r30,lo8((4+1)) sbci r31,hi8((4+1)) subi r20,-1 ; 16 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 subi r30,lo8(-(4+1)) ; 17 [c=4 l=4] *movhi/3 sbci r31,hi8(-(4+1)) st Z,r21 st -Z,r20 where the code could be -- and with this patch actually is -- like ldi r30,lo8(vars+4) ; 28 [c=4 l=2] *movhi/4 ldi r31,hi8(vars+4) ld r20,Z+ ; 17 [c=8 l=2] *movhi/2 ld r21,Z+ subi r20,-1 ; 19 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 st -Z,r21 ; 30 [c=4 l=2] *movhi/3 st -Z,r20 This is achieved in two steps: - A post-reload split into "real" instructions during .split2. - A new avr-specific mini pass .avr-fuse-add that runs before RTL peephole and that tries to combine the generated pointer additions into memory accesses to form POST_INC or PRE_DEC. gcc/ PR target/114100 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. * config/avr/avr.opt (-mfuse-add=): New target option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. * config/avr/avr-protos.h (avr_split_tiny_move) (make_avr_pass_fuse_add): New protos. * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses avr_split_tiny_move to split indirect memory accesses. (gen_move_clobbercc): New define_expand helper. * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. (avr_pass_fuse_add): New class from rtl_opt_pass. (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets of PLUS addressing for AVR_TINY. (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng1-0/+46
The output of -march=help is like below: ``` All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 ... ``` Also support -print-supported-extensions and --print-supported-extensions for clang compatibility. gcc/ChangeLog: PR target/109349 * common/config/riscv/riscv-common.cc (riscv_arch_help): New. * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. (RISCV_MINOR_VERSION_BASE): Ditto. (RISCV_REVISION_VERSION_BASE): Ditto. * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum rather than magic number. * config/riscv/riscv.h (riscv_arch_help): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and --print-supported-extensions. * config/riscv/riscv.opt (march=help): New. (print-supported-extensions): New. (-print-supported-extensions): New. * doc/invoke.texi (RISC-V Options): Document -march=help. Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+14
The RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions These extensions don't add any new features but describe existing features. So this patch only adds parsing. Za64rs: Reservation set size of 64 bytes Za128rs: Reservation set size of 128 bytes Ziccif: Main memory supports instruction fetch with atomicity requirement Ziccrse: Main memory supports forward progress on LR/SC sequences Ziccamoa: Main memory supports all atomics in A Zicclsm: Main memory supports misaligned loads/stores Zic64b: Cache block size isf 64 bytes gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items. * config/riscv/riscv.opt: New macro for 7 new unprivileged extensions. * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/za-ext.c: New test. * gcc.target/riscv/zi-ext.c: New test.
2024-01-25RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension.
2024-01-24RISC-V: Don't make Ztso imply APalmer Dabbelt1-2/+0
I can't actually find anything in the ISA manual that makes Ztso imply A. In theory the memory ordering is just a different thing that the set of availiable instructions (ie, Ztso without A would still imply TSO for loads and stores). It also seems like a configuration that could be sane to build: without A it's all but impossible to write any meaningful multi-core code, and TSO is really cheap for a single core. That said, I think it's kind of reasonable to provide A to users asking for Ztso. So maybe even if this was a mistake it's the right thing to do? gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Remove {"ztso", "a"}.
2024-01-19RISC-V: Add the Zihpm and Zicntr extensionsPalmer Dabbelt1-0/+3
These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions and otherwise ignores them. I added these under SPEC_CLASS_NONE even though the PDF lists them as 20190614 because it seems pointless to add another spec class just to accept two extensions we then ignore. 1: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/HZGoqP1eyps/m/GTNKRLJoAQAJ 2: https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjQhChrq9Q/m/7gqdkctgAgAJ gcc/ChangeLog * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr extensions.
2024-01-19RISC-V: Remove unused function in riscv_subset_list [NFC]Kito Cheng1-179/+0
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_std_ext): Remove. (riscv_subset_list::parse_multiletter_ext): Remove. * config/riscv/riscv-subset.h (riscv_subset_list::parse_std_ext): Remove. (riscv_subset_list::parse_multiletter_ext): Remove.
2024-01-19RISC-V: Relax the -march string for accept any orderKito Cheng1-37/+54
-march was require canonical order before, however it's not easy for most user when we have so many extension, so this patch is relax the constraint, -march accept the ISA string in any order, it only has few requirement: 1. Must start with rv[32|64][e|i|g]. 2. Multi-letter and single letter extension must be separated by at least one underscore(`_`). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_single_std_ext): New parameter. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::parse): Relax the order for the input of ISA string. * config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext): New parameter. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::parse_single_ext): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-33.c: New. * gcc.target/riscv/arch-34.c: New.
2024-01-19RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]Kito Cheng1-24/+45
Minor refactor, preparation for further change. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_base_ext): New. (riscv_subset_list::parse): Extract part of logic into riscv_subset_list::parse_base_ext. * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext): New.
2024-01-18RISC-V: Introduce XTheadVector as a subset of V1.0.0Jun Sha (Joshua)1-0/+23
This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extension. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add test marco. * config/riscv/riscv.opt: Add new mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. * gcc.target/riscv/rvv/xtheadvector.c: New test. Co-authored-by: Jin Ma <jinma@linux.alibaba.com> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-03Update copyright years.Jakub Jelinek56-56/+56
2023-12-16[aarch64] Add function multiversioning supportAndrew Carlotti1-0/+94
This adds initial support for function multiversioning on aarch64 using the target_version and target_clones attributes. This loosely follows the Beta specification in the ACLE [1], although with some differences that still need to be resolved (possibly as follow-up patches). Existing function multiversioning implementations are broken in various ways when used across translation units. This includes placing resolvers in the wrong translation units, and using symbol mangling that callers to unintentionally bypass the resolver in some circumstances. Fixing these issues for aarch64 will require modifications to our ACLE specification. It will also require further adjustments to existing middle end code, to facilitate different mangling and resolver placement while preserving existing target behaviours. The list of function multiversioning features specified in the ACLE is also inconsistent with the list of features supported in target option extensions. I intend to resolve some or all of these inconsistencies at a later stage. The target_version attribute is currently only supported in C++, since this is the only frontend with existing support for multiversioning using the target attribute. On the other hand, this patch happens to enable multiversioning with the target_clones attribute in Ada and D, as well as the entire C family, using their existing frontend support. This patch also does not support the following aspects of the Beta specification: - The target_clones attribute should allow an implicit unlisted "default" version. - There should be an option to disable function multiversioning at compile time. - Unrecognised target names in a target_clones attribute should be ignored (with an optional warning). This current patch raises an error instead. [1] https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning gcc/ChangeLog: * config/aarch64/aarch64-feature-deps.h (fmv_deps_<FEAT_NAME>): Define aarch64_feature_flags mask foreach FMV feature. * config/aarch64/aarch64-option-extensions.def: Use new macros to define FMV feature extensions. * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p): Check for target_version attribute after processing target attribute. (aarch64_fmv_feature_data): New. (aarch64_parse_fmv_features): New. (aarch64_process_target_version_attr): New. (aarch64_option_valid_version_attribute_p): New. (get_feature_mask_for_version): New. (compare_feature_masks): New. (aarch64_compare_version_priority): New. (build_ifunc_arg_type): New. (make_resolver_func): New. (add_condition_to_bb): New. (dispatch_function_versions): New. (aarch64_generate_version_dispatcher_body): New. (aarch64_get_function_versions_dispatcher): New. (aarch64_common_function_versions): New. (aarch64_mangle_decl_assembler_name): New. (TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): New implementation. (TARGET_OPTION_EXPANDED_CLONES_ATTRIBUTE): New implementation. (TARGET_OPTION_FUNCTION_VERSIONS): New implementation. (TARGET_COMPARE_VERSION_PRIORITY): New implementation. (TARGET_GENERATE_VERSION_DISPATCHER_BODY): New implementation. (TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): New implementation. (TARGET_MANGLE_DECL_ASSEMBLER_NAME): New implementation. * config/aarch64/aarch64.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE): Set target macro. * config/arm/aarch-common.h (enum aarch_parse_opt_result): Add new value to report duplicate FMV feature. * common/config/aarch64/cpuinfo.h: New file. libgcc/ChangeLog: * config/aarch64/cpuinfo.c (enum CPUFeatures): Move to shared copy in gcc/common gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_17.c: Reorder expected flags. * gcc.target/aarch64/cpunative/native_cpu_0.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_13.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_16.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_17.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_18.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_19.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_20.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_21.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_6.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_7.c: Ditto.
2023-12-16aarch64: Fix +nopredres, +nols64 and +nomopsAndrew Carlotti1-8/+3
For native cpu feature detection, certain features have no entry in /proc/cpuinfo, so have to be assumed to be present whenever the detected cpu is supposed to support that feature. However, the logic for this was mistakenly implemented by excluding these features from part of aarch64_get_extension_string_for_isa_flags. This function is also used elsewhere when canonicalising explicit feature sets, which may require removing features that are normally implied by the specified architecture version. This change reenables generation of +nopredres, +nols64 and +nomops during canonicalisation, by relocating the misplaced native cpu detection logic. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_option_extension): Remove unused field. (all_extensions): Ditto. (aarch64_get_extension_string_for_isa_flags): Remove filtering of features without native detection. * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Explicitly add expected features that lack cpuinfo detection. gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_28.c: New test.
2023-12-16aarch64: Fix +nocrypto handlingAndrew Carlotti1-8/+27
Additionally, replace all checks for the AARCH64_FL_CRYPTO bit with checks for (AARCH64_FL_AES | AARCH64_FL_SHA2) instead. The value of the AARCH64_FL_CRYPTO bit within isa_flags is now ignored, but it is retained because removing it would make processing the data in option-extensions.def significantly more complex. This bug should have been picked up by an existing test, but a missing newline meant that the pattern incorrectly allowed "+crypto+nocrypto". gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_get_extension_string_for_isa_flags): Fix generation of the "+nocrypto" extension. * config/aarch64/aarch64.h (AARCH64_ISA_CRYPTO): Remove. (TARGET_CRYPTO): Remove. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Don't use TARGET_CRYPTO. gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_4.c: Add terminating newline. * gcc.target/aarch64/options_set_27.c: New test.
2023-12-15[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVelw. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVelw builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-elw-elw-compile-1.c: Create test for cv.elw. * lib/target-supports.exp: Add proc for the XCVelw extension.
2023-12-15[PATCH] RISC-V: Add Zvfbfmin extension to the -march= optionXiao Zeng1-0/+4
This patch would like to add new sub extension (aka Zvfbfmin) to the -march= option. It introduces a new data type BF16. Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. You can locate more information about Zvfbfmin from below spec doc. https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfbfmin item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt: (MASK_ZVFBFMIN): New macro. (MASK_VECTOR_ELEN_BF_16): Ditto. (TARGET_ZVFBFMIN): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-31.c: New test. * gcc.target/riscv/arch-32.c: New test. * gcc.target/riscv/predef-32.c: New test. * gcc.target/riscv/predef-33.c: New test.
2023-12-13RISC-V:Add crypto vector implied ISA info.Feng Wang1-0/+9
Due to the crypto vector entension is depend on the Vector extension, so add the implied ISA info with the corresponding crypto vector extension. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Modify implied ISA info. * config/riscv/arch-canonicalize: Add crypto vector implied info.
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+1
This pass adds a simple register allocator for FP & SIMD registers. Its main purpose is to make use of SME2's strided LD1, ST1 and LUTI2/4 instructions, which require a very specific grouping structure, and so would be difficult to exploit with general allocation. The allocator is very simple. It gives up on anything that would require spilling, or that it might not handle well for other reasons. The allocator needs to track liveness at the level of individual FPRs. Doing that fixes a lot of the PRs relating to redundant moves caused by structure loads and stores. That particular problem is going to be fixed more generally for GCC 15 by Lehua's RA patches. However, the early-RA pass runs before scheduling, so it has a chance to bag a spill-free allocation of vector code before the scheduler moves things around. It could therefore still be useful for non-SME code (e.g. for hand-scheduled ACLE code) even after Lehua's patches are in. The pass is controlled by a tristate switch: - -mearly-ra=all: run on all functions - -mearly-ra=strided: run on functions that have access to strided registers - -mearly-ra=none: don't run on any function The patch makes -mearly-ra=all the default at -O2 and above for now. We can revisit this for GCC 15 once Lehua's patches are in; -mearly-ra=strided might then be more appropriate. As said previously, the pass is very naive. There's much more that we could do, such as handling invariants better. The main focus is on not committing to a bad allocation, rather than on handling as much as possible. gcc/ PR rtl-optimization/106694 PR rtl-optimization/109078 PR rtl-optimization/109391 * config.gcc: Add aarch64-early-ra.o for AArch64 targets. * config/aarch64/t-aarch64 (aarch64-early-ra.o): New rule. * config/aarch64/aarch64-opts.h (aarch64_early_ra_scope): New enum. * config/aarch64/aarch64.opt (mearly_ra): New option. * doc/invoke.texi: Document it. * common/config/aarch64/aarch64-common.cc (aarch_option_optimization_table): Use -mearly-ra=strided by default for -O2 and above. * config/aarch64/aarch64-passes.def (pass_aarch64_early_ra): New pass. * config/aarch64/aarch64-protos.h (aarch64_strided_registers_p) (make_pass_aarch64_early_ra): Declare. * config/aarch64/aarch64-sme.md (@aarch64_sme_lut<LUTI_BITS><mode>): Add a stride_type attribute. (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): New pattern. (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svld1_impl::expand) (svldnt1_impl::expand, svst1_impl::expand, svstn1_impl::expand): Handle new way of defining multi-register loads and stores. * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>) (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>) (@aarch64_stnt1<SVE_FULLx24:mode>): Delete. * config/aarch64/aarch64-sve2.md (@aarch64_<LD1_COUNT:optab><mode>) (@aarch64_<LD1_COUNT:optab><mode>_strided2): New patterns. (@aarch64_<LD1_COUNT:optab><mode>_strided4): Likewise. (@aarch64_<ST1_COUNT:optab><mode>): Likewise. (@aarch64_<ST1_COUNT:optab><mode>_strided2): Likewise. (@aarch64_<ST1_COUNT:optab><mode>_strided4): Likewise. * config/aarch64/aarch64.cc (aarch64_strided_registers_p): New function. * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): Delete. (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise. (UNSPEC_STNT1_SVE_COUNT): Likewise. (stride_type): New attribute. * config/aarch64/constraints.md (Uwd, Uwt): New constraints. * config/aarch64/iterators.md (UNSPEC_LD1_COUNT, UNSPEC_LDNT1_COUNT) (UNSPEC_ST1_COUNT, UNSPEC_STNT1_COUNT): New unspecs. (optab): Handle them. (LD1_COUNT, ST1_COUNT): New iterators. * config/aarch64/aarch64-early-ra.cc: New file. gcc/testsuite/ PR rtl-optimization/106694 PR rtl-optimization/109078 PR rtl-optimization/109391 * gcc.target/aarch64/ldp_stp_16.c (cons4_4_float): Tighten expected output test. * gcc.target/aarch64/sve/shift_1.c: Allow reversed shifts for .s as well as .d. * gcc.target/aarch64/sme/strided_1.c: New test. * gcc.target/aarch64/pr109078.c: Likewise. * gcc.target/aarch64/pr109391.c: Likewise. * gcc.target/aarch64/sve/pr106694.c: Likewise.
2023-12-05RISC-V: Check if zcd conflicts with zcmt and zcmpKito Cheng1-0/+8
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): Check zcd conflicts with zcmt and zcmp. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-29.c: New test. * gcc.target/riscv/arch-30.c: New test.
2023-12-04RISC-V: Update crypto vector ISA info with latest specFeng Wang1-2/+4
This patch add the Zvkb subset of crypto vector extension. The corresponding test cases have aslo been modified. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zvkb ISA info. * config/riscv/riscv.opt: Add Mask(ZVKB) gcc/testsuite/ChangeLog: * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb. * gcc.target/riscv/zvkn.c: Ditto. * gcc.target/riscv/zvknc-1.c:Ditto. * gcc.target/riscv/zvknc-2.c:Ditto. * gcc.target/riscv/zvknc.c: Ditto. * gcc.target/riscv/zvkng-1.c:Ditto. * gcc.target/riscv/zvkng-2.c:Ditto. * gcc.target/riscv/zvkng.c: Ditto. * gcc.target/riscv/zvks-1.c: Ditto. * gcc.target/riscv/zvks.c: Ditto. * gcc.target/riscv/zvksc-1.c:Ditto. * gcc.target/riscv/zvksc-2.c:Ditto. * gcc.target/riscv/zvksc.c: Ditto. * gcc.target/riscv/zvksg-1.c:Ditto. * gcc.target/riscv/zvksg-2.c:Ditto. * gcc.target/riscv/zvksg.c: Ditto.
2023-12-04RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional ↵Kito Cheng1-11/+33
implication [NFC] RISC-V ISA implication rules become little bit complicated than before, it may come with condition, so this commit extend the capability of riscv_implied_info_t, also make it more...C++ize. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New. (riscv_implied_info_t::riscv_implied_info_t): New. (riscv_implied_info_t::match): New. (riscv_implied_info): New entry for zcf. (riscv_subset_list::handle_implied_ext): Use riscv_implied_info_t::match. (riscv_subset_list::check_implied_ext): Ditto. (riscv_subset_list::handle_combine_ext): Ditto. (riscv_subset_list::parse): Move zcf implication handling to riscv_implied_infos.
2023-12-04RISC-V: Refine riscv_subset_list::parse [NFC]Kito Cheng1-12/+19
Extract the logic of checking conflict extensions to a standard alone function, prepare to add more checking logic. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): New. (riscv_subset_list::parse): Move checking conflict ext. to check_conflict_ext. * config/riscv/riscv-subset.h: Add riscv_subset_list::check_conflict_ext.
2023-12-04i386: Fix CPUID of USER_MSR.Hu, Lin11-2/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR to the correct location. gcc/testsuite/ChangeLog: * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user an proper example.
2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-4/+4
Along with RV32E, RV64E is ratified. Though ILP32E and LP64E ABIs are still draft, it's worth supporting it. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Set version to ratified 2.0. (riscv_subset_list::parse_std_ext): Allow RV64E. * config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'. * config/riscv/arch-canonicalize: Parse base ISA 'rv64e'. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define different macro per XLEN. Add handling for ABI_LP64E. * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi): Add handling for ABI_LP64E. * config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E. * config/riscv/riscv.cc (riscv_option_override): Enhance error handling to support RV64E and LP64E. (riscv_conditional_register_usage): Change "RV32E" in a comment to "RV32E/RV64E". * config/riscv/riscv.h (UNITS_PER_FP_ARG): Add handling for ABI_LP64E. (STACK_BOUNDARY): Ditto. (ABI_STACK_BOUNDARY): Ditto. (MAX_ARGS_IN_REGISTERS): Ditto. (ABI_SPEC): Add support for "lp64e". * config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E. * doc/invoke.texi: Add documentation of the LP64E ABI. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-1.c: Test for __riscv_64e. * gcc.target/riscv/predef-2.c: Ditto. * gcc.target/riscv/predef-3.c: Ditto. * gcc.target/riscv/predef-4.c: Ditto. * gcc.target/riscv/predef-5.c: Ditto. * gcc.target/riscv/predef-6.c: Ditto. * gcc.target/riscv/predef-7.c: Ditto. * gcc.target/riscv/predef-8.c: Ditto. * gcc.target/riscv/predef-9.c: New test for RV64E and LP64E, based on predef-7.c.
2023-11-20Initial support for AVX10.1Haochen Jiang4-1/+92
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_256_SET): New. (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1. (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512. Add indicator for explicit no-avx512 and no-avx10.1 options. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_1_256 and AVX10_1_512. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (check_avx10_avx512_features): New. (host_detect_local_cpu): Do not append "-mno-" options under specific scenarios to avoid emitting a warning. * config/i386/i386-isa.def (EVEX512): Add DEF_PTA(EVEX512). (AVX10_1_256): Add DEF_PTA(AVX10_1_256). (AVX10_1_512): Add DEF_PTA(AVX10_1_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and -mavx10.1-512. (ix86_function_specific_save): Save explicit no indicator. (ix86_function_specific_restore): Restore explicit no indicator. (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and avx10.1-512. (ix86_valid_target_attribute_tree): Handle avx512 function attributes with avx10.1 command line option. (ix86_option_override_internal): Handle AVX10.1 options. * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target machines. * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: New test. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto.
2023-11-15RISC-V: Fix ICE in non-canonical march parsingPatrick O'Neill1-4/+13
Passing in a base extension in non-canonical order (i, e, g) causes GCC to ICE: xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e' xgcc: internal compiler error: in add, at common/config/riscv/riscv-common.cc:671 ... This is fixed by skipping to the next extension when a non-canonical order is detected. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_std_ext): Emit an error and skip to the next extension when a non-canonical ordering is detected. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-27.c: New test. * gcc.target/riscv/arch-28.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-10-30i386: Zhaoxin yongfeng enablementMayshao3-5/+12
Enable -march/-mtune=yongfeng. Costs and tunings are set according to the characteristics of the processor. Add a new .md file to describe yongfeng processor. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize yongfeng. * common/config/i386/i386-common.cc: Add yongfeng. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add ZHAOXIN_FAM7H_YONGFENG. * config.gcc: Add yongfeng. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize yongfeng processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add yongfeng. * config/i386/i386-options.cc (m_YONGFENG): New definition. (m_ZHAOXIN): Ditto. * config/i386/i386.h (enum processor_type): Add PROCESSOR_YONGFENG. * config/i386/i386.md: Add yongfeng. * config/i386/lujiazui.md: Fix typo. * config/i386/x86-tune-costs.h (struct processor_costs): Add yongfeng costs. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add yongfeng. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Replace m_LUJIAZUI with m_ZHAOXIN. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_MOVX): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_LCP_STALL): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_OPT_AGU): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_EXPAND_ABS): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_USE_FFREEP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. (X86_TUNE_USE_GATHER_2PARTS): Add m_YONGFENG. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER_8PARTS): Ditto. (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. * doc/extend.texi: Add details about yongfeng. * doc/invoke.texi: Ditto. * config/i386/yongfeng.md: New file to describe yongfeng processor. gcc/testsuite/ChangeLog: * g++.target/i386/mv32.C: Handle new -march. * gcc.target/i386/funcspec-56.inc: Ditto.
2023-10-22RISC-V: Prohibit combination of 'E' and 'H'Tsukasa OI1-0/+4
According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Prohibit 'E' and 'H' combinations. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-26.c: New test.
2023-10-22RISC-V: 'Zfa' extension is now ratifiedTsukasa OI1-1/+1
Since this extension is ratified, it now has the version number 1.0. Reference: <https://github.com/riscv/riscv-isa-manual/pull/1096> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Change version number of the 'Zfa' extension to 1.0.
2023-10-18Initial Panther Lake SupportHaochen Jiang3-0/+12
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Add Panther Lake. * common/config/i386/i386-common.cc (processor_name): Ditto. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_PANTHERLAKE. * config.gcc: Add -march=pantherlake. * config/i386/driver-i386.cc (host_detect_local_cpu): Refactor the if clause. Handle pantherlake. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle pantherlake. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_PANTHERLAKE): New. (m_CORE_HYBRID): Add pantherlake. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-10-18Initial Clearwater Forest SupportHaochen Jiang3-0/+10
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Clearwater Forest. * common/config/i386/i386-common.cc (processor_name): Add Clearwater Forest. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_CLEARWATERFOREST. * config.gcc: Add -march=clearwaterforest. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle clearwaterforest. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_CLEARWATERFOREST): New. (m_CORE_ATOM): Add clearwaterforest. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-10-12Support Intel USER_MSRHu, Lin14-0/+19
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect USER_MSR. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_USER_MSR_SET): New. (OPTION_MASK_ISA2_USER_MSR_UNSET): Ditto. (ix86_handle_option): Handle -musermsr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_USER_MSR. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for usermsr. * config.gcc: Add usermsrintrin.h * config/i386/cpuid.h (bit_USER_MSR): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (VOID, UINT64, UINT64). * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Add __builtin_urdmsr and __builtin_uwrmsr. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_URDMSR and IX86_BUILTIN_UWRMSR. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __USER_MSR__. * config/i386/i386-expand.cc (ix86_expand_builtin): Handle new builtins. * config/i386/i386-isa.def (USER_MSR): Add DEF_PTA(USER_MSR). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle usermsr. * config/i386/i386.md (urdmsr): New define_insn. (uwrmsr): Ditto. * config/i386/i386.opt: Add option -musermsr. * config/i386/x86gprintrin.h: Include usermsrintrin.h * doc/extend.texi: Document usermsr. * doc/invoke.texi: Document -musermsr. * doc/sourcebuild.texi: Document target usermsr. * config/i386/usermsrintrin.h: New file. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -musermsr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add musermsr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto * gcc.target/i386/user_msr-1.c: New test. * gcc.target/i386/user_msr-2.c: Ditto.
2023-10-11RISC-V: Extend riscv_subset_list, preparatory for target attribute supportKito Cheng1-0/+209
riscv_subset_list only accept a full arch string before, but we need to parse single extension when supporting target attribute, also we may set a riscv_subset_list directly rather than re-parsing the ISA string again. gcc/ChangeLog: * config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext): New. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::clone): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::set_loc): Ditto. (riscv_set_arch_by_subset_list): Ditto. * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_single_std_ext): New. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::clone): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::set_loc): Ditto. (riscv_set_arch_by_subset_list): Ditto.
2023-10-11[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add the XCValu extension. * config/riscv/constraints.md: Add builtins for the XCValu extension. * config/riscv/predicates.md (immediate_register_operand): Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. (RISCV_ATYPE_UHI): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Likewise. * doc/extend.texi: Add XCValu documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add proc for the XCValu extension. * gcc.target/riscv/cv-alu-compile.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addun.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-clip.c: New test. * gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subun.c: New test. * gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test. * gcc.target/riscv/cv-alu-fail-compile.c: New test.
2023-10-11[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+4
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVmac. * config/riscv/riscv-ftypes.def: Add XCVmac builtins. * config/riscv/riscv-builtins.cc: Likewise. * config/riscv/riscv.md: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVmac builtin documentation. * doc/sourcebuild.texi: Likewise. * config/riscv/corev.def: New file. * config/riscv/corev.md: New file. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add new effective target check. * gcc.target/riscv/cv-mac-compile.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mac.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-msu.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test. * gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
2023-10-09Initial support for -mevex512Haochen Jiang1-0/+15
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_EVEX512_SET): New. (OPTION_MASK_ISA2_EVEX512_UNSET): Ditto. (ix86_handle_option): Handle EVEX512. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__ when AVX512VL is set. * config/i386/i386-options.cc: (isa2_opts): Handle EVEX512. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Set EVEX512 target if it is not explicitly set when AVX512 is enabled. Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. * config/i386/i386.opt: Add mevex512. Temporaily RejectNegative.
2023-10-07[APX_EGPR] Initial support for APX_FKong Lingling4-1/+30
Add -mapx-features= enumeration to separate subfeatures of APX_F. -mapxf is treated same as previous ISA flag, while it sets -mapx-features=apx_all that enables all subfeatures. gcc/ChangeLog: * common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro. (XCR_APX_F_ENABLED_MASK): Likewise. (get_available_features): Detect APX_F under * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_APX_F_SET): New. (OPTION_MASK_ISA2_APX_F_UNSET): Likewise. (ix86_handle_option): Handle -mapxf. * common/config/i386/i386-cpuinfo.h (FEATURE_APX_F): New. * common/config/i386/i386-isas.h: Add entry for APX_F. * config/i386/cpuid.h (bit_APX_F): New. * config/i386/i386.h (bit_APX_F): (TARGET_APX_EGPR, TARGET_APX_PUSH2POP2, TARGET_APX_NDD): New define. * config/i386/i386-opts.h (enum apx_features): New enum. * config/i386/i386-isa.def (APX_F): New DEF_PTA. * config/i386/i386-options.cc (ix86_function_specific_save): Save ix86_apx_features. (ix86_function_specific_restore): Restore it. (ix86_valid_target_attribute_inner_p): Add mapxf. (ix86_option_override_internal): Set ix86_apx_features for PTA and TARGET_APX_F. Also reports error when APX_F is set but not having TARGET_64BIT. * config/i386/i386.opt: (-mapxf): New ISA flag option. (-mapx=): New enumeration option. (apx_features): New enum type. (apx_none): New enum value. (apx_egpr): Likewise. (apx_push2pop2): Likewise. (apx_ndd): Likewise. (apx_all): Likewise. * doc/invoke.texi: Document mapxf. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-1.c: New test. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
2023-09-08LoongArch: Enable -fsched-pressure by default at -O1 and higher.Guo Jie1-0/+1
gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: (default_options loongarch_option_optimization_table): Default to -fsched-pressure.
2023-09-07RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' supportTsukasa OI1-0/+2
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard 'Zicond' extension are functionally equivalent (only encodings and instruction names are different). * czero.eqz == vt.maskc * czero.nez == vt.maskcn This commit adds support for the 'XVentanaCondOps' extension by extending 'Zicond' extension support. With this, we can now reuse the optimization using the 'Zicond' extension for the 'XVentanaCondOps' extension. The specification for the 'XVentanaCondOps' extension is based on: <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Parse 'XVentanaCondOps' extension. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New. (TARGET_XVENTANACONDOPS): Ditto. (TARGET_ZICOND_LIKE): New to represent targets with conditional moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'. * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. (riscv_expand_conditional_move): Ditto. * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. * config/riscv/riscv.opt: Add new riscv_xventana_subext. * config/riscv/zicond.md: Modify description. (eqz_ventana): New to match corresponding czero instructions. (nez_ventana): Ditto. (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if 'Zicond' is not available but 'XVentanaCondOps' + RV64 is. (*czero.<eqz>.<GPR><X>): Ditto. (*czero.eqz.<GPR><X>.opt1): Ditto. (*czero.nez.<GPR><X>.opt2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test, * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New test to make sure that XVentanaCondOps instructions are disabled on RV32. * gcc.target/riscv/xventanacondops-xor-01.c: New test,
2023-09-05arc: Remove obsolete mbbit-peephole option and unused patterns.Claudiu Zissulescu1-1/+0
gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove mbbit_peephole. * config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove. (store_direct): Likewise. (BBIT peephole2): Likewise. * config/arc/arc.opt (mbbit-peephole): Ignore option. * doc/invoke.texi (mbbit-peephole): Update document. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-08-29RISC-V: Add stub support for existing extensions (unprivileged)Tsukasa OI1-0/+1
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported standard unprivileged extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet merged 'Zce', 'Zcmp' and 'Zcmt' support). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from unprivileged extensions. (riscv_ext_version_table): Add stub support for all unprivileged extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-31.c: New test for a stub unprivileged extension 'Zcb' with some implications.
2023-08-29RISC-V: Add stub support for existing extensions (vendor)Tsukasa OI1-0/+2
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported vendor extensions to riscv_ext_version_table (no riscv_implied_info entries to add; all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add stub support for all vendor extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-30.c: New test for a stub vendor extension 'XVentanaCondOps'.
2023-08-29RISC-V: Add stub support for existing extensions (privileged)Tsukasa OI1-0/+18
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. As a start, this commit adds stub supported *privileged* extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from privileged extensions. (riscv_ext_version_table): Add stub support for all privileged extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-29.c: New test for a stub privileged extension 'Smstateen' with some implications.
2023-08-29LoongArch: Enable '-free' starting at -O2.Lulu Cheng1-0/+1
gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-free' on O2 and above. * doc/invoke.texi: Modify the description information of the '-free' compilation option and add the LoongArch description. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend.c: New test.
2023-08-28RISC-V: __builtin_riscv_pause for all environmentTsukasa OI1-0/+2
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension (in the assembler). However, GCC emits "pause" unconditionally, making an assembler error while compiling code with __builtin_riscv_pause while the 'Zihintpause' extension disabled. However, the "pause" instruction code (0x0100000f) is a HINT and emitting its instruction code is safe in any environment. This commit implements handling for the 'Zihintpause' extension and emits ".insn 0x0100000f" instead of "pause" only if the extension is disabled (making the diagnostics better). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Implement the 'Zihintpause' extension, version 2.0. (riscv_ext_flag_table) Add 'Zihintpause' handling. * config/riscv/riscv-builtins.cc: Remove availability predicate "always" and add "hint_pause". (riscv_builtins) : Add "pause" extension. * config/riscv/riscv-opts.h (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New. * config/riscv/riscv.md (riscv_pause): Adjust output based on TARGET_ZIHINTPAUSE. gcc/testsuite/ChangeLog: * gcc.target/riscv/builtin_pause.c: Removed. * gcc.target/riscv/zihintpause-1.c: New test when the 'Zihintpause' extension is enabled. * gcc.target/riscv/zihintpause-2.c: Likewise. * gcc.target/riscv/zihintpause-noarch.c: New test when the 'Zihintpause' extension is disabled.
2023-08-25[PATCH v10] RISC-V: Add support for the Zfa extensionJin Ma1-0/+7
This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2023-April/127060.html What needs special explanation is: 1, According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to accelerate the processing of JavaScript Numbers.", so it seems that no implementation is required. 2, The instructions FMINM and FMAXM correspond to C23 library function fminimum and fmaximum. Therefore, this patch has simply implemented the pattern of fminm<hf\sf\df>3 and fmaxm<hf\sf\df>3 to prepare for later. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zfa extension version, which depends on the F extension. * config/riscv/constraints.md (zfli): Constrain the floating point number that the instructions FLI.H/S/D can load. * config/riscv/iterators.md (ceil): New. * config/riscv/riscv-opts.h (MASK_ZFA): New. (TARGET_ZFA): New. * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): New. * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New. (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used, memory is not applicable. (riscv_const_insns): Likewise. (riscv_legitimize_const_move): Likewise. (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no split is required. (riscv_split_doubleword_move): Likewise. (riscv_output_move): Output the mov instructions in zfa extension. (riscv_print_operand): Output the floating-point value of the FLI.H/S/D immediate in assembly. (riscv_secondary_memory_needed): Likewise. * config/riscv/riscv.md (fminm<mode>3): New. (fmaxm<mode>3): New. (movsidf2_low_rv32): New. (movsidf2_high_rv32): New. (movdfsisi3_rv32): New. (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_zfa): New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fleq-fltq.c: New test. * gcc.target/riscv/zfa-fli-zfh.c: New test. * gcc.target/riscv/zfa-fli.c: New test. * gcc.target/riscv/zfa-fmovh-fmovp.c: New test. * gcc.target/riscv/zfa-fli-1.c: New test. * gcc.target/riscv/zfa-fli-2.c: New test. * gcc.target/riscv/zfa-fli-3.c: New test. * gcc.target/riscv/zfa-fli-4.c: New test. * gcc.target/riscv/zfa-fli-6.c: New test. * gcc.target/riscv/zfa-fli-7.c: New test. * gcc.target/riscv/zfa-fli-8.c: New test. Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com>
2023-08-24RISC-V: Enable pressure-aware scheduling by default.Robin Dapp1-0/+2
this patch enables pressure-aware scheduling for riscv. There have been various requests for it so I figured I'd just go ahead and send the patch. There is some slight regression in code quality for a number of vector tests where we spill more due to different instructions order. The ones I looked at were a mix of bad luck and/or brittle tests. Comparing the size of the generated assembly or the number of vsetvls for SPECint also didn't show any immediate benefit but that's obviously not a very fine-grained analysis. As cost and scheduling models mature I expect the situation to improve and for now I think it's generally favorable to enable pressure-aware scheduling so we can work with it rather than trying to find every possible problem in advance. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add -fsched-pressure. * config/riscv/riscv.cc (riscv_option_override): Set sched pressure algorithm. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/narrow_constraint-1.c: Add -fno-sched-pressure. * gcc.target/riscv/rvv/base/narrow_constraint-17.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-18.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-19.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-20.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-21.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-22.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-23.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-24.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-25.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-26.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-27.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-28.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-29.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-30.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-31.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-4.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-5.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto.
2023-08-24Revert "Initial support for AVX10.1"Haochen Jiang4-96/+1
This reverts commit 11ad44da01dd1c91c96e45802fd8b1c50e88703f.
2023-08-24Revert "Emit a warning when disabling AVX512 with AVX10 enabled or disabling ↵Haochen Jiang1-54/+14
AVX10 with AVX512 enabled" This reverts commit 0288ab14732a16b3787546cdd159941eb7306cf3.
2023-08-24Revert "Emit a warning when AVX10 options conflict in vector width"Haochen Jiang1-20/+0
This reverts commit 26a820dc136b00b4dc37609429576b6a914cb572.
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