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2023-08-24Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")liuhongt1-4/+7
Both "graniterapid-d" and "graniterapids" are attached with PROCESSOR_GRANITERAPID in processor_alias_table but mapped to different __cpu_subtype in get_intel_cpu. And get_builtin_code_for_version will try to match the first PROCESSOR_GRANITERAPIDS in processor_alias_table which maps to "granitepraids" here. 861 else if (new_target->arch_specified && new_target->arch > 0) 1862 for (i = 0; i < pta_size; i++) 1863 if (processor_alias_table[i].processor == new_target->arch) 1864 { 1865 const pta *arch_info = &processor_alias_table[i]; 1866 switch (arch_info->priority) 1867 { 1868 default: 1869 arg_str = arch_info->name; This mismatch makes dispatch_function_versions check the preidcate of__builtin_cpu_is ("graniterapids") for "graniterapids-d" and causes the issue. The patch explicitly adds PROCESSOR_ARROWLAKE_S and PROCESSOR_GRANITERAPIDS_D to make a distinction. For "alderlake","raptorlake", "meteorlake" they share same isa, cost, tuning, and mapped to the same __cpu_type/__cpu_subtype in get_intel_cpu, so no need to add PROCESSOR_RAPTORLAKE and others. gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_names): Add new member graniterapids-s and arrowlake-s. * config/i386/i386-options.cc (processor_alias_table): Update table with PROCESSOR_ARROWLAKE_S and PROCESSOR_GRANITERAPIDS_D. (m_GRANITERAPID_D): New macro. (m_ARROWLAKE_S): Ditto. (m_CORE_AVX512): Add m_GRANITERAPIDS_D. (processor_cost_table): Add icelake_cost for PROCESSOR_GRANITERAPIDS_D and alderlake_cost for PROCESSOR_ARROWLAKE_S. * config/i386/x86-tune.def: Hanlde m_ARROWLAKE_S same as m_ARROWLAKE. * config/i386/i386.h (enum processor_type): Add new member PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S
2023-08-21Support -march=gracemontliuhongt2-0/+5
Alderlake-N is E-core only, add it as an alias of Alderlake. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Alderlake-N. * common/config/i386/i386-common.cc (alias_table): Support -march=gracemont as an alias of -march=alderlake.
2023-08-17Emit a warning when AVX10 options conflict in vector widthHaochen Jiang1-0/+20
gcc/ChangeLog: * common/config/i386/i386-common.cc (ix86_check_avx10_vector_width): New function to check isa_flags to emit a warning when there is a conflict in AVX10 options for vector width. (ix86_handle_option): Add check for avx10.1-256 and avx10.1-512. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10-max-512bit for -march=native. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-15.c: New test. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto.
2023-08-17Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 ↵Haochen Jiang1-14/+54
with AVX512 enabled gcc/ChangeLog: * common/config/i386/i386-common.cc (ix86_check_avx10): New function to check isa_flags and isa_flags_explicit to emit warning when AVX10 is enabled by "-m" option. (ix86_check_avx512): New function to check isa_flags and isa_flags_explicit to emit warning when AVX512 is enabled by "-m" option. (ix86_handle_option): Do not change the flags when warning is emitted. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.1 for -march=native. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-11.c: New test. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto.
2023-08-17Initial support for AVX10.1Haochen Jiang4-1/+96
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_512BIT_SET): New. (OPTION_MASK_ISA2_AVX10_1_SET): Ditto. (OPTION_MASK_ISA2_AVX10_512BIT_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10_1. (ix86_handle_option): Handle -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_512BIT, FEATURE_AVX10_1 and FEATURE_AVX10_512BIT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_512BIT, AVX10_1 and AVX10_1_512. * config/i386/constraints.md (Yk): Add AVX10_1. (Yv): Ditto. (k): Ditto. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/i386-c.cc (ix86_target_macros_internal): Define AVX10_512BIT and AVX10_1. * config/i386/i386-isa.def (AVX10_512BIT): Add DEF_PTA(AVX10_512BIT). (AVX10_1): Add DEF_PTA(AVX10_1). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1. (ix86_valid_target_attribute_inner_p): Handle avx10-512bit, avx10.1 and avx10.1-512. (ix86_option_override_internal): Enable AVX512{F,VL,BW,DQ,CD,BF16, FP16,VBMI,VBMI2,VNNI,IFMA,BITALG,VPOPCNTDQ} features for avx10.1-512. (ix86_valid_target_attribute_inner_p): Handle AVX10_1. * config/i386/i386.cc (ix86_get_ssemov): Add AVX10_1. (ix86_conditional_register_usage): Ditto. (ix86_hard_regno_mode_ok): Ditto. (ix86_rtx_costs): Ditto. * config/i386/i386.h (VALID_MASK_AVX10_MODE): New macro. * config/i386/i386.opt: Add option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * g++.target/i386/mv33.C: New test. * gcc.target/i386/avx10_1-1.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto. * gcc.target/i386/avx10_1-10.c: Ditto.
2023-08-14RISC-V: Minimal support for ZC* extensions.Jiawei1-0/+38
This patch is the minimal support for ZC* extensions, include the extension name, mask and target defination. Also define the dependencies with Zca and Zce extension. Notes that all ZC* extensions depend on the Zca extension. Zce includes all relevant ZC* extensions for microcontrollers using. Zce will imply zcf when 'f' extension enabled in rv32. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions. * config/riscv/riscv-opts.h (MASK_ZCA): New mask. (MASK_ZCB): Ditto. (MASK_ZCE): Ditto. (MASK_ZCF): Ditto. (MASK_ZCD): Ditto. (MASK_ZCMP): Ditto. (MASK_ZCMT): Ditto. (TARGET_ZCA): New target. (TARGET_ZCB): Ditto. (TARGET_ZCE): Ditto. (TARGET_ZCF): Ditto. (TARGET_ZCD): Ditto. (TARGET_ZCMP): Ditto. (TARGET_ZCMT): Ditto. * config/riscv/riscv.opt: New target variable.
2023-08-14x86: Update model values for Raptorlake.Cui, Lili1-0/+1
Update model values for Raptorlake according to SDM. gcc/ChangeLog * common/config/i386/cpuinfo.h (get_intel_cpu): Add model value 0xba to Raptorlake.
2023-08-10RISC-V: Add Ztso atomic mappingsPatrick O'Neill1-0/+6
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-08-09RISC-V: Remove non-existing 'Zve32d' extensionTsukasa OI1-1/+0
Since this extension does not exist, this commit prunes this from the defined extension version table. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove 'Zve32d' from the version list.
2023-08-09Rename local variable subleaf_level to max_subleaf_level.liuhongt1-3/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Rename local variable subleaf_level to max_subleaf_level.
2023-08-09Workaround possible CPUID bug in Sandy Bridge.liuhongt1-39/+43
Don't access leaf 7 subleaf 1 unless subleaf 0 says it is supported via EAX. Intel documentation says invalid subleaves return 0. We had been relying on that behavior instead of checking the max sublef number. It appears that some Sandy Bridge CPUs return at least the subleaf 0 EDX value for subleaf 1. Best guess is that this is a bug in a microcode patch since all of the bits we're seeing set in EDX were introduced after Sandy Bridge was originally released. This is causing avxvnniint16 to be incorrectly enabled with -march=native on these CPUs. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Check EAX for valid subleaf before use CPUID.
2023-08-02i386: refactor macros.Hu, Lin11-5/+5
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Change OPTION_MASK_ISA2_AMX_TILE to OPTION_MASK_ISA2_AMX_TILE_SET. (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto (OPTION_MASK_ISA2_AMX_COMPLEX_SET): Ditto (OPTION_MASK_ISA_ABM_SET): Change OPTION_MASK_ISA_POPCNT to OPTION_MASK_ISA_POPCNT_SET. Signed-off-by: Hu, Lin1 <lin1.hu@intel.com>
2023-07-26[PATCH 1/5] [RISC-V] Recognize Zicond extensionXiao Zeng1-0/+3
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. (TARGET_ZICOND): New target. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/attribute-21.c: New test. Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-07-24[committed] Use single quote rather than backquote in RISC-V diagnosticJeff Law1-3/+3
Similar to the other patch this morning, this fixes a warning that was causing the RISC-V bootstrap to fail. In this case the diagnostic used a backquote. This changes it to a simple single quote which the diagnostic framework won't complain about. Committed to the trunk. gcc/ * common/config/riscv/riscv-common.cc (riscv_subset_list::add): Use single quote rather than backquote in diagnostic.
2023-07-19RISC-V: Throw compilation error for unknown extensionsLehua Ding1-12/+56
This tiny patch add a check for extension starts with 'z' or 's' in `-march` option. Currently this unknown extension will be passed to the assembler, which then reports an error. With this patch, the compiler will throw a compilation error if the extension starts with 'z' or 's' is not a standard sub-extension or supervisor extension. Along with two extra changes. The first is to reduce repeated errors, which are currently reported at least twice. The second is to report as many mistakes as possible. e.g.: Run `riscv64-unknown-elf-gcc -march=rv64gvcw_zvl128_s123_x123 -mabi=lp64d a.c` will throw these error: riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': ISA string is not in canonical order. 'c' riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'w' is unsupported standard single letter extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'zvl128' start with `z` but is unsupported standard extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 's123' start with `s` but is unsupported standard supervisor extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'x123' start with `x` but is unsupported non-standard extension gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_supported_std_ext): Init. (standard_extensions_p): Add check. (riscv_subset_list::add): Just return NULL if it failed before. (riscv_subset_list::parse_std_ext): Continue parse when find a error (riscv_subset_list::parse): Just return NULL if it failed before. * config/riscv/riscv-subset.h (class riscv_subset_list): Add field. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-2.c: Update -march. * gcc.target/riscv/arch-3.c: Ditto. * gcc.target/riscv/arch-5.c: Ditto. * gcc.target/riscv/arch-8.c: Ditto. * gcc.target/riscv/attribute-10.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/attribute-19.c: Ditto. * gcc.target/riscv/attribute-8.c: Ditto. * gcc.target/riscv/attribute-9.c: Ditto. * gcc.target/riscv/pr102957.c: Ditto. * gcc.target/riscv/arch-22.cc: New test.
2023-07-17RISC-V: Ensure all implied extensions are included [PR110696]Lehua Ding1-3/+30
This patch fix target/PR110696, recursively add all implied extensions. PR target/110696 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions. (riscv_subset_list::check_implied_ext): Add new method. (riscv_subset_list::parse): Call checker check_implied_ext. * config/riscv/riscv-subset.h: Add new method. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/pr110696.c: New test. Signed-off-by: Lehua Ding <lehua.ding@rivai.ai>
2023-07-17Initial Lunar Lake, Arrow Lake and Arrow Lake S SupportMo, Zewei3-0/+27
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake, Arrow Lake and Arrow Lake S. * common/config/i386/i386-common.cc: (processor_name): Add arrowlake. (processor_alias_table): Add arrow lake, arrow lake s and lunar lake. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S. * config.gcc: Add -march=arrowlake and -march=arrowlake-s. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle arrowlake-s. * config/i386/i386-c.cc (ix86_target_macros_internal): Add arrowlake. * config/i386/i386-options.cc (m_ARROWLAKE): New. (processor_cost_table): Add arrowlake. * config/i386/i386.h (enum processor_type): Add PROCESSOR_ARROWLAKE. * config/i386/x86-tune.def: Add m_ARROWLAKE. * doc/extend.texi: Add arrowlake and arrowlake-s. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add arrowlake and arrowlake-s. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-07-17Support Intel SM4Haochen Jiang4-1/+23
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle -msm4. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM4. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sm4. * config.gcc: Add sm4intrin.h. * config/i386/cpuid.h (bit_SM4): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM4__. * config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4). * config/i386/i386-options.cc (isa2_opts): Add -msm4. (ix86_valid_target_attribute_inner_p): Handle sm4. * config/i386/i386.opt: Add option -msm4. * config/i386/immintrin.h: Include sm4intrin.h * config/i386/sse.md (vsm4key4_<mode>): New define insn. (vsm4rnds4_<mode>): Ditto. * doc/extend.texi: Document sm4. * doc/invoke.texi: Document -msm4. * doc/sourcebuild.texi: Document target sm4. * config/i386/sm4intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm4. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm4. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm4. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm4): New. * gcc.target/i386/sm4-1.c: New test. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/sm4key4-2.c: Ditto. * gcc.target/i386/sm4rnds4-2.c: Ditto.
2023-07-17Support Intel SHA512Haochen Jiang4-1/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512. (ix86_handle_option): Handle -msha512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SHA512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sha512. * config.gcc: Add sha512intrin.h. * config/i386/cpuid.h (bit_SHA512): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SHA512__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI. * config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512). * config/i386/i386-options.cc (isa2_opts): Add -msha512. (ix86_valid_target_attribute_inner_p): Handle sha512. * config/i386/i386.opt: Add option -msha512. * config/i386/immintrin.h: Include sha512intrin.h. * config/i386/sse.md (vsha512msg1): New define insn. (vsha512msg2): Ditto. (vsha512rnds2): Ditto. * doc/extend.texi: Document sha512. * doc/invoke.texi: Document -msha512. * doc/sourcebuild.texi: Document target sha512. * config/i386/sha512intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msha512. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msha512. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sha512. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sha512): New. * gcc.target/i386/sha512-1.c: New test. * gcc.target/i386/sha512-check.h: Ditto. * gcc.target/i386/sha512msg1-2.c: Ditto. * gcc.target/i386/sha512msg2-2.c: Ditto. * gcc.target/i386/sha512rnds2-2.c: Ditto.
2023-07-17Support Intel SM3Haochen Jiang4-1/+23
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle -msm3. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM3. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for SM3. * config.gcc: Add sm3intrin.h * config/i386/cpuid.h (bit_SM3): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM3__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4SI_FTYPE_V4SI_V4SI_V4SI_INT. * config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3). * config/i386/i386-options.cc (isa2_opts): Add -msm3. (ix86_valid_target_attribute_inner_p): Handle sm3. * config/i386/i386.opt: Add option -msm3. * config/i386/immintrin.h: Include sm3intrin.h. * config/i386/sse.md (vsm3msg1): New define insn. (vsm3msg2): Ditto. (vsm3rnds2): Ditto. * doc/extend.texi: Document sm3. * doc/invoke.texi: Document -msm3. * doc/sourcebuild.texi: Document target sm3. * config/i386/sm3intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm3. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Add new define for immediate. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm3. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm3. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm3): New. * gcc.target/i386/sm3-1.c: New test. * gcc.target/i386/sm3-check.h: Ditto. * gcc.target/i386/sm3msg1-2.c: Ditto. * gcc.target/i386/sm3msg2-2.c: Ditto. * gcc.target/i386/sm3rnds2-2.c: Ditto.
2023-07-17Support Intel AVX-VNNI-INT16Kong Lingling4-1/+26
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint16. * config.gcc: Add avxvnniint16.h. * config/i386/avxvnniint16intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT16): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT16__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16. (ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16). * config/i386/i386.opt: Add option -mavxvnniint16. * config/i386/immintrin.h: Include avxvnniint16.h. * config/i386/sse.md (vpdp<vpdpwprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint16. * doc/invoke.texi: Document -mavxvnniint16. * doc/sourcebuild.texi: Document target avxvnniint16. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint16 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint16. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint16): New. * gcc.target/i386/avxvnniint16-1.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusd-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsuds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuuds-2.c: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2023-07-14RISC-V: Recognized zihintntl extensionsMonk Chiang1-0/+4
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zihintntl item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro. (TARGET_ZIHINTNTL): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-22.c: New test. * gcc.target/riscv/predef-28.c: New test.
2023-07-12Initial Granite Rapids D SupportMo, Zewei3-1/+11
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Granite Rapids D. * common/config/i386/i386-common.cc: (processor_alias_table): Add graniterapids-d. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_GRANITERAPIDS_D. * config.gcc: Add -march=graniterapids-d. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle graniterapids-d. * config/i386/i386.h: (PTA_GRANITERAPIDS_D): New. * doc/extend.texi: Add graniterapids-d. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add graniterapids-d. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-07-04RISC-V: Add support for vector crypto extensionsChristoph Müllner1-0/+55
This series adds basic support for the vector crypto extensions: * Zvbb * Zvbc * Zvkg * Zvkned * Zvkhn[a,b] * Zvksed * Zvksh * Zvkn * Zvknc * Zvkng * Zvks * Zvksc * Zvksg * Zvkt This patch is based on the v20230620 version of the Vector Cryptography specification. The specification is frozen and can be found here: https://github.com/riscv/riscv-crypto/releases/tag/v20230620 Binutils support is merged as 9fdc1b157b6e72f7dd98851a240c5fdb386a558e. All extensions come with (passing) tests for the feature test macros. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add support for zvbb, zvbc, zvkg, zvkned, zvknha, zvknhb, zvksed, zvksh, zvkn, zvknc, zvkng, zvks, zvksc, zvksg, zvkt and the implied subsets. * config/riscv/arch-canonicalize: Add canonicalization info for zvkn, zvknc, zvkng, zvks, zvksc, zvksg. * config/riscv/riscv-opts.h (MASK_ZVBB): New macro. (MASK_ZVBC): Likewise. (TARGET_ZVBB): Likewise. (TARGET_ZVBC): Likewise. (MASK_ZVKG): Likewise. (MASK_ZVKNED): Likewise. (MASK_ZVKNHA): Likewise. (MASK_ZVKNHB): Likewise. (MASK_ZVKSED): Likewise. (MASK_ZVKSH): Likewise. (MASK_ZVKN): Likewise. (MASK_ZVKNC): Likewise. (MASK_ZVKNG): Likewise. (MASK_ZVKS): Likewise. (MASK_ZVKSC): Likewise. (MASK_ZVKSG): Likewise. (MASK_ZVKT): Likewise. (TARGET_ZVKG): Likewise. (TARGET_ZVKNED): Likewise. (TARGET_ZVKNHA): Likewise. (TARGET_ZVKNHB): Likewise. (TARGET_ZVKSED): Likewise. (TARGET_ZVKSH): Likewise. (TARGET_ZVKN): Likewise. (TARGET_ZVKNC): Likewise. (TARGET_ZVKNG): Likewise. (TARGET_ZVKS): Likewise. (TARGET_ZVKSC): Likewise. (TARGET_ZVKSG): Likewise. (TARGET_ZVKT): Likewise. * config/riscv/riscv.opt: Introduction of riscv_zv{b,k}_subext. gcc/testsuite/ChangeLog: * gcc.target/riscv/zvbb.c: New test. * gcc.target/riscv/zvbc.c: New test. * gcc.target/riscv/zvkg.c: New test. * gcc.target/riscv/zvkn-1.c: New test. * gcc.target/riscv/zvkn.c: New test. * gcc.target/riscv/zvknc-1.c: New test. * gcc.target/riscv/zvknc-2.c: New test. * gcc.target/riscv/zvknc.c: New test. * gcc.target/riscv/zvkned.c: New test. * gcc.target/riscv/zvkng-1.c: New test. * gcc.target/riscv/zvkng-2.c: New test. * gcc.target/riscv/zvkng.c: New test. * gcc.target/riscv/zvknha.c: New test. * gcc.target/riscv/zvknhb.c: New test. * gcc.target/riscv/zvks-1.c: New test. * gcc.target/riscv/zvks.c: New test. * gcc.target/riscv/zvksc-1.c: New test. * gcc.target/riscv/zvksc-2.c: New test. * gcc.target/riscv/zvksc.c: New test. * gcc.target/riscv/zvksed.c: New test. * gcc.target/riscv/zvksg-1.c: New test. * gcc.target/riscv/zvksg-2.c: New test. * gcc.target/riscv/zvksg.c: New test. * gcc.target/riscv/zvksh.c: New test. * gcc.target/riscv/zvkt.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-06-29x86: Update model values for Alderlake, Rocketlake and Raptorlake.Cui, Lili1-2/+1
Update model values for Alderlake, Rocketlake and Raptorlake according to SDM. gcc/ChangeLog * common/config/i386/cpuinfo.h (get_intel_cpu): Remove model value 0xa8 from Rocketlake, move model value 0xbf from Alderlake to Raptorlake.
2023-06-19avr: Fix wrong array bounds warning on SFR accessSenthil Kumar Selvaraj1-6/+0
The warning was raised on accessing SFRs at addresses below the default page size, as gcc considers accessing addresses in the first page of memory as suspicious. This doesn't apply to an embedded target like the avr, where both flash and RAM have zero as a valid address. Zero is also a valid address in named address spaces (__memx, flash<n> etc..). This commit implements TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID for the avr target and reports to gcc that zero is a valid address on all address spaces. It also disables flag_delete_null_pointer_checks based on the target hook, and modifies target-supports.exp to add avr to the list of targets that always keep null pointer checks. This fixes a bunch of DejaGNU failures that occur otherwise. PR target/105523 gcc/ChangeLog: * common/config/avr/avr-common.cc: Remove setting of OPT_fdelete_null_pointer_checks. * config/avr/avr.cc (avr_option_override): Clear flag_delete_null_pointer_checks if zero_address_valid. (avr_addr_space_zero_address_valid): New function. (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Provide target hook. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_keeps_null_pointer_checks): Add avr. * gcc.target/avr/pr105523.c: New test.
2023-06-01RISC-V: Introduce vfloat16m{f}*_t and their machine mode.Pan Li1-0/+2
This patch would like to introduce the built-in type vfloat16m{f}*_t, as well as their machine mode VNx*HF. They depend on architecture zvfhmin or zvfh. When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will be true. The underlying PATCH will implement the zvfhmin extension based on this. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin and zvfh. * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16. (main): Disable FP16 tuple. * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro. (TARGET_VECTOR_ELEN_FP_16): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add FP16. * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type. (vfloat16mf2_t): Ditto. (vfloat16m1_t): Ditto. (vfloat16m2_t): Ditto. (vfloat16m4_t): Ditto. (vfloat16m8_t): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16): New macro. * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16 machine mode based on TARGET_VECTOR_ELEN_FP_16.
2023-05-31RISC-V: Add ZVFH extension to the -march= optionPan Li1-0/+4
This patch would like to add new sub extension (aka ZVFH) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH. The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate more information about ZVFH from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfh item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFH): New macro. (TARGET_ZVFH): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-21.c: New test. * gcc.target/riscv/predef-27.c: New test.
2023-05-29RISC-V: Add ZVFHMIN extension to the -march= optionPan Li1-0/+3
This patch would like to add new sub extension (aka ZVFHMIN) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFHMIN. The Zvfhmin extension depends on the Zve32f extension. You can locate more information about ZVFHMIN from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfhmin item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro. (TARGET_ZFHMIN): Align indent. (TARGET_ZFH): Ditto. (TARGET_ZVFHMIN): New macro. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-20.c: New test. * gcc.target/riscv/predef-26.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-17RISC-V: Remove trailing spaces on lines.Jin Ma1-1/+1
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Remove trailing spaces on lines. * config/riscv/riscv.cc (riscv_legitimize_move): Likewise. * config/riscv/riscv.h (enum reg_class): Likewise. * config/riscv/riscv.md: Likewise.
2023-05-16rs6000: Enable REE pass by default“Ajit Kumar Agarwal”1-0/+2
Add ree pass as a default pass for rs6000 target for O2 and above. 2023-05-16 Ajit Kumar Agarwal <aagarwa1@linux.ibm.com> gcc/ChangeLog: * common/config/rs6000/rs6000-common.cc: Add REE pass as a default rs6000 target pass for O2 and above. * doc/invoke.texi: Document -free
2023-05-16RISC-V: Fix wrong select_kind in riscv_compute_multilibKito Cheng1-3/+3
Seems like I screw up bare-metal toolchian multi lib selection during finxing linux multi-lib selction... gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix wrong select_kind...
2023-05-12RISC-V: Suppress unused parameter warning in riscv-common.ccKito Cheng1-9/+3
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): Drop unused parameter. (riscv_select_multilib): Ditto. (riscv_compute_multilib): Update call site of riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.
2023-05-08RISC-V: Handle multi-lib path correclty for linuxKito Cheng1-40/+88
RISC-V Linux encodes the ABI into the path, so in theory, we can only use that to select multi-lib paths, and no way to use different multi-lib paths between `rv32i/ilp32` and `rv32ima/ilp32`, we'll mapping both to `/lib/ilp32`. It's hard to do that with GCC's builtin multi-lib selection mechanism; builtin mechanism did the option string compare and then enumerate all possible reuse rules during the build time. However, it's impossible to RISC-V; we have a huge number of combinations of `-march`, so implementing a customized multi-lib selection becomes the only solution. Multi-lib configuration is only used for determines which ISA should be used when compiling the corresponding ABI variant after this patch. During the multi-lib selection stage, only consider -mabi as the only key to select the multi-lib path. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): New. (riscv_select_multilib): New. (riscv_compute_multilib): Extract logic to riscv_select_multilib and also handle select_by_abi. * config/riscv/elf.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Change it to select_by_abi_arch_cmodel from 1. * config/riscv/linux.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Define. * config/riscv/riscv-opts.h (enum riscv_multilib_select_kind): New.
2023-04-20i386: Share AES xmm intrin with VAESHaochen Jiang1-1/+4
Currently in GCC, the 128 bit intrin for instruction vaes{end,dec}{last,} is under AES ISA. Because there is no dependency between ISA set AES and VAES, The 128 bit intrin is not available when we use compiler flag -mvaes -mavx512vl and there is no other way to use that intrin. But it should according to Intel SDM. Although VAES aims to be a VEX/EVEX promotion for AES, but it is only part of it. Therefore, we share the AES xmm intrin with VAES. Also, since -mvaes indicates that we could use VEX encoding for ymm, we should imply AVX for VAES. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX_UNSET): Add OPTION_MASK_ISA2_VAES_UNSET. (ix86_handle_option): Set AVX flag for VAES. * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Add OPTION_MASK_ISA2_VAES_UNSET. (def_builtin): Share builtin between AES and VAES. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Ditto. * config/i386/i386.md (aes): New isa attribute. * config/i386/sse.md (aesenc): Add pattern for VAES with xmm. (aesenclast): Ditto. (aesdec): Ditto. (aesdeclast): Ditto. * config/i386/vaesintrin.h: Remove redundant avx target push. * config/i386/wmmintrin.h (_mm_aesdec_si128): Change to macro. (_mm_aesdeclast_si128): Ditto. (_mm_aesenc_si128): Ditto. (_mm_aesenclast_si128): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fvl-vaes-1.c: Add VAES xmm test. * gcc.target/i386/pr109117-1.c: Modify error message.
2023-04-20i386: Add PCLMUL dependency for VPCLMULQDQHaochen Jiang1-3/+6
Currently in GCC, the 128 bit intrin for instruction vpclmulqdq is under PCLMUL ISA. Because there is no dependency between ISA set PCLMUL and VPCLMULQDQ, The 128 bit intrin is not available when we just use compiler flag -mvpclmulqdq. But it should according to Intel SDM. Since VPCLMULQDQ is a VEX/EVEX promotion for PCLMUL, it is natural to add dependency between them. Also, with -mvpclmulqdq, we can use ymm under VEX encoding, so VPCLMULQDQ should imply AVX. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA_VPCLMULQDQ_SET): Add OPTION_MASK_ISA_PCLMUL_SET and OPTION_MASK_ISA_AVX_SET. (OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_VPCLMULQDQ_UNSET. (OPTION_MASK_ISA_PCLMUL_UNSET): Ditto. * config/i386/i386.md (vpclmulqdqvl): New. * config/i386/sse.md (pclmulqdq): Add evex encoding. * config/i386/vpclmulqdqintrin.h: Remove redudant avx target push. gcc/testsuite/ChangeLog: * gcc.target/i386/vpclmulqdq.c: Add compile test for xmm.
2023-04-20i386: Add AVX512BW dependency to AVX512VBMI2Haochen Jiang1-3/+2
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVX512VBMI2_SET): Change OPTION_MASK_ISA_AVX512F_SET to OPTION_MASK_ISA_AVX512BW_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Remove OPTION_MASK_ISA_AVX512VBMI2_UNSET. (OPTION_MASK_ISA_AVX512BW_UNSET): Add OPTION_MASK_ISA_AVX512VBMI2_UNSET. * config/i386/avx512vbmi2intrin.h: Do not push avx512bw. * config/i386/avx512vbmi2vlintrin.h: Ditto. * config/i386/i386-builtin.def: Remove OPTION_MASK_ISA_AVX512BW. * config/i386/sse.md (VI12_AVX512VLBW): Removed. (VI12_VI48F_AVX512VLBW): Rename to VI12_VI48F_AVX512VL. (compress<mode>_mask): Change iterator from VI12_AVX512VLBW to VI12_AVX512VL. (compressstore<mode>_mask): Ditto. (expand<mode>_mask): Ditto. (expand<mode>_maskz): Ditto. (*expand<mode>_mask): Change iterator from VI12_VI48F_AVX512VLBW to VI12_VI48F_AVX512VL. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bw-pr100267-1.c: Remove avx512f and avx512bw. * gcc.target/i386/avx512bw-pr100267-b-2.c: Ditto. * gcc.target/i386/avx512bw-pr100267-d-2.c: Ditto. * gcc.target/i386/avx512bw-pr100267-q-2.c: Ditto. * gcc.target/i386/avx512bw-pr100267-w-2.c: Ditto. * gcc.target/i386/avx512f-vpcompressb-1.c: Ditto. * gcc.target/i386/avx512f-vpcompressb-2.c: Ditto. * gcc.target/i386/avx512f-vpcompressw-1.c: Ditto. * gcc.target/i386/avx512f-vpcompressw-2.c: Ditto. * gcc.target/i386/avx512f-vpexpandb-1.c: Ditto. * gcc.target/i386/avx512f-vpexpandb-2.c: Ditto. * gcc.target/i386/avx512f-vpexpandw-1.c: Ditto. * gcc.target/i386/avx512f-vpexpandw-2.c: Ditto. * gcc.target/i386/avx512f-vpshld-1.c: Ditto. * gcc.target/i386/avx512f-vpshldd-2.c: Ditto. * gcc.target/i386/avx512f-vpshldq-2.c: Ditto. * gcc.target/i386/avx512f-vpshldv-1.c: Ditto. * gcc.target/i386/avx512f-vpshldvd-2.c: Ditto. * gcc.target/i386/avx512f-vpshldvq-2.c: Ditto. * gcc.target/i386/avx512f-vpshldvw-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdd-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdq-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdv-1.c: Ditto. * gcc.target/i386/avx512f-vpshrdvd-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdvq-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdvw-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdw-2.c: Ditto. * gcc.target/i386/avx512vbmi2-vpshld-1.c: Ditto. * gcc.target/i386/avx512vbmi2-vpshrd-1.c: Ditto. * gcc.target/i386/avx512vl-vpcompressb-1.c: Ditto. * gcc.target/i386/avx512vl-vpcompressb-2.c: Ditto. * gcc.target/i386/avx512vl-vpcompressw-2.c: Ditto. * gcc.target/i386/avx512vl-vpexpandb-1.c: Ditto. * gcc.target/i386/avx512vl-vpexpandb-2.c: Ditto. * gcc.target/i386/avx512vl-vpexpandw-1.c: Ditto. * gcc.target/i386/avx512vl-vpexpandw-2.c: Ditto. * gcc.target/i386/avx512vl-vpshldd-2.c: Ditto. * gcc.target/i386/avx512vl-vpshldq-2.c: Ditto. * gcc.target/i386/avx512vl-vpshldv-1.c: Ditto. * gcc.target/i386/avx512vl-vpshldvd-2.c: Ditto. * gcc.target/i386/avx512vl-vpshldvq-2.c: Ditto. * gcc.target/i386/avx512vl-vpshldvw-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdd-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdq-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdv-1.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvd-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvq-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvw-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdw-2.c: Ditto. * gcc.target/i386/avx512vlbw-pr100267-1.c: Ditto. * gcc.target/i386/avx512vlbw-pr100267-b-2.c: Ditto. * gcc.target/i386/avx512vlbw-pr100267-w-2.c: Ditto.
2023-04-20i386: Add AVX512BW dependency to AVX512BITALGHaochen Jiang1-4/+4
Since some of the AVX512BITALG intrins use 32/64 bit mask, AVX512BW should be implied. gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVX512BITALG_SET): Change OPTION_MASK_ISA_AVX512F_SET to OPTION_MASK_ISA_AVX512BW_SET. (OPTION_MASK_ISA_AVX512F_UNSET): Remove OPTION_MASK_ISA_AVX512BITALG_SET. (OPTION_MASK_ISA_AVX512BW_UNSET): Add OPTION_MASK_ISA_AVX512BITALG_SET. * config/i386/avx512bitalgintrin.h: Do not push avx512bw. * config/i386/i386-builtin.def: Remove redundant OPTION_MASK_ISA_AVX512BW. * config/i386/sse.md (VI1_AVX512VLBW): Removed. (avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): Change the iterator from VI1_AVX512VLBW to VI1_AVX512VL. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bitalg-vpopcntb-1.c: Remove avx512bw. * gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto. * gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto. * gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto. * gcc.target/i386/pr93696-1.c: Ditto. * gcc.target/i386/pr93696-2.c: Ditto.
2023-04-18RISC-V: Adjust the parsing order of extensions to be consistent with ↵Jin Ma1-6/+6
riscv-spec and binutils. The current order of gcc and binutils parsing extensions is inconsistent. According to latest risc-v spec, the canonical order in which extension names must appear in the name string specified in Table 29.1 is different from before. In the latest table, non-standard extensions must be listed after all standard extensions. To keep consistent, we now change the parsing order. Related llvm patch links: https://reviews.llvm.org/D148315 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (multi_letter_subset_rank): Swap the order of z-extensions and s-extensions. (riscv_subset_list::parse): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-5.c: Likewise.
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang4-1/+23
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect AMX-COMPLEX. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_COMPLEX_SET, OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New. (ix86_handle_option): Handle -mamx-complex. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AMX_COMPLEX. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-complex. * config.gcc: Add amxcomplexintrin.h. * config/i386/cpuid.h (bit_AMX_COMPLEX): New. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AMX_COMPLEX__. * config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle amx-complex. * config/i386/i386.opt: Add option -mamx-complex. * config/i386/immintrin.h: Include amxcomplexintrin.h. * doc/extend.texi: Document amx-complex. * doc/invoke.texi: Document -mamx-complex. * doc/sourcebuild.texi: Document target amx-complex. * config/i386/amxcomplexintrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -mamx-complex. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/amx-check.h: Add cpu check for AMX-COMPLEX. * gcc.target/i386/amx-helper.h: Add amx-complex support. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mamx-complex. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add amx-complex. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_amx_complex): New. * gcc.target/i386/amxcomplex-asmatt-1.c: New test. * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto. * gcc.target/i386/amxcomplex-cmmimfp16ps-2.c: Ditto. * gcc.target/i386/amxcomplex-cmmrlfp16ps-2.c: Ditto.
2023-04-04riscv: Fix bootstrap [PR109384]Jakub Jelinek1-4/+3
The following patch unbreaks riscv bootstrap, where it previously failed on -Werror=format-diag warning promoted to error. Ok for trunk? Or shall it say e.g. "%<-march=%s%>: %<zfinx%> extension conflicts with %<f>" ? Or say if the current condition is true, do const char *ext = "zfinx"; if (subset_list->lookup ("zdinx")) ext = "zdinx"; else if (subset_list->lookup ("zhinx")) ext = "zhinx"; else if (subset_list->lookup ("zhinxmin")) ext = "zhinxmin"; and "%<-march=%s%>: %qs extension conflicts with %<f>", arch, ext ? Or do similar check for which extension to print against it, const char *ext = "zfinx"; const char *ext2 = "f"; if (subset_list->lookup ("zdinx")) { ext = "zdinx"; if (subset_list->lookup ("d")) ext2 = "d"; } else if (subset_list->lookup ("zhinx")) { ext = "zhinx"; if (subset_list->lookup ("zfh")) ext2 = "zfh"; } else if (subset_list->lookup ("zhinxmin")) { ext = "zhinxmin"; if (subset_list->lookup ("zfhmin")) ext2 = "zfhmin"; } "%<-march=%s%>: %qs extension conflicts with %qs", arch, ext, ext2 ? 2023-04-04 Jakub Jelinek <jakub@redhat.com> PR target/109384 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Reword diagnostics about zfinx conflict with f, formatting fixes. * gcc.target/riscv/arch-19.c: Expect a different message about zfinx vs. f conflict.
2023-03-29RISC-V: Add Z*inx imcompatible check in gccJiawei1-0/+5
Z*inx is conflict with float extensions, add incompatible check when z*inx and f extension both enabled. Since all float extension imply f extension and all z*inx extension imply zfinx extension, so we just need to check f with zfinx extension as the base case. Co-Authored by: Kito Cheng <kito.cheng@gmail.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New check. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-19.c: New test.
2023-03-15riscv: Add basic XThead* vendor extension supportChristoph Müllner1-0/+26
This patch add basic support for the following XThead* ISA extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadInt * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The extensions are just recognized by the compiler and feature test macros are generated (which this patch also brings tests for). gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add xthead* extensions. * config/riscv/riscv-opts.h (MASK_XTHEADBA): New. (MASK_XTHEADBB): New. (MASK_XTHEADBS): New. (MASK_XTHEADCMO): New. (MASK_XTHEADCONDMOV): New. (MASK_XTHEADFMEMIDX): New. (MASK_XTHEADFMV): New. (MASK_XTHEADINT): New. (MASK_XTHEADMAC): New. (MASK_XTHEADMEMIDX): New. (MASK_XTHEADMEMPAIR): New. (MASK_XTHEADSYNC): New. (TARGET_XTHEADBA): New. (TARGET_XTHEADBB): New. (TARGET_XTHEADBS): New. (TARGET_XTHEADCMO): New. (TARGET_XTHEADCONDMOV): New. (TARGET_XTHEADFMEMIDX): New. (TARGET_XTHEADFMV): New. (TARGET_XTHEADINT): New. (TARGET_XTHEADMAC): New. (TARGET_XTHEADMEMIDX): New. (TARGET_XTHEADMEMPAIR): new. (TARGET_XTHEADSYNC): New. * config/riscv/riscv.opt: Add riscv_xthead_subext. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba.c: New test. * gcc.target/riscv/xtheadbb.c: New test. * gcc.target/riscv/xtheadbs.c: New test. * gcc.target/riscv/xtheadcmo.c: New test. * gcc.target/riscv/xtheadcondmov.c: New test. * gcc.target/riscv/xtheadfmemidx.c: New test. * gcc.target/riscv/xtheadfmv.c: New test. * gcc.target/riscv/xtheadint.c: New test. * gcc.target/riscv/xtheadmac.c: New test. * gcc.target/riscv/xtheadmemidx.c: New test. * gcc.target/riscv/xtheadmempair.c: New test. * gcc.target/riscv/xtheadsync.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-02-13arc: Don't use millicode thunks unless asked for.Claudiu Zissulescu1-1/+0
ARC has enter_s/leave_s instructions which can save/restore the entire function context. It is not needed the millicode thunks anylonger when compiling for size, thus, make their usage optional. gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove millicode from list. gcc/testsuite/ * gcc.target/arc/milli-1.c: Update test.
2023-02-12RISC-V: Add vmulh C/C++ supportJu-Zhe Zhong1-0/+1
Co-authored-by: kito-cheng <kito.cheng@sifive.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add flag for 'V' extension. * config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vmulh): Add vmulh API support. (vmulhu): Ditto. (vmulhsu): Ditto. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_FULL_V_I_OPS): New macro. (DEF_RVV_FULL_V_U_OPS): Ditto. (vint8mf8_t): Ditto. (vint8mf4_t): Ditto. (vint8mf2_t): Ditto. (vint8m1_t): Ditto. (vint8m2_t): Ditto. (vint8m4_t): Ditto. (vint8m8_t): Ditto. (vint16mf4_t): Ditto. (vint16mf2_t): Ditto. (vint16m1_t): Ditto. (vint16m2_t): Ditto. (vint16m4_t): Ditto. (vint16m8_t): Ditto. (vint32mf2_t): Ditto. (vint32m1_t): Ditto. (vint32m2_t): Ditto. (vint32m4_t): Ditto. (vint32m8_t): Ditto. (vint64m1_t): Ditto. (vint64m2_t): Ditto. (vint64m4_t): Ditto. (vint64m8_t): Ditto. (vuint8mf8_t): Ditto. (vuint8mf4_t): Ditto. (vuint8mf2_t): Ditto. (vuint8m1_t): Ditto. (vuint8m2_t): Ditto. (vuint8m4_t): Ditto. (vuint8m8_t): Ditto. (vuint16mf4_t): Ditto. (vuint16mf2_t): Ditto. (vuint16m1_t): Ditto. (vuint16m2_t): Ditto. (vuint16m4_t): Ditto. (vuint16m8_t): Ditto. (vuint32mf2_t): Ditto. (vuint32m1_t): Ditto. (vuint32m2_t): Ditto. (vuint32m4_t): Ditto. (vuint32m8_t): Ditto. (vuint64m1_t): Ditto. (vuint64m2_t): Ditto. (vuint64m4_t): Ditto. (vuint64m8_t): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FULL_V_I_OPS): Ditto. (DEF_RVV_FULL_V_U_OPS): Ditto. (check_required_extensions): Add vmulh support. (rvv_arg_type_info::get_tree_type): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_FULL_V): Ditto. (enum rvv_base_type): Ditto. * config/riscv/riscv.opt: Add 'V' extension flag. * config/riscv/vector-iterators.md (su): New iterator. * config/riscv/vector.md (@pred_mulh<v_su><mode>): New pattern. (@pred_mulh<v_su><mode>_scalar): Ditto. (*pred_mulh<v_su><mode>_scalar): Ditto. (*pred_mulh<v_su><mode>_extended_scalar): Ditto.
2023-02-09i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]Jakub Jelinek1-16/+9
get_available_features doesn't depend on cpu_model2->__cpu_{family,model} and just sets stuff up based on CPUID leaf 1, or some extended ones, so I wonder why are we calling it separately for Intel, AMD and Zhaoxin and not for all other CPUs too? I think various programs in the wild which aren't using __builtin_cpu_{is,supports} just check the various CPUID leafs and query bits in there, without blacklisting unknown CPU vendors, so I think even __builtin_cpu_supports ("sse2") etc. should be reliable if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID leaf 1 or some extended ones. Calling it for all CPUs also means it can be inlined because there will be just a single caller. I have tested it on Intel and Martin tested it on AMD, but can't test it on non-Intel/AMD; for Intel/AMD/Zhaoxin it should be really no change in behavior. 2023-02-09 Jakub Jelinek <jakub@redhat.com> PR target/100758 * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes. (cpu_indicator_init): Call get_available_features for all CPUs with max_level >= 1, rather than just Intel, AMD or Zhaoxin. Formatting fixes.
2023-02-02RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.Jin Ma1-1/+4
MAX_MATCH_SCORE is not assigned anywhere except initialized to 0, causing BEST_MATCH_MULTI_LIB to always be 0 or -1, which will cause the result of TARGET_COMPUTE_MULTILIB hook to fail. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix finding best match score.
2023-02-01AArch64: Fix native detection in the presence of mandatory features which ↵Tamar Christina1-5/+17
don't have midr values aarch64-option-extensions.def explicitly defines the semantics for an empty midr field as being: In that case this field should contain a space (" ") separated list of the strings in 'Features' that are required. Their order is not important. An empty string means do not detect this feature during auto detection. That is to say, an empty string means that we don't know the midr value for this feature and so it just shouldn't be taken into account for native features detection. However this meaning seems to have gotten lost at some point. This results in e.g. -mcpu=native on a Neoverse N2 disabling features it does have. Essentially we disabled any mandatory feature for which there is no midr entry. The rationale for having -mcpu=native being able to disable features at all, is because the kernel is able to disable a mandatory feature for correctness issues. Unfortunately we can't distinguish between "old kernel" and "kernel disabled". This patch adds a new field that indicates whether the midr field has any value at all. If there's no value we skip the extension when determining the "off" flags. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_option_extension): Add native_detect and document struct a bit more. (all_extensions): Set new field native_detect. * config/aarch64/aarch64.cc (struct aarch64_option_extension): Delete unused struct. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cpunative/info_19: New test. * gcc.target/aarch64/cpunative/info_20: New test. * gcc.target/aarch64/cpunative/info_21: New test. * gcc.target/aarch64/cpunative/info_22: New test. * gcc.target/aarch64/cpunative/native_cpu_19.c: New test. * gcc.target/aarch64/cpunative/native_cpu_20.c: New test. * gcc.target/aarch64/cpunative/native_cpu_21.c: New test. * gcc.target/aarch64/cpunative/native_cpu_22.c: New test.
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab1-0/+4
This follows the example of aarch64. gcc/: * common/config/riscv/riscv-common.cc (riscv_option_optimization_table) [TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable -fasynchronous-unwind-tables and -funwind-tables. * config.gcc (riscv*-*-linux*): Define TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo1-6/+7
Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the movement of all branch protection parsing routines from aarch64.c to aarch-common.c and supporting data types and static data structures. This patch also pre-declares variables and types required in the aarch32 back-end for moved variables for function sign scope and key to prepare for the impending series of patches that support parsing the feature mbranch-protection in the aarch32 back-end. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc: Include aarch-common.h. (all_architectures): Fix comment. (aarch64_parse_extension): Rename return type, enum value names. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename factored out aarch_ra_sign_scope and aarch_ra_sign_key variables. Also rename corresponding enum values. * config/aarch64/aarch64-opts.h (aarch64_function_type): Factor out aarch64_function_type and move it to common code as aarch_function_type in aarch-common.h. * config/aarch64/aarch64-protos.h: Include common types header, move out types aarch64_parse_opt_result and aarch64_key_type to aarch-common.h * config/aarch64/aarch64.cc: Move mbranch-protection parsing types and functions out into aarch-common.h and aarch-common.cc. Fix up all the name changes resulting from the move. * config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change and enum value. * config/aarch64/aarch64.opt: Include aarch-common.h to import type move. Fix up name changes from factoring out common code and data. * config/arm/aarch-common-protos.h: Export factored out routines to both backends. * config/arm/aarch-common.cc: Include newly factored out types. Move all mbranch-protection code and data structures from aarch64.cc. * config/arm/aarch-common.h: New header that declares types shared between aarch32 and aarch64 backends. * config/arm/arm-protos.h: Declare types and variables that are made common to aarch64 and aarch32 backends - aarch_ra_sign_key, aarch_ra_sign_scope and aarch_enable_bti. * config/arm/arm.opt (config/arm/aarch-common.h): Include header. (aarch_ra_sign_scope, aarch_enable_bti): Declare variable. * config/arm/arm.cc: Add missing includes. Co-Authored-By: Tejas Belagod <tbelagod@arm.com>
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