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From-SVN: r256169
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PR target/83488
* config/i386/i386.opt (-mavx512vpopcntdq, -mmavx512bitalg): Move from
ix86_isa_flags2 to ix86_isa_flags.
* config/i386/i386-c.c (ix86_target_macros_internal): Test
OPTION_MASK_ISA_AVX512BITALG and OPTION_MASK_ISA_AVX512VPOPCNTDQ in
isa_flags rather than isa_flags2.
* config/i386/i386.c (ix86_target_string): Move -mavx512vpopcntdq
and -mavx512bitalg from isa2_opts to isa_opts.
(ix86_option_override_internal): Test OPTION_MASK_ISA_AVX512VPOPCNTDQ
in x_ix86_isa_flags_explicit rather than x_ix86_isa_flags2_explicit
and set it in x_ix86_isa_flags rather than x_ix86_isa_flags2.
Formatting fixes.
(def_builtin): Treat OPTION_MASK_ISA_AVX512BW or
OPTION_MASK_ISA_AVX512F ored with another option similarly to
OPTION_MASK_ISA_AVX512VL. Even for OPTION_MASK_ISA_AVX512VL don't
clear it if mask is just OPTION_MASK_ISA_AVX512VL itself.
(ix86_expand_builtin): Don't handle OPTION_MASK_ISA_GFNI and
OPTION_MASK_ISA_VPCLMULQDQ specially, instead handle
OPTION_MASK_ISA_AVX512BW and OPTION_MASK_ISA_AVX512F that way.
* config/i386/i386-builtin.def: Move AVX512VPOPCNTDQ and AVX512BITALG
builtins from bdesc_args2 to bdesc_args section.
(__builtin_ia32_compressstoreuqi512_mask,
__builtin_ia32_compressstoreuhi512_mask,
__builtin_ia32_compressstoreuqi256_mask,
__builtin_ia32_expandloadqi512_mask,
__builtin_ia32_expandloadqi512_maskz,
__builtin_ia32_expandloadhi512_mask,
__builtin_ia32_expandloadhi512_maskz,
__builtin_ia32_compressqi512_mask, __builtin_ia32_compresshi512_mask,
__builtin_ia32_compressqi256_mask, __builtin_ia32_expandqi512_mask,
__builtin_ia32_expandqi512_maskz, __builtin_ia32_expandhi512_mask,
__builtin_ia32_expandhi512_maskz, __builtin_ia32_expandqi256_mask,
__builtin_ia32_expandqi256_maskz, __builtin_ia32_vpshrd_v32hi_mask,
__builtin_ia32_vpshld_v32hi_mask, __builtin_ia32_vpshrdv_v32hi_mask,
__builtin_ia32_vpshrdv_v32hi_maskz, __builtin_ia32_vpshldv_v32hi_mask,
__builtin_ia32_vpshldv_v32hi_maskz,
__builtin_ia32_vpopcountb_v64qi_mask,
__builtin_ia32_vpopcountw_v32hi_mask,
__builtin_ia32_vpshufbitqmb512_mask,
__builtin_ia32_vpshufbitqmb256_mask): Add
" | OPTION_MASK_ISA_AVX512BW".
(__builtin_ia32_expandloadqi256_mask,
__builtin_ia32_expandloadqi256_maskz,
__builtin_ia32_vpopcountb_v32qi_mask): Add
" | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW".
(__builtin_ia32_expandloadhi256_mask,
__builtin_ia32_expandloadhi256_maskz,
__builtin_ia32_expandloadqi128_mask,
__builtin_ia32_expandloadqi128_maskz,
__builtin_ia32_expandloadhi128_mask,
__builtin_ia32_expandloadhi128_maskz,
__builtin_ia32_vpshrd_v16hi, __builtin_ia32_vpshrd_v16hi_mask,
__builtin_ia32_vpshrd_v8hi, __builtin_ia32_vpshrd_v8hi_mask,
__builtin_ia32_vpshrd_v8si, __builtin_ia32_vpshrd_v8si_mask,
__builtin_ia32_vpshrd_v4si, __builtin_ia32_vpshrd_v4si_mask,
__builtin_ia32_vpshrd_v4di, __builtin_ia32_vpshrd_v4di_mask,
__builtin_ia32_vpshrd_v2di, __builtin_ia32_vpshrd_v2di_mask,
__builtin_ia32_vpshld_v16hi, __builtin_ia32_vpshld_v16hi_mask,
__builtin_ia32_vpshld_v8hi, __builtin_ia32_vpshld_v8hi_mask,
__builtin_ia32_vpshld_v8si, __builtin_ia32_vpshld_v8si_mask,
__builtin_ia32_vpshld_v4si, __builtin_ia32_vpshld_v4si_mask,
__builtin_ia32_vpshld_v4di, __builtin_ia32_vpshld_v4di_mask,
__builtin_ia32_vpshld_v2di, __builtin_ia32_vpshld_v2di_mask,
__builtin_ia32_vpshrdv_v16hi, __builtin_ia32_vpshrdv_v16hi_mask,
__builtin_ia32_vpshrdv_v16hi_maskz, __builtin_ia32_vpshrdv_v8hi,
__builtin_ia32_vpshrdv_v8hi_mask, __builtin_ia32_vpshrdv_v8hi_maskz,
__builtin_ia32_vpshrdv_v8si, __builtin_ia32_vpshrdv_v8si_mask,
__builtin_ia32_vpshrdv_v8si_maskz, __builtin_ia32_vpshrdv_v4si,
__builtin_ia32_vpshrdv_v4si_mask, __builtin_ia32_vpshrdv_v4si_maskz,
__builtin_ia32_vpshrdv_v4di, __builtin_ia32_vpshrdv_v4di_mask,
__builtin_ia32_vpshrdv_v4di_maskz, __builtin_ia32_vpshrdv_v2di,
__builtin_ia32_vpshrdv_v2di_mask, __builtin_ia32_vpshrdv_v2di_maskz,
__builtin_ia32_vpshldv_v16hi, __builtin_ia32_vpshldv_v16hi_mask,
__builtin_ia32_vpshldv_v16hi_maskz, __builtin_ia32_vpshldv_v8hi,
__builtin_ia32_vpshldv_v8hi_mask, __builtin_ia32_vpshldv_v8hi_maskz,
__builtin_ia32_vpshldv_v8si, __builtin_ia32_vpshldv_v8si_mask,
__builtin_ia32_vpshldv_v8si_maskz, __builtin_ia32_vpshldv_v4si,
__builtin_ia32_vpshldv_v4si_mask, __builtin_ia32_vpshldv_v4si_maskz,
__builtin_ia32_vpshldv_v4di, __builtin_ia32_vpshldv_v4di_mask,
__builtin_ia32_vpshldv_v4di_maskz, __builtin_ia32_vpshldv_v2di,
__builtin_ia32_vpshldv_v2di_mask, __builtin_ia32_vpshldv_v2di_maskz,
__builtin_ia32_vpopcountb_v32qi, __builtin_ia32_vpopcountb_v16qi,
__builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v16hi,
__builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi,
__builtin_ia32_vpopcountw_v8hi_mask): Add
" | OPTION_MASK_ISA_AVX512VL".
* config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16,
_mm512_shrdi_epi32, _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
_mm512_shrdi_epi64, _mm512_mask_shrdi_epi64, _mm512_maskz_shrdi_epi64,
_mm512_shldi_epi16, _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
_mm512_maskz_shldi_epi32, _mm512_shldi_epi64, _mm512_mask_shldi_epi64,
_mm512_maskz_shldi_epi64, _mm512_shrdv_epi16, _mm512_shrdv_epi32,
_mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64,
_mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64, _mm512_shldv_epi16,
_mm512_shldv_epi32, _mm512_mask_shldv_epi32, _mm512_maskz_shldv_epi32,
_mm512_shldv_epi64, _mm512_mask_shldv_epi64,
_mm512_maskz_shldv_epi64): Don't require avx512bw for these intrinsics.
* config/i386/avx512bitalgintrin.h (_mm_bitshuffle_epi64_mask,
_mm_mask_bitshuffle_epi64_mask): Likewise.
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET,
OPTION_MASK_ISA_AVX512BITALG_SET): Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET and
OPTION_MASK_ISA_AVX512BITALG_UNSET.
(OPTION_MASK_ISA2_AVX512F_UNSET,
OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Define.
(ix86_handle_option): For -mno-general-regs-only, clear from
ix86_isa_flags2 OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET rather than
just OPTION_MASK_ISA_MPX. For -mno-sse{,2,3,4,4.1,4.2,avx,avx2} and
-mno-ssse3 clear OPTION_MASK_ISA2_AVX512F_UNSET bits from
ix86_isa_flags2. For -mno-avx512f likewise, instead of masking
individually listed ISAs. For -m{,no-}avx512{vpopcntdq,bitalg} adjust
for moving from ix86_isa_flags2 to ix86_isa_flags.
From-SVN: r255997
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gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512BITALG_SET,
OPTION_MASK_ISA_AVX512BITALG_UNSET): New.
(ix86_handle_option): Handle -mavx512bitalg, fix 4VNNIW formatting.
* config.gcc: Add avx512vpopcntdqvlintrin.h and avx512bitalgintrin.h.
* config/i386/avx512bitalgintrin.h (_mm512_popcnt_epi8, _mm512_popcnt_epi16,
_mm512_mask_popcnt_epi8, _mm512_maskz_popcnt_epi8, _mm512_mask_popcnt_epi16,
_mm512_maskz_popcnt_epi16, _mm512_bitshuffle_epi64_mask, _mm256_popcnt_epi8,
_mm512_mask_bitshuffle_epi64_mask, _mm256_mask_popcnt_epi8, _mm_popcnt_epi8,
_mm256_maskz_popcnt_epi8, _mm_bitshuffle_epi64_mask, _mm256_popcnt_epi16,
_mm_mask_bitshuffle_epi64_mask, _mm256_bitshuffle_epi64_mask,
_mm256_mask_bitshuffle_epi64_mask, _mm_popcnt_epi16, _mm_maskz_popcnt_epi8,
_mm256_mask_popcnt_epi16, _mm256_maskz_popcnt_epi16, _mm_mask_popcnt_epi8,
_mm_mask_popcnt_epi16, _mm_maskz_popcnt_epi16): New intrinsics.
* config/i386/avx512vpopcntdqvlintrin.h (_mm_popcnt_epi32, _mm_popcnt_epi64,
_mm_mask_popcnt_epi32, _mm_maskz_popcnt_epi32, _mm256_popcnt_epi32,
_mm256_mask_popcnt_epi32, _mm256_maskz_popcnt_epi32, _mm_mask_popcnt_epi64,
_mm_maskz_popcnt_epi64, _mm256_popcnt_epi64, _mm256_mask_popcnt_epi64,
_mm256_maskz_popcnt_epi64): New intrinsics.
* config/i386/cpuid.h (bit_AVX512BITALG): New bit.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect -mavx512bitalg.
* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI, V64QI_FTYPE_V64QI,
V4DI_FTYPE_V4DI, UHI_FTYPE_V2DI_V2DI_UHI, USI_FTYPE_V4DI_V4DI_USI,
V4SI_FTYPE_V4SI_V4SI_UHI, V8SI_FTYPE_V8SI_V8SI_UHI): New types.
* config/i386/i386-builtin.def (__builtin_ia32_vpopcountq_v4di,
__builtin_ia32_vpopcountq_v4di_mask, __builtin_ia32_vpopcountq_v2di,
__builtin_ia32_vpopcountq_v2di_mask, __builtin_ia32_vpopcountd_v4si,
__builtin_ia32_vpopcountd_v4si_mask, __builtin_ia32_vpopcountd_v8si,
__builtin_ia32_vpopcountd_v8si_mask, __builtin_ia32_vpopcountb_v64qi,
__builtin_ia32_vpopcountb_v64qi_mask, __builtin_ia32_vpopcountb_v32qi,
__builtin_ia32_vpopcountb_v32qi_mask, __builtin_ia32_vpopcountb_v16qi,
__builtin_ia32_vpopcountb_v16qi_mask, __builtin_ia32_vpopcountw_v32hi,
__builtin_ia32_vpopcountw_v32hi_mask, __builtin_ia32_vpopcountw_v16hi,
__builtin_ia32_vpopcountw_v16hi_mask, __builtin_ia32_vpopcountw_v8hi,
__builtin_ia32_vpopcountw_v8hi_mask, __builtin_ia32_vpshufbitqmb128_mask,
__builtin_ia32_vpshufbitqmb256_mask,
__builtin_ia32_vpshufbitqmb512_mask): New builtins.
* config/i386/i386-c.c (__AVX512BITALG__): New.
* config/i386/i386.c (isa2_opts): Add -mavx512bitalg.
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_expand_args_builtin): Handle new types.
* config/i386/i386.h (TARGET_AVX512BITALG, TARGET_AVX512BITALG_P): New.
* config/i386/i386.opt: Add -mavx512bitalg.
* config/i386/immintrin.h: Add avx512vpopcntdqvlintrin.h and
avx512bitalgintrin.h.
* config/i386/sse.md (VI48_AVX512VLBW): New iterator.
(vpopcount<mode><mask_name>): Add more types.
(avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): New.
* doc/invoke.texi: Add -mavx512bitalg and -mavx512vpopcntdq.
gcc/testsuite/
* g++.dg/other/i386-2.C: Add new options.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx512-check.h: Handle bit_AVX512BITALG.
* gcc.target/i386/avx512bitalg-vpopcntb-1.c: New.
* gcc.target/i386/avx512bitalg-vpopcntb.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntbvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntw.c: Ditto.
* gcc.target/i386/avx512bitalg-vpopcntwvl.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512bitalg-vpshufbitqmb.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto.
* gcc.target/i386/avx512bitalgvl-vpshufbitqmb-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntd-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdqvl-vpopcntq-1.c: Ditto.
* gcc.target/i386/i386.exp (check_effective_target_avx512bitalg): New.
* gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Add more types.
* gcc.target/i386/avx512vpopcntdq-vpopcntd.c: Handle new intrinsics.
* gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto.
Co-Authored-By: Sebastian Peryt <sebastian.peryt@intel.com>
From-SVN: r255975
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This is a follow up patch for pr83488 to fix an error in setting
OPTION_MASK_ISA_AVX512VNNI_SET and OPTION_MASK_ISA_AVX512F_SET bits.
There were both set in ix86_isa_flags2 while being defined in
different ISA sets. Additionally move OPTION_MASK_ISA_AVX512VNNI_SET
to ix86_isa_flags as it can be used with OPTION_MASK_ISA_AVX512VL_SET.
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VNNI_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_AVX512VNNI_*SET being in ix86_isa_flags.
* config/i386/i386-builtin.def: Move VNNI builtins from ARGS2
section to ARGS.
* config/i386/i386-c.c: Check for OPTION_MASK_ISA_AVX512VNNI in
isa_flag instead of isa_flag2.
* config/i386/i386.c (ix86_target_string): Move -mavx512vnni from
isa_opts2 to isa_opts.
* config/i386/i386.opt (mavx512vnni): Move from ix86_isa_flags2
to ix86_isa_flags.
From-SVN: r255974
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* common/config/arm/arm-common.c (compare_opt_names): Add function
comment. Use strcmp instead of manual loop.
From-SVN: r255942
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PR target/83488
* config/i386/i386.c (ix86_target_string): Move -mavx512vbmi2 and
-mshstk entries from isa_opts2 to isa_opts and -mhle, -mmovbe,
-mclzero and -mmwaitx entries from isa_opts to isa_opts2.
(ix86_option_override_internal): Adjust for
OPTION_MASK_ISA_{HLE,MOVBE,CLZERO,MWAITX} moving to ix86_isa_flags2
and OPTION_MASK_ISA_SHSTK moving to ix86_isa_flags.
(BDESC_VERIFYS): Remove SPECIAL_ARGS2 related checks.
(ix86_init_mmx_sse_builtins): Remove bdesc_special_args2 handling.
Use def_builtin2 instead of def_builtin for OPTION_MASK_ISA_MWAITX
and OPTION_MASK_ISA_CLZERO builtins. Use def_builtin instead of
def_builtin2 for CET builtins.
(ix86_expand_builtin): Remove bdesc_special_args2 handling. Fix
up formatting in IX86_BUILTIN_RDPID code.
* config/i386/i386-builtin.def: Move VBMI2 builtins from SPECIAL_ARGS2
section to SPECIAL_ARGS and from ARGS2 section to ARGS.
* config/i386/i386.opt (mavx512vbmi2, mshstk): Move from
ix86_isa_flags2 to ix86_isa_flags.
(mhle, mmovbe, mclzero, mmwaitx): Move from ix86_isa_flags to
ix86_isa_flags2.
* config/i386/i386-c.c (ix86_target_macros_internal): Check for
OPTION_MASK_ISA_{CLZERO,MWAITX} in isa_flag2 instead of isa_flag.
Check for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2} in isa_flag instead
of isa_flag2.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VBMI2_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_{SHSTK,AVX512VBMI2}_*SET being in ix86_isa_flags
and OPTION_MASK_ISA_{MOVBE,MWAITX,CLZERO}_*SET in ix86_isa_flags2.
* gcc.target/i386/pr83488.c: New test.
From-SVN: r255937
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gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET,
OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New.
(ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2.
* config.gcc: Include vpclmulqdqintrin.h.
* config/i386/cpuid.h: Handle bit_VPCLMULQDQ.
* config/i386/driver-i386.c (host_detect_local_cpu): Handle -mvpclmulqdq.
* config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di,
__builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New.
* config/i386/i386-c.c (__VPCLMULQDQ__): New.
* config/i386/i386.c (isa2_opts): Add -mcx16.
(isa_opts): Add -mpclmulqdq, remove -mcx16.
(ix86_option_override_internal): Move mcx16 to flags2.
(ix86_valid_target_attribute_inner_p): Add vpclmulqdq.
(ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ.
* config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New.
* config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2.
* config/i386/immintrin.h: Include vpclmulqdqintrin.h.
* config/i386/sse.md (vpclmulqdq_<mode>): New pattern.
* config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128,
_mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics.
* doc/invoke.texi: Add -mvpclmulqdq.
gcc/testsuite/
* gcc.target/i386/avx-1.c: Handle new intrinsics.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx512-check.h: Handle bit_VPCLMULQDQ.
* gcc.target/i386/avx512f-vpclmulqdq-2.c: New test.
* gcc.target/i386/avx512vl-vpclmulqdq-2.c: Ditto.
* gcc.target/i386/vpclmulqdq.c: Ditto.
* gcc.target/i386/i386.exp (check_effective_target_vpclmulqdq): New.
From-SVN: r255850
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gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET,
OPTION_MASK_ISA_VAES_UNSET): New.
(ix86_handle_option): Handle -mvaes.
* config/i386/cpuid.h: Define bit_VAES.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect -mvaes.
* config/i386/i386-c.c (__VAES__): New.
* config/i386/i386.c (ix86_target_string): Add -mvaes.
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.h (TARGET_VAES, TARGET_VAES_P): New.
* config/i386/i386.opt: Add -mvaes.
* doc/invoke.texi: Ditto.
From-SVN: r255571
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When GCC invokes the assembler it generates a sanitized version of the
user-specified -march option to pass through, since the assembler does
not understand all the new FPU-related architectural options.
Unfortunately it goes too far and strips off all the architectural
extensions, including some that are unrelated to the -mfpu variant
selected.
Again, this doesn't really matter when compiling C code because the
compiler will override the command-line specified architecture with
directives in the assembly file itself, but when using the compiler
driver to invoke the assembler the only indiciation of the desired
architecture might come from the command line.
We fix this by adjusting the canonicalization pass to remove any
option that only specifies features that can be expressed by -mfpu
(any that go beyond that are already supported by the assembler). We
do have to take care to re-order the options, though as the assembler
expects feature options to be in a canonical order (unlike the
compiler, where ordering is handled left-to-right: there's only a
difference if there are negation options, but a canonicalized
architecture string shouldn't have any of those). We do this by
recording which options we need and then sorting the final list
alphabetically.
* common/config/arm/arm-common.c: Include <algorithm>.
(INCLUDE_VECTOR): Define.
(compare_opt_names): New function.
(arm_rewrite_selected_arch): Only strip out extensions that can be
expressed through -mfpu. Sort the remaining extensions
alphabetically.
From-SVN: r255503
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When gcc runs with the new -mfpu=auto option (either explicitly or
when that's the default behaviour) then this option is not passed
through to the assembler as we cannot rely on the assembler
understanding it (currently it doesn't understand it at all, but in
future that might change). That means that the assembler falls back
to its builtin default, which may not correspond to what the user
expected based on the command-line options they passed.
Normally that wouldn't matter because assembler files generated by the
compiler will contain explicit directives that set the FPU type
directly and override any internal defaults; but when the compiler
driver is used to invoke the assembler directly (because the source
file ends in .s or .S) then this might cause a problem if that assumes
the FPU matches the compiler.
To address this, this patch makes the driver construct a -mfpu= option
for the assembler in the same way as the compiler generates an
internal .fpu directive. As mentioned, this makes no difference if
the assembler file explicitly overrides the command line options, but
helps in the case where this is implicit.
* config/arm/arm.h (arm_asm_auto_mfpu): Declare.
(ASM_CPU_SPEC_FUNCTIONS): Add new rule asm_auto_mfpu.
(ASM_CPU_SPEC): Use it if -mfpu is set to auto.
* common/config/arm/arm-common.c (arm_asm_auto_mfpu): New function.
-- This line, and those below, will be ignored--
M gcc/ChangeLog
M gcc/common/config/arm/arm-common.c
M gcc/config/arm/arm.h
From-SVN: r255502
|
|
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET,
OPTION_MASK_ISA_AVX512VNNI_UNSET): New.
(ix86_handle_option): Handle -mavx512vnni.
* config/i386/cpuid.h (bit_AVX512VNNI): New bit.
* config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit.
* config/i386/i386-c (__AVX512VNNI__): New.
* config/i386/i386.c (ix86_target_string): Handle new option.
(ix86_valid_target_attribute_inner_p): Handle new option.
* config/i386/i386.h (TARGET_AVX512VNNI, TARGET_AVX512VNNI_P): New.
* config/i386/i386.opt (mavx512vnni): New option.
From-SVN: r255401
|
|
Almost all targets add an explict -fomit-frame-pointer in the target specific
options. Rather than doing this in a target-specific way, do this in the
generic options so it works identically across all targets. In many cases the
target no longer needs to define TARGET_OPTION_OPTIMIZATION_TABLE, reducing
the amount of target code.
gcc/
* opts.c (default_options_table): Add OPT_fomit_frame_pointer entry.
* common/config/alpha/alpha-common.c (TARGET_OPTION_OPTIMIZATION_TABLE):
Remove OPT_fomit_frame_pointer entry.
* common/config/arc/arc-common.c: Likewise.
* common/config/arm/arm-common.c: Likewise.
* common/config/avr/avr-common.c: Likewise.
* common/config/c6x/c6x-common.c: Likewise.
* common/config/cr16/cr16-common.c: Likewise.
* common/config/cris/cris-common.c: Likewise.
* common/config/epiphany/epiphany-common.c: Likewise.
* common/config/fr30/fr30-common.c: Likewise.
* common/config/frv/frv-common.c: Likewise.
* common/config/ia64/ia64-common.c: Likewise.
* common/config/iq2000/iq2000-common.c: Likewise.
* common/config/lm32/lm32-common.c: Likewise.
* common/config/m32r/m32r-common.c: Likewise.
* common/config/mcore/mcore-common.c: Likewise.
* common/config/microblaze/microblaze-common.c: Likewise.
* common/config/mips/mips-common.c: Likewise.
* common/config/mmix/mmix-common.c: Likewise.
* common/config/mn10300/mn10300-common.c: Likewise.
* common/config/nios2/nios2-common.c: Likewise.
* common/config/pa/pa-common.c: Likewise.
* common/config/pdp11/pdp11-common.c: Likewise.
* common/config/powerpcspe/powerpcspe-common.c: Likewise.
* common/config/riscv/riscv-common.c: Likewise.
* common/config/rs6000/rs6000-common.c: Likewise.
* common/config/rx/rx-common.c: Likewise.
* common/config/s390/s390-common.c: Likewise.
* common/config/sh/sh-common.c: Likewise.
* common/config/sparc/sparc-common.c: Likewise.
* common/config/tilegx/tilegx-common.c: Likewise.
* common/config/tilepro/tilepro-common.c: Likewise.
* common/config/v850/v850-common.c: Likewise.
* common/config/visium/visium-common.c: Likewise.
* common/config/xstormy16/xstormy16-common.c: Likewise.
* common/config/xtensa/xtensa-common.c: Likewise.
doc/
* invoke.texi (-fomit-frame-pointer): Update documentation.
From-SVN: r254815
|
|
gcc/
* config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string.
* config/nds32/nds32.opt: Refine the layout.
* config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2,
TARGET_EXT_STRING): Support new options.
* config/nds32/nds32.h: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/constraints.md: Likewise.
* common/config/nds32/nds32-common.c: Likewise.
Co-Authored-By: Kito Cheng <kito.cheng@gmail.com>
From-SVN: r254798
|
|
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET,
OPTION_MASK_ISA_AVX512VBMI2_UNSET): New.
(ix86_handle_option): Handle -mavx512vbmi2.
* config/i386/cpuid.h: Add bit_AVX512VBMI2.
* config/i386/driver-i386.c (host_detect_local_cpu): Handle new bit.
* config/i386/i386-c.c (__AVX512VBMI2__): New.
* config/i386/i386.c (ix86_target_string): Handle -mavx512vbmi2.
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.h (TARGET_AVX512VBMI2, TARGET_AVX512VBMI2_P): New.
* config/i386/i386.opt (mavx512vbmi2): New option.
* doc/invoke.texi: Add new option.
From-SVN: r254796
|
|
gcc/
PR target/82812
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag.
(ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags.
* config/i386/i386-c.c (ix86_target_macros_internal): Ditto.
* config/i386/i386.opt: Ditto.
* config/i386/i386.c (ix86_target_string): Ditto.
(ix86_option_override_internal): Ditto.
(ix86_init_mpx_builtins): Move MPX to args2.
(ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineinvqb_v64qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v32qi,
__builtin_ia32_vgf2p8affineinvqb_v32qi_mask,
__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array.
From-SVN: r254507
|
|
All platforms except i386 will report the error and do no
instrumentation with -finstrument-control-flow option. i386
will provide the implementation based on a specification
published by Intel for a new technology called Control-flow
Enforcement Technology (CET). The spec is available at
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
The implementation in this patch:
1) enables Control-flow Enforcement Technology (CET), published by
Intel. This part introduces i386 specific options -mcet, -mibt and
-mshstk, new instructions and intrinsics;
2) provides support for -fcf-protection option and 'nocf_check'
attribute by doing needed code instrumentation, which is based on
CET features.
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New.
(OPTION_MASK_ISA_SHSTK_SET): Likewise.
(OPTION_MASK_ISA_IBT_UNSET): Likewise.
(OPTION_MASK_ISA_SHSTK_UNSET): Likewise.
(ix86_handle_option): Add -mibt, -mshstk, -mcet handling.
* config.gcc (extra_headers): Add cetintrin.h for x86 targets.
(extra_objs): Add cet.o for Linux/x86 targets.
(tmake_file): Add i386/t-cet for Linux/x86 targets.
* config/i386/cet.c: New file.
* config/i386/cetintrin.h: Likewise.
* config/i386/t-cet: Likewise.
* config/i386/cpuid.h (bit_SHSTK): New.
(bit_IBT): Likewise.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect and
pass IBT and SHSTK bits.
* config/i386/i386-builtin-types.def
(VOID_FTYPE_UNSIGNED_PVOID): New.
(VOID_FTYPE_UINT64_PVOID): Likewise.
* config/i386/i386-builtin.def: Add CET intrinsics.
* config/i386/i386-c.c (ix86_target_macros_internal): Add
OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling.
* config/i386/i386-passes.def: Add pass_insert_endbranch pass.
* config/i386/i386-protos.h (make_pass_insert_endbranch): New
prototype.
* config/i386/i386.c (rest_of_insert_endbranch): New.
(pass_data_insert_endbranch): Likewise.
(pass_insert_endbranch): Likewise.
(make_pass_insert_endbranch): Likewise.
(ix86_notrack_prefixed_insn_p): Likewise.
(ix86_target_string): Add -mibt, -mshstk flags.
(ix86_option_override_internal): Add flag_cf_protection
processing.
(ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk.
(ix86_print_operand): Add 'notrack' prefix output.
(ix86_init_mmx_sse_builtins): Add CET intrinsics.
(ix86_expand_builtin): Expand CET intrinsics.
(x86_output_mi_thunk): Add 'endbranch' instruction.
* config/i386/i386.h (TARGET_IBT): New.
(TARGET_IBT_P): Likewise.
(TARGET_SHSTK): Likewise.
(TARGET_SHSTK_P): Likewise.
* config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP,
UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP,
UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY.
(builtin_setjmp_setup): New pattern.
(builtin_longjmp): Likewise.
(rdssp<mode>): Likewise.
(incssp<mode>): Likewise.
(saveprevssp): Likewise.
(rstorssp): Likewise.
(wrss<mode>): Likewise.
(wruss<mode>): Likewise.
(setssbsy): Likewise.
(clrssbsy): Likewise.
(nop_endbr): Likewise.
* config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch
options.
* config/i386/immintrin.h: Include <cetintrin.h>.
* config/i386/linux-common.h
(file_end_indicate_exec_stack_and_cet): New prototype.
(TARGET_ASM_FILE_END): New.
From-SVN: r253977
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|
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_GFNI_SET,
(OPTION_MASK_ISA_GFNI_UNSET): New.
(ix86_handle_option): Handle OPT_mgfni.
* config/i386/cpuid.h (bit_GFNI): New.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect gfni.
* config/i386/i386-c.c (ix86_target_macros_internal): Define __GFNI__.
* config/i386/i386.c (ix86_target_string): Add -mgfni.
(ix86_valid_target_attribute_inner_p): Add OPT_mgfni.
* config/i386/i386.h (TARGET_GFNI, TARGET_GFNI_P): New.
* config/i386/i386.opt: Add mgfni.
From-SVN: r253922
|
|
2017-10-08 Olivier Hainque <hainque@adacore.com>
* common/config/arm/arm-common.c (arm_except_unwind_info):
Handle DWARF2_UNWIND_INFO.
From-SVN: r253521
|
|
This patch autogenerates arm-isa.h from new entries in arm-cpus.in.
This has the primary advantage that it makes the description file more
self-contained, but it also solves the 'array dimensioning' problem
that Tamar recently encountered. It adds two new constructs to
arm-cpus.in: features and fgroups. Fgroups are simply a way of naming
a group of feature bits so that they can be referenced together. We
follow the convention that feature bits are all lower case, while
fgroups are (predominantly) upper case. This is helpful as in some
contexts they share the same namespace. Most of the minor changes in
this patch are related to adopting this new naming convention.
2017-09-22 Richard Earnshaw <richard.earnshaw@arm.com>
* config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file.
* config/arm/arm-isa.h: Delete. Move definitions to ...
* arm-cpus.in: ... here. Use new feature and fgroup values.
* config/arm/arm.c (arm_option_override): Use lower case for feature
bit names.
* config/arm/arm.h (TARGET_HARD_FLOAT): Likewise.
(TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise.
* config/arm/parsecpu.awk (END): Add new command 'isa'.
(isa_pfx): Delete.
(print_isa_bits_for): New function.
(gen_isa): New function.
(gen_comm_data): Use print_isa_bits_for.
(define feature): New keyword.
(define fgroup): New keyword.
* config/arm/t-arm (TM_H): Remove.
(GTM_H): Add arm-isa.h.
(arm-isa.h): Add rule to generate file.
* common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower
case for feature bit names.
From-SVN: r253097
|
|
in nds32_option_optimization_table.
gcc/
* common/config/nds32/nds32-common.c
(nds32_option_optimization_table): Refine formatting.
(nds32_option_optimization_table): Use -fsched-pressure and
-fomit-frame-pointer for specific optimization level.
From-SVN: r252876
|
|
Revert r251800 and r251799.
From-SVN: r251980
|
|
This patch autogenerates arm-isa.h from new entries in arm-cpus.in.
This has the primary advantage that it makes the description file more
self-contained, but it also solves the 'array dimensioning' problem
that Tamar recently encountered. It adds two new constructs to
arm-cpus.in: features and fgroups. Fgroups are simply a way of naming
a group of feature bits so that they can be referenced together. We
follow the convention that feature bits are all lower case, while
fgroups are (predominantly) upper case. This is helpful as in some
contexts they share the same namespace. Most of the minor changes in
this patch are related to adopting this new naming convention.
* config.gcc (arm*-*-*): Don't add arm-isa.h to tm_p_file.
* config/arm/arm-isa.h: Delete. Move definitions to ...
* arm-cpus.in: ... here. Use new feature and fgroup values.
* config/arm/arm.c (arm_option_override): Use lower case for feature
bit names.
* config/arm/arm.h (TARGET_HARD_FLOAT): Likewise.
(TARGET_VFP3, TARGET_VFP5, TARGET_FMA): Likewise.
* config/arm/parsecpu.awk (END): Add new command 'isa'.
(isa_pfx): Delete.
(print_isa_bits_for): New function.
(gen_isa): New function.
(gen_comm_data): Use print_isa_bits_for.
(define feature): New keyword.
(define fgroup): New keyword.
* config/arm/t-arm (OPTIONS_H_EXTRA): Add arm-isa.h
(arm-isa.h): Add rule to generate file.
* common/config/arm/arm-common.c: (arm_canon_arch_option): Use lower
case for feature bit names.
From-SVN: r251799
|
|
gcc/
Better ISR prologues by supporting GASes __gcc_isr pseudo insn.
PR target/20296
PR target/81268
* configure.ac [target=avr]: Add GAS check for -mgcc-isr.
(HAVE_AS_AVR_MGCCISR_OPTION): If so, AC_DEFINE it.
* config.in: Regenerate.
* configure: Regenerate.
* doc/extend.texi (AVR Function Attributes) <no_gccisr>: Document it.
* doc/invoke.texi (AVR Options) <-mgas-isr-prologues>: Document it.
* config/avr/avr.opt (-mgas-isr-prologues): New option and...
(TARGET_GASISR_PROLOGUES): ...target mask.
* common/config/avr/avr-common.c
(avr_option_optimization_table) [OPT_LEVELS_1_PLUS_NOT_DEBUG]:
Set -mgas-isr-prologues.
* config/avr/avr-passes.def (avr_pass_pre_proep): Add
INSERT_PASS_BEFORE for it.
* config/avr/avr-protos.h (make_avr_pass_pre_proep): New proto.
* config/avr/avr.c (avr_option_override)
[!HAVE_AS_AVR_MGCCISR_OPTION]: Unset TARGET_GASISR_PROLOGUES.
(avr_no_gccisr_function_p, avr_hregs_split_reg): New static functions.
(avr_attribute_table) <no_gccisr>: Add new function attribute.
(avr_set_current_function) <is_no_gccisr>: Init machine field.
(avr_pass_data_pre_proep, avr_pass_pre_proep): New pass data
and rtl_opt_pass.
(make_avr_pass_pre_proep): New function.
(emit_push_sfr) <treg>: Add argument to function and use it
instead of TMP_REG.
(avr_expand_prologue) [machine->gasisr.maybe]: Emit gasisr insn
and set machine->gasisr.yes.
(avr_expand_epilogue) [machine->gasisr.yes]: Similar.
(avr_asm_function_end_prologue) [machine->gasisr.yes]: Add
__gcc_isr.n_pushed to .L__stack_usage.
(TARGET_ASM_FINAL_POSTSCAN_INSN): Define to...
(avr_asm_final_postscan_insn): ...this new static function.
* config/avr/avr.h (machine_function)
<is_no_gccisr, use_L__stack_usage>: New fields.
<gasisr, gasisr.yes, gasisr.maybe, gasisr.regno>: New fields.
* config/avr/avr.md (UNSPECV_GASISR): Add unspecv enum.
(GASISR_Prologue, GASISR_Epilogue, GASISR_Done): New define_constants.
(gasisr, *gasisr): New expander and insn.
* config/avr/gen-avr-mmcu-specs.c (print_mcu)
[HAVE_AS_AVR_MGCCISR_OPTION]: Print asm_gccisr spec.
* config/avr/specs.h (ASM_SPEC) <asm_gccisr>: Add sub spec.
From-SVN: r250093
|
|
When I originally started work on the new options framework for ARM
I'd worked on the assumption that AWK might not be available on every
build machine (only on developer's machines). However, looking again
I notice that all the options framework relies on it being present for
every build. This means that some of the generated files that come
from running parsecpu.awk do not need to be kept under revision
control.
Unfortunately, it's not _all_ generated files. The build
infrastructure assumes that all .md fragments are in the source tree
and similarly that all .opt fragments are there as well.
Still, eliminating the very big .h files is a step forward as they are
very regular in structure and diff/patch/merge tools can sometimes
make mistakes when resolving conflicts.
So this patch removes the generated .h files from the source tree and
tweaks the make rules accordingly. I've also changed the build rules
to use the stamp technique to eliminate some false dependencies in a
rebuild.
Top-level:
* contrib/gcc_update (files_and_dependencies): Remove stamp rules for
arm-specific auto-generated header files.
gcc:
* common/config/arm/arm-common.c: Adjust include path for
arm-cpu-cdata.h
* t-arm (TM_H): Adjust path for arm-cpu.h.
(arm-cpu.h): Create in build directory. Adjust dependency rules.
(arm-cpu-data.h): Likewise.
(arm-cpu-cdata.h): Likewise.
* config/arm/arm-cpu.h: Delete.
* config/arm/arm-cpu-cdata.h: Delete.
* config/arm/arm-cpu-data.h: Delete.
From-SVN: r249971
|
|
The existing code in arm/bpabi.h was quite fragile and relied on matching
specific CPU and/or architecture names. The introduction of the option
format for -mcpu and -march broke that in a way that would be non-trivial
to fix by updating the list. The hook in that file was always a pain
as it required every new CPU being added to be add an update here as well
(easy to miss).
I've fixed that problem once and for all by adding a new callback into
the driver to select the correct BE8 behaviour. This uses features in
the ISA capabilities list to select whether or not to use BE8 format
during linking.
I also noticed that if the user happened to pass both -mbig-endian and
-mlittle-endian on the command line then the linker spec rules would
get somewhat confused and potentially do the wrong thing. I've fixed that
by marking these options as opposites in the option descriptions. The
driver will now automatically suppress overridden options leading to the
correct desired behavior.
Whilst fixing this I noticed a couple of anomolus cases in the
existing BE8 support: we were not generating BE8 format for ARMv6 or
ARMv7-R targets. While the ARMv6 status was probably deliberate at
the time, this is probably not a good idea in the long term as the
alternative, BE32, has been deprecated by ARM. After discussion with
a couple of colleagues I've decided to change this, but to then add an
option to restore the existing behaviour at the user's option. So
this patch introduces two new options (opposites) -mbe8 and -mbe32.
This is a quiet behavior change, so I'll add a comment to the release
notes shortly.
* common/config/arm/arm-common.c (arm_be8_option): New function.
* config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8.
(ISA_ARMv6): Add isa_bit_be8.
* config/arm/arm.h (arm_be8_option): Add prototype.
(BE8_SPEC_FUNCTION): New define.
(EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION.
* config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian.
(mlittle-endian): Similarly.
(mbe8, mbe32): New options.
* config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option.
* doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32.
From-SVN: r249909
|
|
Now that the default FPU is 'auto' we can finally rewrite (and
simplify) the rules for mapping compiler options to multilibs. We
no-longer need to know the specific CPU, since the driver will
construct a suitable -march flag for us; this greatly simplifies the
overall logic. This patch rewrites the library list for A-profile
cores. We use various Make extention rules to simplify the logic even
further.
A couple of minor tweaks to the configure script and to the main
driver ensures that we always know the setting of -mfloat-abi and
-marm/-mthumb. Again, this helps simplify the logic further. The
change to arm_target_thumb_only relies on the fact that this routine
is only called if neither -marm nor -mthumb has been previously
selected or specified by the user.
A new testsuite module is added to check the libraries generated. The
new tests are only run if the compiler is configured with the relevant
multilibs enabled.
gcc:
* config.gcc: (arm*-*-*): When building a-profile libraries, force
the driver to pass through the default setting of -mfloat-abi.
* common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm
rather than NULL.
* config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty.
(all_feat_combs): New rule.
(MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework
default libraries.
* config/arm/t-aprofile: Rewrite.
gcc/testsuite:
* gcc.target/arm/multilibs.exp: New file.
From-SVN: r249296
|
|
Finally, we can make 'auto' the default choice for the FPU option. It's
still possible to override this during configure, but we will eventually
deprecate that, moving to the new cpu/architecture selection mechanism.
* config/arm/arm.h (FPUTYPE_AUTO): Define.
* config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the
fpu is not specified by the user/command-line.
* config/arm/bpabi.h (FPUTYPE_DEFAULT): Delete.
* config/arm/netbsd-elf.h (FPUTYPE_DEFAULT): Delete.
* config/arm/linux-elf.h (FPUTYPE_DEFAULT): Delete.
* config/arm/vxworks.h (FPUTYPE_DEFAULT): Delete.
* common/config/arm/arm-common.c (arm_canon_arch_option): Use
FPUTYPE_AUTO insted of FPUTYPE_DEFAULT.
From-SVN: r249295
|
|
This patch uses the driver and some spec rewrite rules to generate a
canonicalized form of the -march= option. We want to do this for
several reasons, all relating to making multi-lib selection sane.
1) It can remove redundant extension options to produce a minimal
list.
2) The general syntax of the option permits a plethora of features,
these are permitted in any order. Canonicalization ensures that there
is a single ordering of the options that are needed.
3) It can use additional options to remove extensions that aren't
relevant, such as removing all features that relate to the FPU when
use of that is disabled.
Once we have this information in a sensible form the multilib rules
can be vastly simplified making for much more understandable Makefile
fragments.
* common/config/arm/arm-common.c: Define INCLUDE_LIST.
(configargs.h): Include it.
(arm_print_hint_for_fpu_option): New function.
(arm_parse_fpu_option): New function.
(candidate_extension): New class.
(arm_canon_for_multilib): New function.
* config/arm/arm.h (CANON_ARCH_SPEC_FUNCTION): New macro.
(EXTRA_SPEC_FUNCTIONS): Add CANON_ARCH_SPEC_FUNCTION.
(ARCH_CANONICAL_SPECS): New macro.
(DRIVER_SELF_SPECS): Add ARCH_CANONICAL_SPECS.
From-SVN: r249292
|
|
Now that the standard CPU and architecture option parsing code is
available in the driver we can use the main CPU and architecture data
tables for driving the automatic enabling of Thumb code.
Doing this requires that the driver script tell the parser whether or
not the target string is a CPU name or an architecture, but beyond
that it is just standard use of the new capabilities.
We do, however, now get some error checking if the target isn't
recognized, when previously we just ignored unknown targets and hoped
that a later pass would pick up on this.
* config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to
call to target_mode_check describing the type of option passed.
* common/config/arm/arm-common.c (arm_arch_core_flag): Delete.
(arm_target_thumb_only): Use arm_parse_arch_option_name or
arm_parse_cpu_option_name to match parameters against list of
available targets.
* config/arm/parsecpu.awk (gen_comm_data): Don't generate
arm_arch_core_flags data structure.
* config/arm/arm-cpu_cdata.h: Regenerated.
From-SVN: r249288
|
|
This patch has no functional change. The code used for parsing -mcpu,
-mtune and -march options is simply moved from arm.c arm-common.c.
The list of FPU options is also moved. Subsequent patches will make
use of this within the driver.
Some small adjustments are needed as a consequence of moving the
definitions of the data objects to another object file, in that we
no-longer have direct access to the size of the object.
* common/config/arm/arm-common.c (arm_initialize_isa): Moved here from
config/arm/arm.c.
(arm_print_hint_for_cpu_option): Likewise.
(arm_print_hint_for_arch_option): Likewise.
(arm_parse_cpu_option_name): Likewise.
(arm_parse_arch_option_name): Likewise.
* config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number
of entries in the all_fpus list.
* config/arm/arm-protos.h (all_architectures, all_cores): Declare.
(arm_parse_cpu_option_name): Declare.
(arm_parse_arch_option_name): Declare.
(arm_parse_option_features): Declare.
(arm_intialize_isa): Declare.
* config/arm/parsecpu.awk (gen_data): Move CPU and architecture
data tables to ...
(gen_comm_data): ... here. Make definitions non-static.
* config/arm/arm-cpu-data.h: Regenerated.
* config/arm/arm-cpu-cdata.h: Regenerated.
From-SVN: r249287
|
|
The assembler does not understand all the '+' options accepted by the
compiler. The best solution to this is to simply strip the extensions
and just pass the raw architecture or cpu name through to the
assembler. We will use .arch and .arch_extension directives anyway to
turn on or off individual features. We already do something similar
for big.little combinations and this just extends this principle a bit
further. This patch also fixes a possible bug by ensuring that the
limited string copy is correctly NUL-terminated.
While messing with this code I've also taken the opportunity to clean up
the duplicate definitions of EXTRA_SPEC_FUNCTIONS by moving it outside of
the ifdef wrapper.
* config/arm/arm.h (BIG_LITTLE_SPEC): Delete macro.
(ASM_REWRITE_SPEC_FUNCTIONS): New macro.
(BIG_LITTLE_CPU_SPEC_FUNCTIONS): Delete macro.
(ASM_CPU_SPEC): Rewrite.
(MCPU_MTUNE_NATIVE_FUNCTIONS): New macro.
(EXTRA_SPEC_FUNCTIONS): Move outside of ifdef. Use
MCPU_MTUNE_NATIVE_FUNCTIONS and ASM_REWRITE_SPEC_FUNCTIONS. Remove
reference to BIG_LITTLE_CPU_SPEC_FUNCTIONS.
* common/config/arm/arm-common.c (arm_rewrite_selected_cpu): Ensure
copied string is NUL-terminated. Also strip any characters prefixed
by '+'.
(arm_rewrite_selected_arch): New function.
(arm_rewrite_march): New function.
From-SVN: r249280
|
|
* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
SPE ABI handling.
* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
paired_divv2sf3): Similar.
* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
RS6000_BUILTIN_S.
Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
Rename the paired_* instruction patterns.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
define __SPE__.
* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and
TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with
PAIRED_VECTOR_MODE.
(struct machine_function): Delete field spe_insn_chain_scanned_p.
(spe_func_has_64bit_regs_p): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(TARGET_DWARF_REGISTER_SPAN): Do not define.
(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
(invalid_e500_subreg): Delete.
(rs6000_legitimize_address): Always force_reg op2 as well, for
paired single memory accesses.
(rs6000_member_type_forces_blk): Delete.
(rs6000_spe_function_arg): Delete.
(rs6000_expand_unop_builtin): Delete SPE handling.
(rs6000_expand_binop_builtin): Ditto.
(spe_expand_stv_builtin): Delete.
(bdesc_2arg_spe): Delete.
(spe_expand_builtin): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
(spe_init_builtins): Delete.
(spe_func_has_64bit_regs_p): Delete.
(savres_routine_name): Delete "info" parameter. Adjust callers.
(rs6000_emit_stack_reset): Ditto.
(rs6000_dwarf_register_span): Delete.
* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
Delete.
* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
Delete.
* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
mulv2sf3, divv2sf3): Delete expanders.
From-SVN: r248980
|
|
* config/powerpcspe: New port. Files are copied from the rs6000
port, with "rs6000" in filenames replaced by "powerpcspe".
* config.gcc (powerpc*-*-*spe*): New.
(powerpc-*-eabispe*): Use ${cpu_type} instead of hardcoded pathnames.
(powerpc-*-rtems*spe*): New.
(powerpc*-*-linux*spe*): New.
(powerpc-wrs-vxworksspe): New.
(powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
(misc flags) [powerpc*-*-*, rs6000-*-*): Use ${cpu_type}.
* config.host (powerpc*-*-*spe*): New.
From-SVN: r248429
|
|
This patch covers the mechanical work of making the new architecture
option arch12 available wherever it will be needed later.
gcc/testsuite/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.target/s390/s390.exp: Run tests in arch12 and vxe dirs.
* lib/target-supports.exp: Add effective target check s390_vxe.
gcc/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* common/config/s390/s390-common.c (processor_flags_table): Add
arch12.
* config.gcc: Add arch12.
* config/s390/driver-native.c (s390_host_detect_local_cpu):
Default to arch12 for unknown CPU model numbers.
* config/s390/s390-builtins.def: Add B_VXE builtin flag.
* config/s390/s390-c.c (s390_cpu_cpp_builtins_internal): Adjust
PROCESSOR_max sanity check.
* config/s390/s390-opts.h (enum processor_type): Add
PROCESSOR_ARCH12.
* config/s390/s390.c (processor_table): Add arch12.
(s390_expand_builtin): Add check for B_VXE flag.
(s390_issue_rate): Add PROCESSOR_ARCH12.
(s390_get_sched_attrmask): Likewise.
(s390_get_unit_mask): Likewise.
(s390_sched_score): Enable z13 scheduling for arch12.
(s390_sched_reorder): Likewise.
(s390_sched_variable_issue): Likewise.
* config/s390/s390.h (enum processor_flags): Add PF_ARCH12 and
PF_VXE.
(s390_tune_attr): Use z13 scheduling also for arch12.
(TARGET_CPU_ARCH12, TARGET_CPU_ARCH12_P, TARGET_CPU_VXE)
(TARGET_CPU_VXE_P, TARGET_ARCH12, TARGET_ARCH12_P, TARGET_VXE)
(TARGET_VXE_P): New macros.
* config/s390/s390.md: Add arch12 to cpu attribute. Add arch12
and vxe to cpu_facility. Add arch12 and vxe to enabled attribute.
* config/s390/s390.opt: Add arch12 as processor_type.
From-SVN: r246452
|
|
gcc/
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
(arc_conditional_register_usage): Use a different allocation order
when optimizing for size.
* common/config/arc/arc-common.c (arc_option_optimization_table):
Section anchors default on when optimizing for size.
From-SVN: r246091
|
|
PR target/79569
* config/i386/i386.opt (m3dnowa): Replace Undocumented with Report.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_3DNOW_A_SET): Define.
(ix86_handle_option): Handle OPT_m3dnowa.
* doc/invoke.texi (-m3dnowa): Document.
* doc/extend.texi (__builtin_ia32_pmulhuw, __builtin_ia32_pf2iw): Use
-m3dnowa instead of -m3dnow -march=athlon.
* gcc.target/i386/3dnowA-3.c: New test.
From-SVN: r245561
|
|
* common/config/i386/i386-common.c (OPTION_MASK_ISA_RDPID_SET): New.
(OPTION_MASK_ISA_PKU_UNSET): New.
(ix86_handle_option): Handle -mrdpid.
* config/i386/cpuid.h (bit_RDPID): New.
* config/i386/driver-i386.c (host_detect_local_cpu):
Detect RDPID feature.
* config/i386/i386-builtin.def (__builtin_ia32_rdpid): New.
* config/i386/i386-c.c (ix86_target_macros_internal):
Handle RDPID flag.
* config/i386/i386.c (ix86_target_string): Add -mrdpid to isa2_opts.
(ix86_valid_target_attribute_inner_p): Add "rdpid".
(ix86_expand_builtin): Handle IX86_BUILTIN_RDPID.
* config/i386/i386.h (TARGET_RDPID, TARGET_RDPID_P): New.
* config/i386/i386.md (define_insn "rdpid"): New.
* config/i386/i386.opt Add -mrdpid.
* config/i386/immintrin.h (_rdpid_u32): New.
testsuite/ChangeLog:
* gcc.target/i386/rdpid.c New test.
* gcc.target/i386/sse-12.c: Add -mrdpid.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
From-SVN: r245540
|
|
gcc/ChangeLog:
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.c: New file.
* gcc/common/config/riscv/riscv-common.c: Likewise.
* config.gcc: Likewise.
* config/riscv/constraints.md: Likewise.
* config/riscv/elf.h: Likewise.
* config/riscv/generic.md: Likewise.
* config/riscv/linux.h: Likewise.
* config/riscv/multilib-generator: Likewise.
* config/riscv/peephole.md: Likewise.
* config/riscv/pic.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.c: Likewise.
* config/riscv/riscv-c.c: Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-modes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/sync.md: Likewise.
* config/riscv/t-elf-multilib: Likewise.
* config/riscv/t-linux: Likewise.
* config/riscv/t-linux-multilib: Likewise.
* config/riscv/t-riscv: Likewise.
* configure.ac: Likewise.
* doc/contrib.texi: Add Kito Cheng, Palmer Dabbelt, and Andrew
Waterman as RISC-V maintainers.
* doc/install.texi: Add RISC-V entries.
* doc/invoke.texi: Add RISC-V options section.
* doc/md.texi: Add RISC-V constraints section.
From-SVN: r245224
|
|
* common/config/i386/i386-common.c (OPTION_MASK_ISA_SGX_UNSET): New.
(OPTION_MASK_ISA_SGX_SET): New.
(ix86_handle_option): Handle OPT_msgx.
* config.gcc: Added sgxintrin.h.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect sgx.
* config/i386/i386-c.c (ix86_target_macros_internal): Define __SGX__.
* config/i386/i386.c (ix86_target_string): Add -msgx.
(PTA_SGX): New.
(ix86_option_override_internal): Handle new options.
(ix86_valid_target_attribute_inner_p): Add sgx.
* config/i386/i386.h (TARGET_SGX, TARGET_SGX_P): New.
* config/i386/i386.opt: Add msgx.
* config/i386/sgxintrin.h: New file.
* config/i386/x86intrin.h: Add sgxintrin.h.
testsuite/ChangeLog:
* gcc.target/i386/sgx.c New test.
* gcc.target/i386/sse-12.c: Add -msgx.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>
From-SVN: r244339
|
|
The files arm-cores.def, arm-fpus.def and arm-arches.def are parsed and
used in several places and the format is slightly awkward to maintain
as they must be parsable in C and by certain scripts. Furthermore,
changes to the content that affects every entry is particularly awkward for
dealing with merges.
This patch replaces all three files with a single file that specifies all
the command-line related definitions in a new format that allows for better
checking for consistency as well as (hopefully) easier to merge changes.
The awk script used to parse it is relatively complicated, but should be
pretty portable. It works by parsing in all the data and then operating
one of a number of possible sub-commands to generate the desired output.
The new method picked up one error. The CPU descriptions referred to an
architecture ARMv5tej which was not supported by -march. This has been
fixed by adding the relevant entry to the architecture list.
gcc:
* config.gcc: Use new awk script to check CPU, FPU and architecture
parameters for --with-... options.
* config/arm/parsecpu.awk: New file
* config/arm/arm-cpus.in: New file.
* config/arm/arm-opts.h: Include arm-cpu.h instead of processing .def
files.
* config/arm/arm.c: Include arm-cpu-data.h instead of processing .def
files.
* config/arm/t-arm: Update dependency rules.
* common/config/arm/arm-common.c: Include arm-cpu-cdata.h instead
of processing .def files.
* config/arm/genopt.sh: Deleted.
* config/arm/gentune.sh: Deleted.
* config/arm/arm-cores.def: Deleted.
* config/arm/arm-arches.def: Deleted.
* config/arm/arm-fpus.def: Deleted.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-cpu.h: New generated file.
* config/arm/arm-cpu-data.h: New generated file.
* config/arm/arm-cpu-cdata.h: New generated file.
Contrib:
* gcc_update: Adjust touch list.
From-SVN: r244316
|
|
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET,
OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET): New.
* config.gcc: Add avx512vpopcntdqintrin.h.
* config/i386/avx512vpopcntdqintrin.h: New.
* config/i386/cpuid.h (bit_AVX512VPOPCNTDQ): New.
* config/i386/i386-builtin-types.def: Add new types.
* config/i386/i386-builtin.def (__builtin_ia32_vpopcountd_v16si,
__builtin_ia32_vpopcountd_v16si_mask, __builtin_ia32_vpopcountq_v8di,
__builtin_ia32_vpopcountq_v8di_mask): New.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__AVX512VPOPCNTDQ__.
* config/i386/i386.c (ix86_target_string): Add -mavx512vpopcntdq.
(PTA_AVX512VPOPCNTDQ): Define.
* config/i386/i386.h (TARGET_AVX512VPOPCNTDQ,
TARGET_AVX512VPOPCNTDQ_P): Define.
* config/i386/i386.opt: Add mavx512vpopcntdq.
* config/i386/immintrin.h: Include avx512vpopcntdqintrin.h.
* config/i386/sse.md (define_insn "vpopcount<mode><mask_name>"): New.
libgcc/
* config/i386/cpuinfo.h (processor_features): Add
FEATURE_AVX512VPOPCNTDQ.
* config/i386/cpuinfo.c (get_available_features): Habdle new
feature.
gcc/testsuite/
* g++.dg/other/i386-2.C: Add -mavx512vpopcntdq.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/builtin_target.c: Handle new option.
* gcc.target/i386/funcspec-56.inc: Test new attributes.
* gcc.target/i386/avx512vpopcntdq-vpopcntd.c: New test.
* gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto.
From-SVN: r244263
|
|
PR translation/79019
PR translation/79020
* params.def (PARAM_INLINE_MIN_SPEEDUP,
PARAM_IPA_CP_SINGLE_CALL_PENALTY,
PARAM_USE_AFTER_SCOPE_DIRECT_EMISSION_THRESHOLD): Fix typos
in descriptions.
* config/avr/avr.opt (maccumulate-args): Likewise.
* config/msp430/msp430.opt (mwarn-mcu): Likewise.
* common.opt (freport-bug): Likewise.
* cif-code.def (CIF_FINAL_ERROR): Likewise.
* doc/invoke.texi (ipa-cp-single-call-penalty): Likewise.
* config/s390/s390.c (s390_invalid_binary_op): Fix spelling in
translatable string.
* config/i386/i386.c (function_value_32): Likewise.
* config/nios2/nios2.c (nios2_valid_target_attribute_rec): Likewise.
* config/msp430/msp430.c (msp430_option_override, msp430_attr):
Likewise.
* config/msp430/driver-msp430.c (msp430_select_hwmult_lib): Likewise.
* common/config/msp430/msp430-common.c (msp430_handle_option):
Likewise.
* symtab.c (symtab_node::verify_base): Likewise.
* opts.c (set_debug_level): Likewise.
* tree.c (verify_type_variant): Likewise. Fix typo in comment.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
missing whitespace to translatable strings.
* config/avr/avr.md (bswapsi2): Fix typo in comment.
* config/sh/superh.h: Likewise.
* config/i386/xopintrin.h: Likewise.
* config/i386/znver1.md: Likewise.
* config/rs6000/rs6000.c (struct rs6000_opt_mask): Likewise.
* ipa-inline-analysis.c (compute_inline_parameters): Likewise.
* double-int.h (struct double_int): Likewise.
* double-int.c (div_and_round_double): Likewise.
* wide-int.cc: Likewise.
* tree-ssa.c (non_rewritable_mem_ref_base): Likewise.
* tree-ssa-sccvn.c (vn_reference_lookup_3): Likewise.
* cfgcleanup.c (crossjumps_occured): Renamed to ...
(crossjumps_occurred): ... this.
(try_crossjump_bb, try_head_merge_bb, try_optimize_cfg, cleanup_cfg):
Adjust all uses.
cp/
* semantics.c (finish_omp_clauses): Add missing whitespace to
translatable strings.
* cp-cilkplus.c (cpp_validate_cilk_plus_loop_aux): Fix comment typo.
lto/
* lto-symtab.c (lto_symtab_merge_symbols): Fix comment typo.
fortran/
* decl.c (attr_decl1): Fix spelling in translatable string.
* intrinsic.texi: Fix spelling - invokation -> invocation.
* lang.opt (faggressive-function-elimination, gfc_convert): Fix
typos in descriptions.
* openmp.c (resolve_omp_clauses): Add missing whitespace to
translatable strings.
c-family/
* c.opt (Wnormalized=): Fix typo in description.
testsuite/
* c-c++-common/goacc/host_data-2.c (f): Adjust expected spelling of
diagnostics.
* gfortran.dg/initialization_17.f90: Likewise.
From-SVN: r244245
|
|
This patch, taken from
<https://git.busybox.net/buildroot/tree/package/gcc/5.4.0/840-microblaze-enable-dwarf-eh-support.patch>
and with a few formatting cleanups and an update for the removal of
gen_rtx_raw_REG, enables DWARF EH support for MicroBlaze.
This is needed for building glibc with a compiler that includes shared
libgcc; right now all glibc builds for MicroBlaze are failing with my
bot for lack of this support. (It's dubious if we should have glibc
ports at all where required support is missing in FSF GCC.)
Tested building glibc with build-many-glibcs.py. I have *not* done
any other testing or any execution testing for MicroBlaze.
2017-01-06 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
David Holsgrove <david.holsgrove@xilinx.com>
* common/config/microblaze/microblaze-common.c
(TARGET_EXCEPT_UNWIND_INFO): Remove.
* config/microblaze/microblaze-protos.h (microblaze_eh_return):
New prototype.
* config/microblaze/microblaze.c (microblaze_must_save_register)
(microblaze_expand_epilogue, microblaze_return_addr): Handle
calls_eh_return.
(microblaze_eh_return): New function.
* config/microblaze/microblaze.h (RETURN_ADDR_OFFSET)
(EH_RETURN_DATA_REGNO, MB_EH_STACKADJ_REGNUM)
(EH_RETURN_STACKADJ_RTX, ASM_PREFERRED_EH_DATA_FORMAT): New macros.
* config/microblaze/microblaze.md (eh_return): New pattern.
Co-Authored-By: David Holsgrove <david.holsgrove@xilinx.com>
From-SVN: r244183
|
|
From-SVN: r243994
|
|
performance)
PR rtl-optimization/11488
* common/config/rs6000/rs6000-common.c
(rs6000_option_optimization_table): Enable -fsched-pressure.
* config/rs6000/rs6000.c (TARGET_COMPUTE_PRESSURE_CLASSES): Define
target hook.
(rs6000_option_override_internal): Set default -fsched-pressure algorithm.
(rs6000_compute_pressure_classes): Implement target hook.
From-SVN: r243866
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Nothing uses the old feature sets now, so we can delete them entirely.
* arm-cores.def: Remove FLAGS field from all core definitions.
* arm-arches.def: Likewise.
* arm-opts.h (enum processor_type): Remove FLAGS parameter from
ARM_CORES macro.
(arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
* arm-protos.h (FL_*): Delete.
(arm_feature_set): Delete.
(ARM_FSET_*): Delete.
* arm.c (struct processors): Delete flags field.
(all_cores): Delete FLAGS parameter from macro, don't initialize flags.
(all architectures): Likewise.
From-SVN: r243705
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This converts the recently added implicit -mthumb support code to use
the new data structures. Since we have a very simple query and no
initialized copies of the sbitmaps, for now we simply scan the list of
features to look for the one of interest.
* arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
Initialize it.
(arm_arch_core_flag): Delete flags field.
(arm_arch_core_flags): Don't initialize flags field.
* common/config/arm/arm-common.c (check_isa_bits_for): New function.
(arm_target_thumb_only): Use new isa bits arrays.
From-SVN: r243704
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This patch adds the new ISA data structures. The idea is to use an
sbitmap for carrying these around internally. We don't make much use
of this yet, but will increasingly migrate over to this in the
following patches. All cores and architectures currently have both
old and new encodings for now.
For simplicity and clarity we introduce internally the concept of
ARMv7ve. It doesn't change any visible behaviour.
There's also a bit of tidying up of the various supported cores,
sorting them by profile.
* arm-isa.h: New file.
* arm-protos.h: Include it.
* arm-arches.def: Add new ISA field to all entries. Drop bogus
armv8.1-a+crc architecture.
* arm-cores.def: Similarly. Group ARMv8 cores by profile.
* arm-opts.h (enum processor_type): Adjust for new field.
* arm.c (struct processors): New field 'isa_bits'.
(all_cores, all_architectures): Initialize new field.
* arm-tables.opt: Regenerated.
* arm-tune.md: Regenerated.
From-SVN: r243697
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We start out by separating the 'tuning flags' in a CPU or architecture
specification into a new field in the data structures. Because there
aren't very many of these (and we'd like to get rid of them entirely,
eventually, moving to entries in the tuning tables), we just use a
simple unsigned word. This frees up a number of bits in the main
flags data structure, but we don't consolidate them as we'll be
getting rid of them entirely shortly.
There's one small user-visible change, the slow multiply flag is moved
from being treated as an architectural flag to a tuning flag. This
has two consequences: it's now ignored for architectural matching to a
CPU and specifying a -mtune option will now correctly apply the
multiply performance to the decision as to which sequences to
synthesise.
* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
tuning properties from architectural FLAGS field.
* arm-cores.def (ARM_CORE): Likewise.
* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
(FL_TUNE): Remove deleted elements.
(tune_flags): Convert type to unsigned int.
* arm.c (struct processors): Add new field tune_flags.
(all_cores, all_arches): Initialize it.
(arm_option_override): Adapt uses of tune_flags. Use tune_flags
for deciding when we should have slow multiply operations.
From-SVN: r243696
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2016-12-14 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-cores.def: Add -1 as the variant to all
of the cores.
(thunderx): Update to include LSE by default.
(thunderxt88p1): New core.
(thunderxt88): New core.
(thunderxt81): New core.
(thunderxt83): New core.
* config/aarch64/driver-aarch64.c (struct aarch64_core_data):
Add variant field.
(ALL_VARIANTS): New define.
(AARCH64_CORE): Support VARIANT operand.
(cpu_data): Likewise.
(host_detect_local_cpu): Parse variant field of /proc/cpuinfo.
Combine the arch and single core case and support variant searching.
* common/config/aarch64/aarch64-common.c (AARCH64_CORE):
Add VARIANT operand.
* config/aarch64/aarch64-opts.h (AARCH64_CORE): Likewise.
* config/aarch64/aarch64.c (AARCH64_CORE): Likewise.
* config/aarch64/aarch64.h (AARCH64_CORE): Likewise.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AARCH64/mtune): Document thunderxt88,
thunderxt88p1, thunderxt81, thunderxt83 as available options.
From-SVN: r243675
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