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2021-08-12arc: Small data doesn't need fcommon optionClaudiu Zissulescu1-3/+1
ARC backend is defaulting to -fcommon. This is not anylonger needed, remove it. gcc/ 2021-08-12 Claudiu Zissulescu <claziss@synopsys.com> * common/config/arc/arc-common.c (arc_option_init_struct): Remove fno-common reference. * config/arc/arc.c (arc_override_options): Remove overriding of flag_no_common. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2021-07-18x86: Enable the GPR only instructions for -mgeneral-regs-onlyH.J. Lu1-2/+25
For -mgeneral-regs-only, enable the GPR only instructions which are enabled implicitly by SSE ISAs unless they have been disabled explicitly. gcc/ PR target/101492 * common/config/i386/i386-common.c (ix86_handle_option): For -mgeneral-regs-only, enable the GPR only instructions which are enabled implicitly by SSE ISAs unless they have been disabled explicitly. gcc/testsuite/ PR target/101492 * gcc.target/i386/pr101492-1.c: New test. * gcc.target/i386/pr101492-2.c: Likewise. * gcc.target/i386/pr101492-3.c: Likewise. * gcc.target/i386/pr101492-4.c: Likewise.
2021-06-30[amdgcn] Use frame pointer for CFA expressions.Hafiz Abid Qadeer1-1/+1
As size of address is bigger than registers in amdgcn, we are forced to use DW_CFA_def_cfa_expression to make an expression that concatenates multiple registers for the value of the CFA. This then prohibits us from using many of the dwarf ops which expect CFA rule to be a single regsiter plus an offset. Using frame pointer in the CFA rule is only real possibility as it is saved in every frame and it is easy to unwind its value. So unless user gives fomit-frame-pointer, we use frame pointer for the cfi information. This options also has a different default now. gcc/ * common/config/gcn/gcn-common.c (gcn_option_optimization_table): Change OPT_fomit_frame_pointer to -O3. * config/gcn/gcn.c (gcn_expand_prologue): Prefer the frame pointer when emitting CFI. (gcn_expand_prologue): Prefer the frame pointer when emitting CFI. (gcn_frame_pointer_rqd): New function. (TARGET_FRAME_POINTER_REQUIRED): New hook.
2021-06-18arm: Fix multilib mapping for CDE extensions [PR100856].Srinath Parvathaneni1-6/+41
On passing +cdecp[0-7] extension to the -march string in command line options, multilib linking is failing as mentioned in PR100856. This patch fixes this issue by generating a separate canonical string by removing compiler options which are not required for multilib linking from march string and assign the new string to mlibarch option. This mlibarch string is used for multilib comparison. gcc/ChangeLog: 2021-06-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function derived from arm_canon_arch. (arm_canon_arch_option): Call it. (arm_canon_arch_multilib_option): New function. * config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup. * config/arm/arm.h (arm_canon_arch_multilib_option): New prototype. (CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro. (MULTILIB_ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS. * config/arm/arm.opt (mlibarch): New option. * config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use of march on RHS with mlibarch. gcc/testsuite/ChangeLog: 2021-06-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/100856 * gcc.target/arm/acle/pr100856.c: New test. * gcc.target/arm/multilib.exp: Add tests for cde options.
2021-06-07Reformat target.def for better parsing.Martin Liska1-16/+16
gcc/c-family/ChangeLog: * c-target.def: Split long lines and replace them with '\n\'. gcc/ChangeLog: * common/common-target.def: Split long lines and replace them with '\n\'. * target.def: Likewise. * doc/tm.texi: Re-generated.
2021-06-03arc: Remove obsolete optionsClaudiu Zissulescu1-1/+0
Remove the following obsolete options: - munalign-prob-threshold - malign-call - mmixed-code The ARC's options are marked as obsolete and ignored for backwards compatibility. gcc/ 2021-06-03 Claudiu Zissulescu <claziss@synopsys.com> * common/config/arc/arc-common.c (arc_option_optimization_table): Remove malign-call. * config/arc/arc.c (arc_unalign_branch_p): Remove unused function. * config/arc/arc.h (TARGET_MIXED_CODE): Remove macro. (INDEX_REG_CLASS): Only refer to GENERAL_REGS. * config/arc/arc.md (abssi2_mixed): Remove pattern. * config/arc/arc.opt (munalign-prob-threshold): Mark it obsolete. (malign-call): Likewise. (mmixed-code): Likewise. * doc/invoke.texi (ARC): Update doc. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2021-05-19RISC-V: Properly parse the letter 'p' in '-march'.Geng Qi1-33/+35
gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_subset_list::parsing_subset_version): Properly parse the letter 'p' in '-march'. (riscv_subset_list::parse_std_ext, riscv_subset_list::parse_multiletter_ext): To handle errors generated in riscv_subset_list::parsing_subset_version. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-12.c: New. * gcc.target/riscv/attribute-19.c: New.
2021-05-18Use startswith in targets.Martin Liska3-4/+4
gcc/ChangeLog: * common/config/aarch64/aarch64-common.c (aarch64_parse_extension): Use startswith function instead of strncmp. * common/config/bfin/bfin-common.c (bfin_handle_option): Likewise. * common/config/riscv/riscv-common.c (riscv_subset_list::parse): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_type): Likewise. * config/aarch64/aarch64.c (aarch64_process_one_target_attr): Likewise. * config/alpha/alpha.c (alpha_elf_section_type_flags): Likewise. * config/arm/aarch-common.c (arm_md_asm_adjust): Likewise. * config/arm/arm.c (arm_file_start): Likewise. (arm_valid_target_attribute_rec): Likewise. (thumb1_md_asm_adjust): Likewise. * config/arm/driver-arm.c (host_detect_local_cpu): Likewise. * config/avr/avr.c (STR_PREFIX_P): Likewise. (avr_set_current_function): Likewise. (avr_handle_addr_attribute): Likewise. (avr_asm_output_aligned_decl_common): Likewise. (avr_asm_named_section): Likewise. (avr_section_type_flags): Likewise. (avr_asm_select_section): Likewise. * config/c6x/c6x.c (c6x_in_small_data_p): Likewise. (c6x_section_type_flags): Likewise. * config/darwin-c.c (darwin_cfstring_ref_p): Likewise. (darwin_objc_declare_unresolved_class_reference): Likewise. (darwin_objc_declare_class_definition): Likewise. * config/darwin.c (indirect_data): Likewise. (darwin_encode_section_info): Likewise. (darwin_objc2_section): Likewise. (darwin_objc1_section): Likewise. (machopic_select_section): Likewise. (darwin_globalize_label): Likewise. (darwin_label_is_anonymous_local_objc_name): Likewise. (darwin_asm_named_section): Likewise. (darwin_asm_output_dwarf_offset): Likewise. * config/frv/frv.c (frv_string_begins_with): Likewise. (frv_in_small_data_p): Likewise. * config/gcn/mkoffload.c (STR): Likewise. (main): Likewise. * config/i386/i386-builtins.c (get_builtin_code_for_version): Likewise. * config/i386/i386-options.c (ix86_option_override_internal): Likewise. * config/i386/i386.c (x86_64_elf_section_type_flags): Likewise. (ix86_md_asm_adjust): Likewise. * config/i386/intelmic-mkoffload.c (STR): Likewise. * config/i386/winnt.c (i386_pe_asm_named_section): Likewise. (i386_pe_file_end): Likewise. * config/ia64/ia64.c (ia64_in_small_data_p): Likewise. (ia64_section_type_flags): Likewise. * config/mips/driver-native.c (host_detect_local_cpu): Likewise. * config/mips/mips.c (mips_handle_interrupt_attr): Likewise. (mips16_stub_function_p): Likewise. (mips_function_rodata_section): Likewise. * config/msp430/msp430.c (msp430_mcu_name): Likewise. (msp430_function_section): Likewise. (msp430_section_type_flags): Likewise. (msp430_expand_helper): Likewise. * config/nios2/nios2.c (nios2_small_section_name_p): Likewise. (nios2_valid_target_attribute_rec): Likewise. * config/nvptx/mkoffload.c (process): Likewise. (STR): Likewise. * config/pa/som.h: Likewise. * config/pdp11/pdp11.c (pdp11_output_ident): Likewise. * config/riscv/riscv.c (riscv_elf_select_rtx_section): Likewise. * config/rs6000/rs6000.c (VTABLE_NAME_P): Likewise. (rs6000_inner_target_options): Likewise. * config/s390/driver-native.c (s390_host_detect_local_cpu): Likewise. * config/sparc/driver-sparc.c (host_detect_local_cpu): Likewise. * config/vax/vax.c (vax_output_int_move): Likewise. * config/vms/vms-ld.c (startswith): Likewise. (process_args): Likewise. (main): Likewise. * config/vms/vms.c: Likewise.
2021-05-10arc: Fix compilation warnings.Claudiu Zissulescu1-1/+1
gcc/ 2021-05-10 Claudiu Zissulescu <claziss@synopsys.com> * common/config/arc/arc-common.c (arc_handle_option): Remove dot from string. * config/arc/arc.c (arc_reorg): Remove underscore from string. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2021-04-27Synchronize Rocket Lake's processor_names and processor_cost_table with ↵Cui,Lili1-1/+1
processor_type gcc/ChangeLog * common/config/i386/i386-common.c (processor_names): Sync processor_names with processor_type. * config/i386/i386-options.c (processor_cost_table): Sync processor_cost_table with processor_type.
2021-04-21x86: Add -mmwait for -mgeneral-regs-onlyH.J. Lu1-0/+15
Add -mmwait so that the MWAIT and MONITOR intrinsics can be used with -mgeneral-regs-only and make -msse3 to imply -mmwait. gcc/ * config.gcc: Install mwaitintrin.h for i[34567]86-*-* and x86_64-*-* targets. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_MWAIT_SET): New. (OPTION_MASK_ISA2_MWAIT_UNSET): Likewise. (ix86_handle_option): Handle -mmwait. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Replace OPTION_MASK_ISA_SSE3 with OPTION_MASK_ISA2_MWAIT on __builtin_ia32_monitor and __builtin_ia32_mwait. * config/i386/i386-options.c (isa2_opts): Add -mmwait. (ix86_valid_target_attribute_inner_p): Likewise. (ix86_option_override_internal): Enable mwait/monitor instructions for -msse3. * config/i386/i386.h (TARGET_MWAIT): New. (TARGET_MWAIT_P): Likewise. * config/i386/i386.opt: Add -mmwait. * config/i386/mwaitintrin.h: New file. * config/i386/pmmintrin.h: Include <mwaitintrin.h>. * config/i386/sse.md (sse3_mwait): Replace TARGET_SSE3 with TARGET_MWAIT. (@sse3_monitor_<mode>): Likewise. * config/i386/x86gprintrin.h: Include <mwaitintrin.h>. * doc/extend.texi: Document mwait target attribute. * doc/invoke.texi: Document -mmwait. gcc/testsuite/ * gcc.target/i386/monitor-2.c: New test.
2021-04-12Add rocketlake to gcc.Cui,Lili3-2/+13
gcc/ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle rocketlake. * common/config/i386/i386-common.c (processor_names): Add rocketlake. (processor_alias_table): Add rocketlake. * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ROCKETLAKE. * config.gcc: Add -march=rocketlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle rocketlake. * config/i386/i386-options.c (m_ROCKETLAKE) : Define. (processor_cost_table): Add rocketlake cost. * config/i386/i386.h (ix86_size_cost) : Define TARGET_ROCKETLAKE. (processor_type) : Add PROCESSOR_ROCKETLAKE. (PTA_ROCKETLAKE): Ditto. * doc/extend.texi: Add rocketlake. * doc/invoke.texi: Add rocketlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march
2021-04-12Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2Cui,Lili1-0/+1
Alder Lake Intel Hybrid Technology will not support Intel® AVX-512. ISA features such as Intel® AVX, AVX-VNNI, Intel® AVX2, and UMONITOR/UMWAIT/TPAUSE are supported. gcc/ChangeLog * config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list. * config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE. * common/config/i386/cpuinfo.h (get_intel_cpu): Add AlderLake model. * doc/invoke.texi: Change alderlake ISA list.
2021-03-24i386: fix -march=amd crashMartin Liska1-1/+1
It started with g:3e2ae3ee285a57455d5a23bd352a68c289130186 where new entry was added to processor_alias_table after generic node: + {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0, + M_CPU_TYPE (AMDFAM19H), P_NONE}, and then the following is violated: /* NB: processor_alias_table stops at the "generic" entry. */ gcc/ChangeLog: PR target/99753 * common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one error. * config/i386/i386-options.c (ix86_option_override_internal): Add run-time assert. gcc/testsuite/ChangeLog: PR target/99753 * gcc.target/i386/pr99753.c: New test.
2021-03-23RISC-V: Add riscv{32,64}be with big endian as defaultMarcus Comstedt1-0/+5
gcc/ * common/config/riscv/riscv-common.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config.gcc (riscv32be-*, riscv64be-*): Set TARGET_BIG_ENDIAN_DEFAULT to 1. * config/riscv/elf.h (LINK_SPEC): Change -melf* value depending on default endianness. * config/riscv/freebsd.h (LINK_SPEC): Likewise. * config/riscv/linux.h (LINK_SPEC): Likewise. * config/riscv/riscv.c (TARGET_DEFAULT_TARGET_FLAGS): Set default endianness. * config/riscv/riscv.h (DEFAULT_ENDIAN_SPEC): New macro.
2021-03-09arm: fix bootstrap failure following automatic mode selection patchRichard Earnshaw1-1/+1
Fix a signed vs unsigned comparison in last change. gcc: * common/config/arm/arm-common.c (arm_config_default): Change type of 'i' to unsigned.
2021-03-03arm: Ignore --with-mode when CPU only supports one instruction set.Richard Earnshaw1-6/+43
Arm processors can support up to two instruction sets. Some early cores only support the traditional A32 (Arm) instructions, while some more recent devices only support T32 (Thumb) instructions. When configuring the compiler,--with-mode can be used to select the default instruction set to target if the user has not made an explicit choice, but this can cause needless problems if the default is not supported by the requested CPU. To fix this this patch adjusts the way that the --with-mode selection is processed so that it can take into account the selected CPU or architecture and not create a meaningless combination. gcc: * common/config/arm/arm-common.c: Include configargs.h. (arm_config_default): New function. (arm_target_mode): Renamed from arm_target_thumb_only. Handle processors that do not support Thumb. Take into account the --with-mode configuration setting for selecting the default. * config/arm/arm.h (OPTION_DEFAULT_SPECS): Remove entry for 'mode'. (TARGET_MODE_SPEC_FUNCTIONS): Update for function name change.
2021-03-02IBM Z: arch14: Add command line optionsAndreas Krebbel1-0/+4
Prepare GCC for a future architecture extension. gcc/ChangeLog: * common/config/s390/s390-common.c (processor_flags_table): New entry. * config.gcc: Enable arch14 for --with-arch and --with-tune. * config/s390/driver-native.c (s390_host_detect_local_cpu): Pick arch14 for unknown CPU models. * config/s390/s390-opts.h (enum processor_type): Add PROCESSOR_ARCH14. * config/s390/s390.c (s390_issue_rate): Add case for PROCESSOR_ARCH14. (s390_get_sched_attrmask): Likewise. (s390_get_unit_mask): Likewise. * config/s390/s390.h (enum processor_flags): Add PF_NNPA and PF_ARCH14. (TARGET_CPU_ARCH14, TARGET_CPU_ARCH14_P, TARGET_CPU_NNPA) (TARGET_CPU_NNPA_P, TARGET_ARCH14, TARGET_ARCH14_P, TARGET_NNPA) (TARGET_NNPA_P): New macro definitions. * config/s390/s390.md ("cpu_facility", "enabled"): Add arch14 and nnpa. * config/s390/s390.opt: Add PROCESSOR_ARCH14. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add check for nnpa facility.
2021-01-28RISC-V: Fix -march option parsing when extension exists.Xing GUO1-3/+1
This patch fixes -march option parsing when `p` extension exists, e.g., -march=rv64imafdcp should produce .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_p" rather than .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c_p" gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_subset_list::parsing_subset_version): Fix -march option parsing when `p` extension exists. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-18.c: New test.
2021-01-14i386: Resolve variable shadowing in i386-options.c [PR98671]Uros Bizjak1-1/+1
Also change global variable pta_size to unsigned. 2021-01-14 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/98671 * config/i386/i386-options.c (ix86_valid_target_attribute_inner_p): Remove declaration and initialization of shadow variable "ret". (ix86_option_override_internal): Remove delcaration of shadow variable "i". Redeclare shadowed variable to unsigned. * common/config/i386/i386-common.c (pta_size): Redeclare to unsigned. * config/i386/i386-builtins.c (get_builtin_code_for_version): Update for redeclaration. * config/i386/i386.h (pta_size): Ditto.
2021-01-08RISC-V: Implement new style of architecture extension test macros.Kito Cheng1-0/+5
- This patch introduce new set of architecture extension test macros which is accept on riscv-c-api-doc recently. - https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro - We will also mark deprecated for legacy architecture extension test macros in GCC 11, but still support that for 1 or 2 release cycles. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_current_subset_list): New. * config/riscv/riscv-c.c (riscv-subset.h): New. (INCLUDE_STRING): Define. (riscv_cpu_cpp_builtins): Add new style architecture extension test macros. * config/riscv/riscv-subset.h (riscv_subset_list::begin): New. (riscv_subset_list::end): New. (riscv_current_subset_list): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-10.c: New. * gcc.target/riscv/predef-11.c: New. * gcc.target/riscv/predef-12.c: New. * gcc.target/riscv/predef-13.c: New.
2021-01-08RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.hKito Cheng1-66/+1
Pre-work of new style of architecture extension test macros, we need the list used in `config/riscv/riscv-c.c`, so those struct/class declaration must move to header file rather than local C file. gcc/ChangeLog * common/config/riscv/riscv-common.c (RISCV_DONT_CARE_VERSION): Move to riscv-subset.h. (struct riscv_subset_t): Ditto. (class riscv_subset_list): Ditto. * config/riscv/riscv-subset.h (RISCV_DONT_CARE_VERSION): Move from riscv-common.c. (struct riscv_subset_t): Ditto. (class riscv_subset_list): Ditto. * config/riscv/t-riscv ($(common_out_file)): Add file dependency.
2021-01-04Update copyright years.Jakub Jelinek57-57/+57
2020-12-11Fix feature check for HRESET/AVX_VNNI/UINTRHongyu1-10/+15
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Move check for HRESET/AVX_VNNI/UINTR out of avx512_usable.
2020-12-05X86_64: Enable support for next generation AMD Zen3 CPU.Venkataramanan Kumar3-1/+34
2020-12-03 Venkataramanan Kumar <Venkataramanan.Kumar@amd.com> Sharavan Kumar <Shravan.Kumar@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu) recognize znver3. * common/config/i386/i386-common.c (processor_names): Add znver3. (processor_alias_table): Add znver3 and AMDFAM19H entry. * common/config/i386/i386-cpuinfo.h (processor_types): Add AMDFAM19H. (processor_subtypes): AMDFAM19H_ZNVER3. * config.gcc (i[34567]86-*-linux* | ...): Likewise. * config/i386/driver-i386.c: (host_detect_local_cpu): Let -march=native recognize znver3 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add znver3. * config/i386/i386-options.c (m_znver3): New definition. (m_ZNVER): Include m_znver3. (processor_cost_table): Add znver3. * config/i386/i386.c (ix86_reassociation_width): Likewise. * config/i386/i386.h (TARGET_znver3): New definition. (enum processor_type): Add PROCESSOR_ZNVER3. * config/i386/i386.md (define_attr "cpu"): Add znver3. * config/i386/x86-tune-sched.c: (ix86_issue_rate): Likewise. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS: Likewise. * config/i386/znver1.md: Add new reservations for znver3. * doc/extend.texi: Add details about znver3. * doc/invoke.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv29.C: New file.
2020-11-18RISC-V: Support version controling for ISA standard extensionsKito Cheng1-72/+215
- New option -misa-spec support: -misa-spec=[2.2|20190608|20191213] and corresponding configuration option --with-isa-spec. - Current default ISA spec set to 2.2, but we intend to bump this to 20191213 or later in next release. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_ext_version): New. (riscv_ext_version_table): Ditto. (get_default_version): Ditto. (riscv_subset_t::implied_p): New field. (riscv_subset_t::riscv_subset_t): Init implied_p. (riscv_subset_list::add): New. (riscv_subset_list::handle_implied_ext): Pass riscv_subset_t instead of separated argument. (riscv_subset_list::to_string): Handle zifencei and zicsr, and omit version if version is unknown. (riscv_subset_list::parsing_subset_version): New argument `ext`, remove default_major_version and default_minor_version, get default version info via get_default_version. (riscv_subset_list::parse_std_ext): Update argument for parsing_subset_version calls. Handle 2.2 ISA spec, always enable zicsr and zifencei, they are included in baseline ISA in that time. (riscv_subset_list::parse_multiletter_ext): Update argument for `parsing_subset_version` and `add` calls. (riscv_subset_list::parse): Adjust argument for riscv_subset_list::handle_implied_ext call. * config.gcc (riscv*-*-*): Handle --with-isa-spec=. * config.in (HAVE_AS_MISA_SPEC): New. (HAVE_AS_MARCH_ZIFENCEI): Ditto. * config/riscv/riscv-opts.h (riscv_isa_spec_class): New. (riscv_isa_spec): Ditto. * config/riscv/riscv.h (HAVE_AS_MISA_SPEC): New. (ASM_SPEC): Pass -misa-spec if gas supported. * config/riscv/riscv.opt (riscv_isa_spec_class) New. * configure.ac (HAVE_AS_MARCH_ZIFENCEI): New test. (HAVE_AS_MISA_SPEC): Ditto. * configure: Regen. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-9.c: New. * gcc.target/riscv/arch-10.c: Ditto. * gcc.target/riscv/arch-11.c: Ditto. * gcc.target/riscv/attribute-6.c: Remove, we don't support G with version anymore. * gcc.target/riscv/attribute-8.c: Reorder arch string to fit canonical ordering. * gcc.target/riscv/attribute-9.c: We don't emit version for unknown extensions now. * gcc.target/riscv/attribute-11.c: Add -misa-spec=2.2 flags. * gcc.target/riscv/attribute-12.c: Ditto. * gcc.target/riscv/attribute-13.c: Ditto. * gcc.target/riscv/attribute-14.c: Ditto. * gcc.target/riscv/attribute-15.c: New. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto.
2020-11-18RISC-V: Support zicsr and zifencei extension for -march.Kito Cheng1-0/+6
- CSR related instructions and fence instructions has to be splitted from baseline ISA, zicsr and zifencei are corresponding sub-extension. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_implied_info): d and f implied zicsr. (riscv_ext_flag_table): Handle zicsr and zifencei. * config/riscv/riscv-opts.h (MASK_ZICSR): New. (MASK_ZIFENCEI): Ditto. (TARGET_ZICSR): Ditto. (TARGET_ZIFENCEI): Ditto. * config/riscv/riscv.md (clear_cache): Check TARGET_ZIFENCEI. (fence_i): Ditto. * config/riscv/riscv.opt (riscv_zi_subext): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-8.c: New. * gcc.target/riscv/attribute-14.c: Ditto.
2020-11-18RISC-V: Handle implied extension in canonical ordering.Kito Cheng1-5/+172
- ISA spec has specify the order between multi-letter extensions, implied extension also need to follow store in canonical ordering, so most easy way is we keep that in-order during insertion. gcc/ChangeLog: * common/config/riscv/riscv-common.c (single_letter_subset_rank): New. (multi_letter_subset_rank): Ditto. (subset_cmp): Ditto. (riscv_subset_list::add): Insert subext in canonical ordering. (riscv_subset_list::parse_std_ext): Move handle_implied_ext to ... (riscv_subset_list::parse): ... here.
2020-11-11Support Intel AVX VNNIliuhongt4-1/+23
2020-10-13 Hongtao Liu <hongtao.liu@intel.com> Hongyu Wang <hongyu.wang@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect AVXVNNI. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AVXVNNI_SET, OPTION_MASK_ISA2_AVXVNNI_UNSET): New. (OPTION_MASK_ISA2_AVX2_UNSET): Add AVXVNNI. (ix86_hanlde_option): Handle -mavxvnni, unset avxvnni when avx2 is disabled. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNI. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avxvnni. * config.gcc: Add avxvnniintrin.h. * config/i386/avx512vnnivlintrin.h: Reimplement 128/256 bit non-mask intrinsics with macros to support unified interface. * config/i386/avxvnniintrin.h: New header file. * config/i386/cpuid.h (bit_AVXVNNI): New. * config/i386/i386-builtins.c (def_builtin): Handle AVXVNNI mask for unified builtin. * config/i386/i386-builtin.def (BDESC): Adjust AVX512VNNI builtins for AVXVNNI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AVXVNNI__. * config/i386/i386-expand.c (ix86_expand_builtin): Handle bisa for AVXVNNI to support unified intrinsic name, since there is no dependency between AVX512VNNI and AVXVNNI. * config/i386/i386-options.c (isa2_opts): Add -mavxvnni. (ix86_valid_target_attribute_inner_p): Handle avxnnni. (ix86_option_override_internal): Ditto. * config/i386/i386.h (TARGET_AVXVNNI, TARGET_AVXVNNI_P, TARGET_AVXVNNI_P, PTA_AVXVNNI): New. (PTA_SAPPHIRERAPIDS): Add AVX_VNNI. (PTA_ALDERLAKE): Likewise. * config/i386/i386.md ("isa"): Add avxvnni, avx512vnnivl. ("enabled"): Adjust for avxvnni and avx512vnnivl. * config/i386/i386.opt: Add option -mavxvnni. * config/i386/immintrin.h: Include avxvnniintrin.h. * config/i386/sse.md (vpdpbusd_<mode>): Adjust for AVXVNNI. (vpdpbusds_<mode>): Likewise. (vpdpwssd_<mode>): Likewise. (vpdpwssds_<mode>): Likewise. (vpdpbusd_v16si): New. (vpdpbusds_v16si): Likewise. (vpdpwssd_v16si): Likewise. (vpdpwssds_v16si): Likewise. * doc/invoke.texi: Document -mavxvnni. * doc/extend.texi: Document avxvnni. * doc/sourcebuild.texi: Document target avxvnni. gcc/testsuite/ * gcc.target/i386/avx512vl-vnni-1.c: Rename.. * gcc.target/i386/avx512vl-vnni-1a.c: To This. * gcc.target/i386/avx512vl-vnni-1b.c: New test. * gcc.target/i386/avx512vl-vnni-2.c: Ditto. * gcc.target/i386/avx512vl-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-1.c: Ditto. * gcc.target/i386/avx-vnni-2.c: Ditto. * gcc.target/i386/avx-vnni-3.c: Ditto. * gcc.target/i386/avx-vnni-4.c: Ditto. * gcc.target/i386/avx-vnni-5.c: Ditto. * gcc.target/i386/avx-vnni-6.c: Ditto. * gcc.target/i386/avx-vpdpbusd-2.c: Ditto. * gcc.target/i386/avx-vpdpbusds-2.c: Ditto. * gcc.target/i386/avx-vpdpwssd-2.c: Ditto. * gcc.target/i386/avx-vpdpwssds-2.c: Ditto. * gcc.target/i386/vnni_inline_error.c: Ditto. * gcc.target/i386/avx512vnnivl-builtin.c: Ditto. * gcc.target/i386/avxvnni-builtin.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -mavxvnni. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * lib/target-supports.exp (check_effective_target_avxvnni): New proc.
2020-11-06RISC-V: Mark non-export symbol static and const in riscv-common.cKito Cheng1-2/+2
gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_implied_info): Add static and const. (riscv_subset_list::handle_implied_ext): Add const due to riscv_implied_info changed to const.
2020-11-02RISC-V: Check multiletter extension has more than 1 letterKito Cheng1-0/+8
gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_subset_list::parse_multiletter_ext): Checking multiletter extension has more than 1 letter. gcc/testsuite/ChangeLog * gcc.target/riscv/arch-7.c: New. * gcc.target/riscv/attribute-10.c: Update test arch string.
2020-10-29Enable GCC to support Intel Key Locker ISAliuhongt4-18/+93
gcc/ChangeLog 2018-12-15 Xuepeng Guo <xuepeng.guo@intel.com> Hongyu Wang <hongyu.wang@intel.com> Hongtao Liu <hongtao.liu@intel.com> * common/config/i386/cpuinfo.h (get_available_features): Detect KL, AESKLE and WIDEKL features. * common/config/i386/i386-common.c (OPTION_MASK_ISA_KL_SET): New. (OPTION_MASK_ISA_WIDEKL_SET): Likewise. (OPTION_MASK_ISA_KL_UNSET): Likewise. (OPTION_MASK_ISA_WIDEKL_UNSET): Likewise. (OPTION_MASK_ISA2_AVX2_UNSET): Likewise. (OPTION_MASK_ISA2_AVX_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_1_UNSET): Likewise. (OPTION_MASK_ISA2_SSE4_UNSET): Likewise. (OPTION_MASK_ISA2_SSSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE3_UNSET): Likewise. (OPTION_MASK_ISA2_SSE2_UNSET): Likewise. (OPTION_MASK_ISA2_SSE_UNSET): Likewise. (ix86_handle_option): Handle kl and widekl, add dependency chain for KL and SSE2. * common/config/i386/i386-cpuinfo.h (enum processor_features): (FEATURE_KL, FEATURE_AESKLE, FEATURE_WIDEKL): New. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for KL, AESKLE and WIDEKL. * config.gcc: Add keylockerintrin.h. * doc/invoke.texi: Document new option -mkl and -mwidekl. * doc/extend.texi: Document kl and widekl. * config/i386/cpuid.h (bit_KL, bit_AESKLE, bit_WIDEKL): New. * config/i386/i386-builtin-types.def ((UINT, UINT, V2DI, V2DI, PVOID), (UINT, UINT, V2DI, PVOID), (VOID, V2DI, V2DI, V2DI, UINT), (UINT8, PV2DI, V2DI, PCVOID), (UINT8, PV2DI, PCV2DI, PCVOID)): New function types. * config/i386/i386-builtin.def: Add __builtin_ia32_loadiwkey, __builtin_ia32_aesdec128kl_u8, __builtin_ia32_aesdec256kl_u8, __builtin_ia32_aesenc128kl_u8, __builtin_ia32_aesenc256kl_u8, __builtin_ia32_aesdecwide128kl_u8, __builtin_ia32_aesdecwide256kl_u8, __builtin_ia32_aesencwide128kl_u8, __builtin_ia32_aesencwide256kl_u8, __builtin_ia32_encodekey128_u32, __builtin_ia32_encodekey256_u32. * config/i386/i386-c.c (ix86_target_macros_internal): Handle kl and widekl. * config/i386/i386-options.c (isa2_opts): Add -mkl and -mwidekl. (ix86_option_override_internal): Handle KL and WIDEKL. (ix86_valid_target_attribute_inner_p): Add attribute for kl and widekl. * config/i386/i386-expand.c (ix86_expand_builtin): Expand Keylocker Builtins. * config/i386/i386.h (TARGET_KL): New. (TARGET_KL_P): Likewise. (TARGET_WIDEKL): Likewise. (TARGET_WIDEKL_P): Likewise. (PTA_KL): Likewise. (PTA_WIDEKL): Likewise. (PTA_TIGERLAKE): Add PTA_KL, PTA_WIDEKL. (PTA_ALDERLAKE): Likewise. * config/i386/i386.opt: Add new option mkl and mwidekl. * config/i386/keylockerintrin.h: New header file for Keylocker. * config/i386/immintrin.h: Include keylockerintrin.h. * config/i386/predicates.md (encodekey128_operation): New predicate. (encodekey256_operation): Likewise. (aeswidekl_operation): Likewise. * config/i386/sse.md (UNSPECV_LOADIWKEY): New. (UNSPECV_AESDEC128KLU8): Likewise. (UNSPECV_AESENC128KLU8): Likewise. (UNSPECV_AESDEC256KLU8): Likewise. (UNSPECV_AESENC256KLU8): Likewise. (UNSPECV_AESDECWIDE128KLU8): Likewise. (UNSPECV_AESENCWIDE128KLU8): Likewise. (UNSPECV_AESDECWIDE256KLU8): Likewise. (UNSPECV_AESENCWIDE256KLU8): Likewise. (UNSPECV_ENCODEKEY128U32): Likewise. (UNSPECV_ENCODEKEY256U32): Likewise. (encodekey128u32): New expander. (encodekey256u32): Likewise. (aes<aeswideklvariant>u8): Likewise. (loadiwkey): New insn pattern. (*encodekey128u32): Likewise. (*encodekey256u32): Likewise. (aes<aesklvariant>u8): Likewise. (*aes<aeswideklvariant>u8): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/keylocker-aesdec128kl.c: New test. * gcc.target/i386/keylocker-aesdec256kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesdecwide256kl.c: Likewise. * gcc.target/i386/keylocker-aesenc128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide128kl.c: Likewise. * gcc.target/i386/keylocker-aesencwide256kl.c: Likewise. * gcc.target/i386/keylocker-encodekey128.c: Likewise. * gcc.target/i386/keylocker-encodekey256.c: Likewise. * gcc.target/i386/keylocker-loadiwkey.c: Likewise. * g++.dg/other/i386-2.C: Add -mkl and -mwidekl. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Add kl and widekl. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/funcspec-56.inc: Add new target attribute test.
2020-10-27RISC-V: Refine riscv_parse_arch_stringKito Cheng1-33/+51
- Generalize logic for translating arch to internal flags, this patch is infrastructure for supporing sub-extension parsing. gcc/ChangeLog * common/config/riscv/riscv-common.c (opt_var_ref_t): New. (riscv_ext_flag_table_t): New. (riscv_ext_flag_table): New. (riscv_parse_arch_string): Pass gcc_options* instead of &opts->x_target_flags only, and using riscv_arch_option_table to setup flags. (riscv_handle_option): Update argument for riscv_parse_arch_string. (riscv_expand_arch): Ditto. (riscv_expand_arch_from_cpu): Ditto.
2020-10-15RISC-V: Add support for -mcpu option.Kito Cheng1-5/+86
- The behavior of -mcpu basically equal to -march plus -mtune, but it has lower priority than -march and -mtune. - The behavior and available options has sync with clang except we don't add few LLVM specific value, and add more sifive processor to the list. - -mtune also accept all available options of -mcpu, and use it setting. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_cpu_tables): New. (riscv_arch_str): Return empty string if current_subset_list is NULL. (riscv_find_cpu): New. (riscv_handle_option): Verify option value of -mcpu. (riscv_expand_arch): Using std::string. (riscv_default_mtune): New. (riscv_expand_arch_from_cpu): Ditto. * config/riscv/riscv-cores.def: New. * config/riscv/riscv-protos.h (riscv_find_cpu): New. (riscv_cpu_info): New. * config/riscv/riscv.c (riscv_tune_info): Rename ... (riscv_tune_param): ... to this. (riscv_cpu_info): Rename ... (riscv_tune_info): ... to this. (tune_info): Rename ... (tune_param): ... to this. (rocket_tune_info): Update data type name. (sifive_7_tune_info): Ditto. (optimize_size_tune_info): Ditto. (riscv_cpu_info_table): Rename ... (riscv_tune_info_table): ... to this. (riscv_parse_cpu): Rename ... (riscv_parse_tune): ... to this, and translate valid -mcpu option to -mtune option. (riscv_rtx_costs): Rename tune_info to tune_param. (riscv_class_max_nregs): Ditto. (riscv_memory_move_cost): Ditto. (riscv_init_machine_status): Use value of -mcpu if -mtune is not given, and rename tune_info to tune_param. * config/riscv/riscv.h (riscv_expand_arch_from_cpu): New. (riscv_default_mtune): Ditto. (EXTRA_SPEC_FUNCTIONS): Add riscv_expand_arch_from_cpu and riscv_default_mtune. (OPTION_DEFAULT_SPECS): Handle default value of -march/-mabi. (DRIVER_SELF_SPECS): Expand -march from -mcpu if -march is not given. * config/riscv/riscv.opt (-mcpu): New option. * config/riscv/t-riscv ($(common_out_file)): Add riscv-cores.def to dependency. * doc/invoke.texi (RISC-V Option): Add -mcpu, and update the description of default value for -mtune and -march. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-1.c: New. * gcc.target/riscv/mcpu-2.c: Ditto. * gcc.target/riscv/mcpu-3.c: Ditto. * gcc.target/riscv/mcpu-4.c: Ditto. * gcc.target/riscv/mcpu-5.c: Ditto. * gcc.target/riscv/mcpu-6.c: Ditto. * gcc.target/riscv/mcpu-7.c: Ditto.
2020-10-15Enable Intel HRESET InstructionHongyu Wang4-0/+20
gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -mhreset. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add mhreset. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-10-15Enable gcc support for UINTRliuhongt4-0/+19
2020-05-20 Hongtao Liu <hongtao.liu@intel.com> gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect UINTR. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR_UNSET): New. (ix86_handle_option): Handle -muintr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_UINTR. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for uintr. * config.gcc: Add uintrintrin.h to extra_headers. * config/i386/uintrintrin.h: New. * config/i386/cpuid.h (bit_UINTR): New. * config/i386/i386-builtin-types.def: Add new types. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins): Add __builtin_ia32_testui. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_TESTUI. * config/i386/i386-c.c (ix86_target_macros_internal): Define __UINTR__. * config/i386/i386-expand.c (ix86_expand_special_args_builtin): Handle UINT8_FTYPE_VOID. (ix86_expand_builtin): Handle IX86_BUILTIN_TESTUI. * config/i386/i386-options.c (isa2_opts): Add -muintr. (ix86_valid_target_attribute_inner_p): Handle UINTR. (ix86_option_override_internal): Add TARGET_64BIT check for UINTR. * config/i386/i386.h (TARGET_UINTR, TARGET_UINTR_P, PTA_UINTR): New. (PTA_SAPPHIRRAPIDS): Add PTA_UINTR. * config/i386/i386.opt: Add -muintr. * config/i386/i386.md (define_int_iterator UINTR_UNSPECV): New. (define_int_attr uintr_unspecv): New. (uintr_<uintr_unspecv>, uintr_senduipi, testui): New define_insn patterns. * config/i386/x86gprintrin.h: Include uintrintrin.h * doc/invoke.texi: Document -muintr. * doc/extend.texi: Document uintr. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/uintr-1.c: New test. * gcc.target/i386/uintr-2.c: Ditto. * gcc.target/i386/uintr-3.c: Ditto. * gcc.target/i386/uintr-4.c: Ditto. * gcc.target/i386/uintr-5.c: Ditto. * gcc.target/i386/x86gprintrin-1.c: Add -muintr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add muintr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto.
2020-10-01PR target/97250: i386: Add support for x86-64-v2, x86-64-v3, x86-64-v4 ↵Florian Weimer1-3/+7
levels for x86-64 These micro-architecture levels are defined in the x86-64 psABI: https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9 PTA_NO_TUNE is introduced so that the new processor alias table entries do not affect the CPU tuning setting in ix86_tune. The tests depend on the macros added in commit 92e652d8c21bd7e66cbb0f900 ("i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on ISA flags"). gcc/: PR target/97250 * config/i386/i386.h (PTA_NO_TUNE, PTA_X86_64_BASELINE) (PTA_X86_64_V2, PTA_X86_64_V3, PTA_X86_64_V4): New. * common/config/i386/i386-common.c (processor_alias_table): Add "x86-64-v2", "x86-64-v3", "x86-64-v4". * config/i386/i386-options.c (ix86_option_override_internal): Handle new PTA_NO_TUNE processor table entries. * doc/invoke.texi (x86 Options): Document new -march values. gcc/testsuite/: PR target/97250 * gcc.target/i386/x86-64-v2.c: New test. * gcc.target/i386/x86-64-v3.c: New test. * gcc.target/i386/x86-64-v3-haswell.c: New test. * gcc.target/i386/x86-64-v3-skylake.c: New test. * gcc.target/i386/x86-64-v4.c: New test.
2020-09-28Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.liuhongt4-0/+72
AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud AMX-BF16:tdpbf16ps gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET, OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET, OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET, OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET): New marcos. (ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16. * common/config/i386/cpuinfo.h (XSTATE_TILECFG, XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro. (get_available_features): Enable AMX features only if their states are suoorited by OSXSAVE. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for amx-tile, amx-int8, amx-bf16. * config.gcc: Add amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h to extra headers. * config/i386/amxbf16intrin.h: New file. * config/i386/amxint8intrin.h: Ditto. * config/i386/amxtileintrin.h: Ditto. * config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8): New macro. * config/i386/i386-c.c (ix86_target_macros_internal): Define __AMX_TILE__, __AMX_INT8__, AMX_BF16__. * config/i386/i386-options.c (ix86_target_string): Add -mamx-tile, -mamx-int8, -mamx-bf16. (ix86_option_override_internal): Handle AMX-TILE, AMX-INT8, AMX-BF16. * config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P, TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P, PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros. * config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16. * config/i386/immintrin.h: Include amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h. * doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16. * doc/extend.texi: Document amx-tile, amx-int8, amx-bf16. * doc/sourcebuild.texi ((Effective-Target Keywords, Other hardware attributes): Document amx_int8, amx_tile, amx_bf16. gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_amx_tile, check_effective_target_amx_int8, check_effective_target_amx_bf16): New proc. * g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/amx-check.h: New header file. * gcc.target/i386/amxbf16-asmatt-1.c: New test. * gcc.target/i386/amxint8-asmatt-1.c: New test. * gcc.target/i386/amxtile-asmatt-1.c: Ditto. * gcc.target/i386/amxbf16-asmintel-1.c: Ditto. * gcc.target/i386/amxint8-asmintel-1.c: Ditto. * gcc.target/i386/amxtile-asmintel-1.c: Ditto. * gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto. * gcc.target/i386/amxint8-dpbssd-2.c: Ditto. * gcc.target/i386/amxint8-dpbsud-2.c: Ditto. * gcc.target/i386/amxint8-dpbusd-2.c: Ditto. * gcc.target/i386/amxint8-dpbuud-2.c: Ditto. * gcc.target/i386/amxtile-2.c: Ditto.
2020-09-17If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx.liuhongt1-2/+3
Current status is -mno-avx implies -mno-xsave which should be wrong. gcc/ChangeLog * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX_UNSET): Remove OPTION_MASK_ISA_XSAVE_UNSET. (OPTION_MASK_ISA_XSAVE_UNSET): Add OPTION_MASK_ISA_AVX_UNSET. gcc/testsuite/ChangeLog * gcc.target/i386/xsave-avx-1.c: New test.
2020-09-10aarch64: Add support for Armv8-RAlex Coplan1-2/+5
This adds support for Armv8-R AArch64 to GCC. It adds the -march value armv8-r and sets the ACLE feature macro __ARM_ARCH_PROFILE correctly when -march is set to armv8-r. gcc/ChangeLog: * common/config/aarch64/aarch64-common.c (aarch64_get_extension_string_for_isa_flags): Don't force +crc for Armv8-R. * config/aarch64/aarch64-arches.def: Add entry for Armv8-R. * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): Set __ARM_ARCH_PROFILE correctly for Armv8-R. * config/aarch64/aarch64.h (AARCH64_FL_V8_R): New. (AARCH64_FL_FOR_ARCH8_R): New. (AARCH64_ISA_V8_R): New. * doc/invoke.texi: Add Armv8-R to architecture table. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/armv8-r.c: New test.
2020-09-08MSP430: Use enums to handle -mcpu= valuesJozef Lawrynowicz1-23/+3
The -mcpu= option accepts only a handful of string values. Using enums instead of strings to handle the accepted values removes the need to have specific processing of the strings in the backend, and simplifies any comparisons which need to be performed on the value. It also allows the default value to have semantic equivalence to a user set value, whilst retaining the ability to differentiate between them. Practically, this allows a user set -mcpu= value to override the the ISA set by -mmcu, whilst the default -mcpu= value can still have an explicit meaning. gcc/ChangeLog: * common/config/msp430/msp430-common.c (msp430_handle_option): Remove OPT_mcpu_ handling. Set target_cpu value to new enum values when parsing certain -mmcu= values. * config/msp430/msp430-opts.h (enum msp430_cpu_types): New. * config/msp430/msp430.c (msp430_option_override): Handle new target_cpu enum values. Set target_cpu using extracted value for given MCU when -mcpu= option is not passed by the user. * config/msp430/msp430.opt: Handle -mcpu= values using enums. gcc/testsuite/ChangeLog: * gcc.target/msp430/mcpu-is-430.c: New test. * gcc.target/msp430/mcpu-is-430x.c: New test. * gcc.target/msp430/mcpu-is-430xv2.c: New test.
2020-08-28Fix: AVX512VP2INTERSECT should imply AVX512DQ.liuhongt1-2/+2
gcc/ChangeLog * common/config/i386/i386-common.c (ix86_handle_option): Set AVX512DQ when AVX512VP2INTERSECT exists.
2020-08-19x86: Detect Rocket Lake and Alder LakeH.J. Lu1-0/+10
From arch/x86/include/asm/intel-family.h on Linux kernel master branch: #define INTEL_FAM6_ROCKETLAKE 0xA7 #define INTEL_FAM6_ALDERLAKE 0x97 * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Rocket Lake and Alder Lake.
2020-07-10Initial Sapphire Rapids and Alder Lake support from ISA r40Cui,Lili3-0/+16
gcc/ * common/config/i386/cpuinfo.h (get_intel_cpu): Handle sapphirerapids. * common/config/i386/i386-common.c (processor_names): Add sapphirerapids and alderlake. (processor_alias_table): Add sapphirerapids and alderlake. * common/config/i386/i386-cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ALDERLAKE and INTEL_COREI7_ALDERLAKE. * config.gcc: Add -march=sapphirerapids and alderlake. * config/i386/driver-i386.c (host_detect_local_cpu) Handle sapphirerapids and alderlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle sapphirerapids and alderlake. * config/i386/i386-options.c (m_SAPPHIRERAPIDS) : Define. (m_ALDERLAKE): Ditto. (m_CORE_AVX512) : Add m_SAPPHIRERAPIDS. (processor_cost_table): Add sapphirerapids and alderlake. (ix86_option_override_internal) Handle PTA_WAITPKG, PTA_ENQCMD, PTA_CLDEMOTE, PTA_SERIALIZE, PTA_TSXLDTRK. * config/i386/i386.h (ix86_size_cost) : Define SAPPHIRERAPIDS and ALDERLAKE. (processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and PROCESSOR_ALDERLAKE. (PTA_ENQCMD): New. (PTA_CLDEMOTE): Ditto. (PTA_SERIALIZE): Ditto. (PTA_TSXLDTRK): New. (PTA_SAPPHIRERAPIDS): Ditto. (PTA_ALDERLAKE): Ditto. (processor_type) : Add PROCESSOR_SAPPHIRERAPIDS and PROCESSOR_ALDERLAKE. * doc/extend.texi: Add sapphirerapids and alderlake. * doc/invoke.texi: Add sapphirerapids and alderlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march
2020-07-01RISC-V: Preserve arch version info during normalizing arch stringKito Cheng1-24/+46
- Arch version should preserved if user explicitly specified the version. e.g. After normalize, -march=rv32if3d should be -march=rv32i_f3p0d instead of-march=rv32ifd. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_subset_t): New field added. (riscv_subset_list::parsing_subset_version): Add parameter for indicate explicitly version, and handle explicitly version. (riscv_subset_list::handle_implied_ext): Ditto. (riscv_subset_list::add): Ditto. (riscv_subset_t::riscv_subset_t): Init new field. (riscv_subset_list::to_string): Always output version info if version explicitly specified. (riscv_subset_list::parsing_subset_version): Handle explicitly arch version. (riscv_subset_list::parse_std_ext): Ditto. (riscv_subset_list::parse_multiletter_ext): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-13.c: New.
2020-06-24x86: Remove brand ID check for Intel processorsH.J. Lu1-7/+5
Brand ID was a feature that briefly existed in some Pentium III and Pentium 4 CPUs. The CPUs that had non-zero brand ID still have had valid family/model. Brand ID just gives a marketing name for the CPU. Remove the extra code for brand ID check. gcc/ PR target/95660 * common/config/i386/cpuinfo.h (get_intel_cpu): Remove brand_id. (cpu_indicator_init): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Updated. gcc/testsuite/ PR target/95660 * gcc.target/i386/builtin_target.c (check_detailed): Updated.
2020-06-24x86: Add Cooper Lake detection with AVX512BF16H.J. Lu1-1/+9
All Sky Lake family processors have the same CPUID model number, 0x55. The differences are Cascade Lake has AVX512VNNI and Cooper Lake has AVX512VNNI + AVX512BF16. Check AVX512BF16 for Cooper Lake. PR target/95774 * common/config/i386/cpuinfo.h (get_intel_cpu): Add Cooper Lake detection with AVX512BF16.
2020-06-24x86: Share _isa_names_table and use cpuinfo.hH.J. Lu1-0/+163
Both driver-i386.c and libgcc use CPUID to detect the processor name as well as available ISAs. To detect the same processor or ISAs, the same detection logic is duplicated in 2 places. Sometimes only one place was up to date or got it right. Sometimes both places got it wrong. 1. Add common/config/i386/i386-isas.h to define _isa_names_table. 2. Use isa_names_table to auto-generate ISA command-line options. 3. Use isa_names_table to auto-generate __builtin_cpu_supports tests. 4. Use common/config/i386/cpuinfo.h to check available ISAs and detect newer Intel processors in driver-i386.c and builtin_target.c. 5. Detection of AMD processors and older processors in driver-i386.c is unchanged. gcc/ PR target/95843 * common/config/i386/i386-isas.h: New file. Extracted from gcc/config/i386/i386-builtins.c. (_isa_names_table): Add option. (ISA_NAMES_TABLE_START): New. (ISA_NAMES_TABLE_END): Likewise. (ISA_NAMES_TABLE_ENTRY): Likewise. (isa_names_table): Defined with ISA_NAMES_TABLE_START, ISA_NAMES_TABLE_END and ISA_NAMES_TABLE_ENTRY. Add more ISAs from enum processor_features. * config/i386/driver-i386.c: Include "common/config/i386/cpuinfo.h" and "common/config/i386/i386-isas.h". (has_feature): New macro. (host_detect_local_cpu): Call cpu_indicator_init to get CPU features. Use has_feature to detect processor features. Call Call get_intel_cpu to get the newer Intel CPU name. Use isa_names_table to generate command-line options. * config/i386/i386-builtins.c: Include "common/config/i386/i386-isas.h". (_arch_names_table): Removed. (isa_names_table): Likewise. gcc/testsuite/ PR target/95843 * gcc.target/i386/builtin_target.c: Include <stdlib.h>, ../../../common/config/i386/i386-cpuinfo.h and ../../../common/config/i386/cpuinfo.h. (check_amd_cpu_model): Removed. (check_intel_cpu_model): Likewise, (CHECK___builtin_cpu_is): New. (gcc_assert): New. Defined as assert. (gcc_unreachable): New. Defined as abort. (inline): New. Defined as empty. (ISA_NAMES_TABLE_START): Likewise. (ISA_NAMES_TABLE_END): Likewise. (ISA_NAMES_TABLE_ENTRY): New. (check_features): Include "../../../common/config/i386/i386-isas.h". (check_detailed): Call cpu_indicator_init. Always call check_features. Call get_amd_cpu instead of check_amd_cpu_model. Call get_intel_cpu instead of check_intel_cpu_model.
2020-06-24x86: Move cpuinfo.h from libgcc to common/config/i386H.J. Lu2-0/+942
Both x86 backend and libgcc define enum processor_features. libgcc sets enum processor_feature and x86 backend checks enum processor_feature. They are very easy out of sync and it has happened multiple times in the past. 1. Move cpuinfo.h from libgcc to common/config/i386 so that we can share the same enum processor_features in x86 backend and libgcc. 2. Change __cpu_features2 to an array to support more processor features. 3. Add more processor features to enum processor_features. gcc/ PR target/95259 * common/config/i386/cpuinfo.h: New file. (__processor_model): Moved from libgcc/config/i386/cpuinfo.h. (__processor_model2): New. (CHECK___builtin_cpu_is): New. Defined as empty if not defined. (has_cpu_feature): New function. (set_cpu_feature): Likewise. (get_amd_cpu): Moved from libgcc/config/i386/cpuinfo.c. Use CHECK___builtin_cpu_is. Return AMD CPU name. (get_intel_cpu): Moved from libgcc/config/i386/cpuinfo.c. Use Use CHECK___builtin_cpu_is. Return Intel CPU name. (get_available_features): Moved from libgcc/config/i386/cpuinfo.c. Also check FEATURE_3DNOW, FEATURE_3DNOWP, FEATURE_ADX, FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT, FEATURE_CLWB, FEATURE_CLZERO, FEATURE_CMPXCHG16B, FEATURE_CMPXCHG8B, FEATURE_ENQCMD, FEATURE_F16C, FEATURE_FSGSBASE, FEATURE_FXSAVE, FEATURE_HLE, FEATURE_IBT, FEATURE_LAHF_LM, FEATURE_LM, FEATURE_LWP, FEATURE_LZCNT, FEATURE_MOVBE, FEATURE_MOVDIR64B, FEATURE_MOVDIRI, FEATURE_MWAITX, FEATURE_OSXSAVE, FEATURE_PCONFIG, FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW, FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED, FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA, FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES, FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC, FEATURE_XSAVEOPT and FEATURE_XSAVES (cpu_indicator_init): Moved from libgcc/config/i386/cpuinfo.c. Also update cpu_model2. * common/config/i386/i386-cpuinfo.h (processor_vendor): Add Add VENDOR_CENTAUR, VENDOR_CYRIX and VENDOR_NSC. (processor_features): Moved from gcc/config/i386/i386-builtins.c. Renamed F_XXX to FEATURE_XXX. Add FEATURE_3DNOW, FEATURE_3DNOWP, FEATURE_ADX, FEATURE_ABM, FEATURE_CLDEMOTE, FEATURE_CLFLUSHOPT, FEATURE_CLWB, FEATURE_CLZERO, FEATURE_CMPXCHG16B, FEATURE_CMPXCHG8B, FEATURE_ENQCMD, FEATURE_F16C, FEATURE_FSGSBASE, FEATURE_FXSAVE, FEATURE_HLE, FEATURE_IBT, FEATURE_LAHF_LM, FEATURE_LM, FEATURE_LWP, FEATURE_LZCNT, FEATURE_MOVBE, FEATURE_MOVDIR64B, FEATURE_MOVDIRI, FEATURE_MWAITX, FEATURE_OSXSAVE, FEATURE_PCONFIG, FEATURE_PKU, FEATURE_PREFETCHWT1, FEATURE_PRFCHW, FEATURE_PTWRITE, FEATURE_RDPID, FEATURE_RDRND, FEATURE_RDSEED, FEATURE_RTM, FEATURE_SERIALIZE, FEATURE_SGX, FEATURE_SHA, FEATURE_SHSTK, FEATURE_TBM, FEATURE_TSXLDTRK, FEATURE_VAES, FEATURE_WAITPKG, FEATURE_WBNOINVD, FEATURE_XSAVE, FEATURE_XSAVEC, FEATURE_XSAVEOPT, FEATURE_XSAVES and CPU_FEATURE_MAX. (SIZE_OF_CPU_FEATURES): New. * config/i386/i386-builtins.c (processor_features): Removed. (isa_names_table): Replace F_XXX with FEATURE_XXX. (fold_builtin_cpu): Change __cpu_features2 to an array. libgcc/ PR target/95259 * config/i386/cpuinfo.c: Don't include "cpuinfo.h". Include "common/config/i386/i386-cpuinfo.h" and "common/config/i386/cpuinfo.h". (__cpu_features2): Changed to array. (get_amd_cpu): Removed. (get_intel_cpu): Likewise. (get_available_features): Likewise. (__cpu_indicator_init): Call cpu_indicator_init. * config/i386/cpuinfo.h: Removed.
2020-06-24x86: Fold arch_names_table into processor_alias_tableH.J. Lu2-90/+283
In i386-builtins.c, arch_names_table is used to to map architecture name string to internal model. A switch statement is used to map internal processor name to architecture name string and internal priority. model and priority are added to processor_alias_table so that a single entry contains architecture name string, internal processor name, internal model and internal priority. 6 entries are appended for i386-builtins.c, which have special architecture name strings: amd, amdfam10h, amdfam15h, amdfam17h, shanghai and istanbul, and pta_size is adjusted to exclude them. Entries which are not used by i386-builtins.c have internal model 0. P_PROC_DYNAMIC is added to internal priority to make entries with dynamic architecture name string or priority. PR target/95842 * common/config/i386/i386-common.c (processor_alias_table): Add processor model and priority to each entry. (pta_size): Updated with -6. (num_arch_names): New. * common/config/i386/i386-cpuinfo.h: New file. * config/i386/i386-builtins.c (feature_priority): Removed. (processor_model): Likewise. (_arch_names_table): Likewise. (arch_names_table): Likewise. (_isa_names_table): Replace P_ZERO with P_NONE. (get_builtin_code_for_version): Replace P_ZERO with P_NONE. Use processor_alias_table. (fold_builtin_cpu): Replace arch_names_table with processor_alias_table. * config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h". (pta): Add model and priority. (num_arch_names): New.
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