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2025-04-13s390: Support z17 processor nameStefan Schulze Frielinghaus1-2/+2
2025-04-01target/119549 - fixup handling of -mno-sse4 in target attributeRichard Biener1-0/+2
2025-03-24i386: Raise deprecate warning for -mavx10.1-256/512 and -mevex512 while add -...Haochen Jiang4-16/+17
2025-03-24i386: Remove avx10.2-256 and avx10.2-512 optionsHaochen Jiang4-51/+22
2025-03-22AVR: target/119421 Better optimize some bit operations.Georg-Johann Lay1-0/+1
2025-03-13libgcc: Remove PREDRES and LS64 from AArch64 cpuinfoWilco Dijkstra1-4/+4
2025-03-06AArch64: Enable early scheduling for -O3 and higher (PR118351)Wilco Dijkstra1-1/+3
2025-03-03aarch64: Ignore target pragmas while defining intrinsicsAndrew Carlotti1-2/+17
2025-03-01[PR target/118906] [PATCH v2] RISC-V: Fix a typo in zce to zcf implicationYuriy Kolerov1-1/+1
2025-02-17i386: Re-alias avx10.2 to 512 bit and deprecate -mno-avx10.2-[256,512]Haochen Jiang2-14/+9
2025-02-17i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole...Haochen Jiang2-11/+8
2025-02-14GCN: Set 'UI_TARGET' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282, PR113331]Thomas Schwinge1-1/+1
2025-02-14nvptx: Set 'UI_TARGET' for 'TARGET_EXCEPT_UNWIND_INFO' [PR86660]Thomas Schwinge1-1/+1
2025-01-24aarch64: Make AARCH64_FL_CRYPTO always unsetAndrew Carlotti1-0/+4
2025-01-24aarch64: Refactor aarch64_rewrite_mcpuAndrew Carlotti1-61/+17
2025-01-24aarch64: Rewrite architecture strings for assemblerAndrew Carlotti1-4/+45
2025-01-24aarch64: Inline aarch64_get_all_extension_candidatesAndrew Carlotti1-11/+4
2025-01-24aarch64: Move arch/cpu parsing to aarch64-common.ccAndrew Carlotti1-6/+328
2025-01-24aarch64: Rename info structs in aarch64-common.ccAndrew Carlotti1-23/+27
2025-01-24aarch64: Remove redundant generic cpu entryAndrew Carlotti1-1/+0
2025-01-20s390: arch15: Prepare for a future architectureStefan Schulze Frielinghaus1-1/+5
2025-01-17RISC-V: Add Zicfilp ISA extension.Monk Chiang1-0/+3
2025-01-17RISC-V: Add Zicfiss ISA extension.Monk Chiang1-0/+7
2025-01-09i386: Remove not used model number for Diamond RapidsHaochen Jiang1-1/+0
2025-01-07AArch64: Switch off early schedulingWilco Dijkstra1-0/+2
2025-01-02Update copyright years.Jakub Jelinek56-56/+56
2024-12-20RISC-V: List valid -mtune options only onceChristoph Müllner1-1/+13
2024-12-17RISC-V: Remove svvptc from riscv-ext-bitmask.defYangyu Chen1-1/+0
2024-12-06AVR: Disable generation of CRC lookup tables.Georg-Johann Lay1-0/+2
2024-12-05AVR: target/107957 - Split multi-byte loads and stores.Georg-Johann Lay1-0/+1
2024-11-29AArch64: Suppress default options when march or mcpu used is not affected by it.Tamar Christina1-0/+27
2024-11-27diagnostics: replace %<%s%> with %qs [PR104896]David Malcolm2-2/+2
2024-11-25nios2: Remove all support for Nios II target.Sandra Loosemore1-43/+0
2024-11-25RISC-V: Minimal support for svvptc extension.Dongyan Chen2-0/+3
2024-11-22build: Remove INCLUDE_MEMORY [PR117737]Andrew Pinski3-3/+0
2024-11-22AVR: Tabify avr-common.cc according to coding rules.Georg-Johann Lay1-26/+26
2024-11-22AVR: Use Var(avropt_xxx) for option variables in avr.opt.Georg-Johann Lay1-4/+4
2024-11-21AVR: target/117726 - Better optimizations of ASHIFT:SI insns.Georg-Johann Lay1-0/+1
2024-11-20RISC-V: Add the mini support for SiFive extensions.yulong1-0/+6
2024-11-18AVR: target/84211 - Add a post reload register optimization pass.Georg-Johann Lay1-0/+2
2024-11-13RISC-V: Implement riscv_minimal_hwprobe_feature_bitsYangyu Chen2-0/+177
2024-11-11Initial Diamond Rapids SupportHaochen Jiang3-0/+20
2024-11-11i386: Add new model number for Arrow LakeHaochen Jiang1-0/+1
2024-11-01Support Intel AMX-MOVRSHu, Lin14-1/+22
2024-11-01Support Intel MOVRSHu, Lin14-0/+20
2024-11-01Support Intel AMX-FP8Liwei Xu4-1/+22
2024-11-01Support Intel AMX-TRANSPOSEHaochen Jiang4-1/+23
2024-11-01Support Intel AMX-TF32Haochen Jiang4-1/+22
2024-11-01Support Intel AMX-AVX512Haochen Jiang4-2/+36
2024-10-29[RISC-V] RISC-V: Add implication for M extension.Tsung Chun Lin1-0/+2
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