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2022-10-25Remove znver4 instruction reservationsTejas Joshi1-1/+1
This reverts the changes made to znver.md in: commit bf3b532b524ecacb3202ab2c8af419ffaaab7cff 2022-10-21 Tejas Joshi <TejasSanjay.Joshi@amd.com> gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_alias_table): Use CPU_ZNVER3 for znver4. * config/i386/znver.md: Remove znver4 reservations.
2022-10-25riscv: fix cross compilerMartin Liska1-4/+4
Move riscv_get_valid_option_values out of Fixes: riscv/riscv-common.cc:1748:40: error: ‘riscv_get_valid_option_values’ was not declared in this scope gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_get_valid_option_values): Get out of ifdef.
2022-10-25i386: fix pedantic warningMartin Liska1-1/+1
PR target/107364 gcc/ChangeLog: * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Fix pedantic warning.
2022-10-24x86: fix VENDOR_MAX enum valueMartin Liska1-1/+3
PR target/107364 gcc/ChangeLog: * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Reorder enum values as BUILTIN_VENDOR_MAX should not point in the middle of the valid enum values.
2022-10-24RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng1-0/+46
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_tunes): New. (riscv_get_valid_option_values): New. (TARGET_GET_VALID_OPTION_VALUES): New. * config/riscv/riscv-cores.def (RISCV_TUNE): New, define options for tune here. (RISCV_CORE): Fix comment. * config/riscv/riscv.cc (riscv_tune_info_table): Move definition to riscv-cores.def.
2022-10-21Enable AMD znver4 support and add instruction reservationsTejas Joshi3-28/+24
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4. * common/config/i386/i386-common.cc (processor_names): Add znver4. (processor_alias_table): Add znver4 and modularize old znvers. * common/config/i386/i386-cpuinfo.h (processor_subtypes): AMDFAM19H_ZNVER4. * config.gcc (x86_64-*-* |...): Likewise. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize znver4 cpus. * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4. * config/i386/i386-options.cc (m_ZNVER4): New definition. (m_ZNVER): Include m_ZNVER4. (processor_cost_table): Add znver4. * config/i386/i386.cc (ix86_reassociation_width): Likewise. * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4. (PTA_ZNVER1): New definition. (PTA_ZNVER2): Likewise. (PTA_ZNVER3): Likewise. (PTA_ZNVER4): Likewise. * config/i386/i386.md (define_attr "cpu"): Add znver4 and rename md file. * config/i386/x86-tune-costs.h (znver4_cost): New definition. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4. (ix86_adjust_cost): Likewise. * config/i386/znver1.md: Rename to znver.md. * config/i386/znver.md: Add new reservations for znver4. * doc/extend.texi: Add details about znver4. * doc/invoke.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv29.C: Likewise.
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling4-1/+26
gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint8. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint8. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT8. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint8. * config.gcc: Add avxvnniint8intrin.h. * config/i386/avxvnniint8intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT8): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT8__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8. (ix86_valid_target_attribute_inner_p): Handle avxvnniint8. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New.. * config/i386/i386.opt: Add option -mavxvnniint8. * config/i386/immintrin.h: Include avxvnniint8intrin.h. * config/i386/sse.md (UNSPEC_VPMADDUBSWACCD UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD, UNSPEC_VPMADDWDACCSSD): Rename according to new style. (vpdp<vpdotprodtype>_<mode>): New define_insn. * doc/extend.texi: Document avxvnniint8. * doc/invoke.texi: Document -mavxvnniint8. * doc/sourcebuild.texi: Document target avxvnniint8. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint8. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint8 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint8. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint8): New. * gcc.target/i386/avxvnniint8-1.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto. * gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-21Support Intel AVX-IFMAHongyu Wang4-1/+23
gcc/ * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, OPTION_MASK_ISA2_AVX2_UNSET): New macro. (ix86_handle_option): Handle -mavxifma. * common/config/i386/i386-cpuinfo.h (processor_types): Add FEATURE_AVXIFMA. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxifma. * common/config/i386/cpuinfo.h (get_available_features): Detect avxifma. * config.gcc: Add avxifmaintrin.h * config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change to macro. (_mm_madd52hi_epu64): Likewise. (_mm256_madd52lo_epu64): Likewise. (_mm256_madd52hi_epu64): Likewise. * config/i386/avxifmaintrin.h: New header. * config/i386/cpuid.h (bit_AVXIFMA): New. * config/i386/i386-builtin.def: Add new builtins, and correct pattern names for AVX512IFMA. * config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA builtins like AVX-VNNI. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXIFMA__. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Relax ISA masks for AVXIFMA. * config/i386/i386-isa.def: Add AVXIFMA. * config/i386/i386-options.cc (isa2_opts): Add -mavxifma. (ix86_valid_target_attribute_inner_p): Handle avxifma. * config/i386/i386.md (isa): Add attr avxifma and avxifmavl. * config/i386/i386.opt: Add option -mavxifma. * config/i386/immintrin.h: Inculde avxifmaintrin.h. * config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>): Remove. (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove. (vpamdd52huq<mode>_maskz): Rename to ... (vpmadd52huq<mode>_maskz): ... this. (vpamdd52luq<mode>_maskz): Rename to ... (vpmadd52luq<mode>_maskz): ... this. (vpmadd52<vpmadd52type><mode>): New define_insn. (vpmadd52<vpmadd52type>v8di): Likewise. (vpmadd52<vpmadd52type><mode>_maskz_1): Likewise. (vpamdd52<vpmadd52type><mode>_mask): Rename to ... (vpmadd52<vpmadd52type><mode>_mask): ... this. * doc/invoke.texi: Document -mavxifma. * doc/extend.texi: Document avxifma. * doc/sourcebuild.texi: Document target avxifma. gcc/testsuite/ * gcc.target/i386/avx-check.h: Add avxifma check. * gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane.. * gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this. * gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto. * gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test. * gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto. * gcc.target/i386/avx-ifma-1.c: Ditto. * gcc.target/i386/avx-ifma-2.c: Ditto. * gcc.target/i386/avx-ifma-3.c: Ditto. * gcc.target/i386/avx-ifma-4.c: Ditto. * gcc.target/i386/avx-ifma-5.c: Ditto. * gcc.target/i386/avx-ifma-6.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto. * gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto. * gcc.target/i386/sse-12.c: Add -mavxifma. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxifma): New.
2022-10-17Enable REE for H8Jeff Law1-0/+2
I was looking at H8 assembly code recently and noticed we had unnecessary extensions. As it turns out we never enabled redundant extension elimination on the H8. This patch fixes that oversight (and was the trigger for the failure fixed my the prior patch). gcc/common * common/config/h8300/h8300-common.cc (h8300_option_optimization_table): Enable redundant extension elimination at -O2 and above.
2022-10-17Initial Meteorlake SupportHu, Lin12-0/+6
gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Meteorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Meteorlake.
2022-10-17Initial Raptorlake SupportHaochen Jiang2-0/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h: (get_intel_cpu): Handle Raptorlake. * common/config/i386/i386-common.cc: (processor_alias_table): Add Raptorlake.
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu1-2/+0
gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove Rcq and Rcw options. * config/arc/arc.opt (mRcq): Ignore option, preserve it for backwards compatibility. (mRcw): Likewise. * doc/invoke.texi (mRcw, mRcq): Update document. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2022-09-29aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford1-0/+12
-mgeneral-regs-only is effectively "+nofp for the compiler without changing the assembler's ISA flags". Currently that's implemented by making TARGET_FLOAT, TARGET_SIMD and TARGET_SVE depend on !TARGET_GENERAL_REGS_ONLY and then making any feature that needs FP registers depend (directly or indirectly) on one of those three TARGET macros. The problem is that it's easy to forgot to do the last bit. This patch instead represents the distinction between "assemnbler ISA flags" and "compiler ISA flags" more directly, funnelling all updates through a new function that sets both sets of flags together. gcc/ * config/aarch64/aarch64.opt (aarch64_asm_isa_flags): New variable. * config/aarch64/aarch64.h (aarch64_asm_isa_flags) (aarch64_isa_flags): Redefine as read-only macros. (TARGET_SIMD, TARGET_FLOAT, TARGET_SVE): Don't depend on !TARGET_GENERAL_REGS_ONLY. * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): New function. (aarch64_handle_option): Call it when updating -mgeneral-regs. * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): Replace m_old_isa_flags with m_old_asm_isa_flags. (aarch64_set_asm_isa_flags): Declare. * config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher) (aarch64_simd_switcher::~aarch64_simd_switcher): Save and restore aarch64_asm_isa_flags instead of aarch64_isa_flags. * config/aarch64/aarch64-sve-builtins.cc (check_required_extensions): Use aarch64_asm_isa_flags instead of aarch64_isa_flags. * config/aarch64/aarch64.cc (aarch64_set_asm_isa_flags): New function. (aarch64_override_options, aarch64_handle_attr_arch) (aarch64_handle_attr_cpu, aarch64_handle_attr_isa_flags): Use aarch64_set_asm_isa_flags to set the ISA flags. (aarch64_option_print, aarch64_declare_function_name) (aarch64_start_file): Use aarch64_asm_isa_flags instead of aarch64_isa_flags. (aarch64_can_inline_p): Check aarch64_asm_isa_flags as well as aarch64_isa_flags.
2022-09-29aarch64: Tweak contents of flags_on/off fieldsRichard Sandiford1-8/+6
After previous changes, it's more convenient if the flags_on and flags_off fields of all_extensions include the feature flag itself. gcc/ * common/config/aarch64/aarch64-common.cc (all_extensions): Include the feature flag in flags_on and flags_off. (aarch64_parse_extension): Update accordingly. (aarch64_get_extension_string_for_isa_flags): Likewise.
2022-09-29aarch64: Make more use of aarch64_feature_flagsRichard Sandiford1-9/+10
A previous patch added a aarch64_feature_flags typedef, to abstract the representation of the feature flags. This patch makes existing code use the typedef too. Hope I've caught them all! gcc/ * common/config/aarch64/aarch64-common.cc: Use aarch64_feature_flags for feature flags throughout. * config/aarch64/aarch64-protos.h: Likewise. * config/aarch64/aarch64-sve-builtins.h: Likewise. * config/aarch64/aarch64-sve-builtins.cc: Likewise. * config/aarch64/aarch64.cc: Likewise. * config/aarch64/aarch64.opt: Likewise. * config/aarch64/driver-aarch64.cc: Likewise.
2022-09-29aarch64: Tweak constness of option-related dataRichard Sandiford1-13/+13
Some of the option structures have all-const member variables. That doesn't seem necessary: we can just use const on the objects that are supposed to be read-only. Also, with the new, more C++-heavy option handling, it seems better to use constexpr for the static data, to make sure that we're not adding unexpected overhead. gcc/ * common/config/aarch64/aarch64-common.cc (aarch64_option_extension) (processor_name_to_arch, arch_to_arch_name): Remove const from member variables. (all_extensions, all_cores, all_architectures): Make a constexpr. * config/aarch64/aarch64.cc (processor): Remove const from member variables. (all_architectures): Make a constexpr. * config/aarch64/driver-aarch64.cc (aarch64_core_data) (aarch64_arch_driver_info): Remove const from member variables. (aarch64_cpu_data, aarch64_arches): Make a constexpr. (get_arch_from_id): Return a pointer to const. (host_detect_local_cpu): Update accordingly.
2022-09-29aarch64: Avoid std::string in static dataRichard Sandiford1-2/+2
Just a minor patch to avoid having to construct std::strings in static data. gcc/ * common/config/aarch64/aarch64-common.cc (processor_name_to_arch) (arch_to_arch_name): Use const char * instead of std::string.
2022-09-29aarch64: Simplify generation of .arch stringsRichard Sandiford1-196/+47
aarch64-common.cc has two arrays, one maintaining the original definition order and one sorted by population count. Sorting by population count was a way of ensuring topological ordering, taking advantage of the fact that the entries are partially ordered by the subset relation. However, the sorting is not needed now that the .def file is forced to have topological order from the outset. Other changes are: (1) The population count used: uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on; uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on; int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a); int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b); where I think the & was supposed to be |. This meant that the counts would always be 1 in practice, since flag_canonical is a single bit. This led us to printing +nofp+nosimd even though GCC "knows" (and GAS agrees) that +nofp disables simd. (2) The .arch output code converts +aes+sha2 to +crypto. I think the main reason for doing this is to support assemblers that predate the individual per-feature crypto flags. It therefore seems more natural to treat it as a special case, rather than as an instance of a general pattern. Hopefully we won't do something similar in future! (There is already special handling of CRC, for different reasons.) (3) Previously, if the /proc/cpuinfo code saw a feature like sve, it would assume the presence of all the features that sve depends on. It would be possible to keep that behaviour if necessary, but it was simpler to assume the presence of fp16 (say) only when fphp is present. There's an argument that that's more conservatively correct too. gcc/ * common/config/aarch64/aarch64-common.cc (TARGET_OPTION_INIT_STRUCT): Delete. (aarch64_option_extension): Remove is_synthetic_flag. (all_extensions): Update accordingly. (all_extensions_by_on, opt_ext, opt_ext_cmp): Delete. (aarch64_option_init_struct, aarch64_contains_opt): Delete. (aarch64_get_extension_string_for_isa_flags): Rewrite to use all_extensions instead of all_extensions_on. gcc/testsuite/ * gcc.target/aarch64/cpunative/info_8: Add all dependencies of sve. * gcc.target/aarch64/cpunative/info_9: Likewise svesm4. * gcc.target/aarch64/cpunative/info_15: Likewise. * gcc.target/aarch64/cpunative/info_16: Likewise sve2. * gcc.target/aarch64/cpunative/info_17: Likewise. * gcc.target/aarch64/cpunative/native_cpu_2.c: Expect just +nofp rather than +nofp+nosimd. * gcc.target/aarch64/cpunative/native_cpu_10.c: Likewise. * gcc.target/aarch64/target_attr_15.c: Likewise.
2022-09-29aarch64: Simplify feature definitionsRichard Sandiford1-11/+18
Currently the aarch64-option-extensions.def entries, the aarch64-cores.def entries, and the AARCH64_FL_FOR_* macros have a transitive closure of dependencies that is maintained by hand. This is a bit error-prone and is becoming less tenable as more features are added. The main point of this patch is to maintain the closure automatically instead. For example, the +sve2-aes extension requires sve2 and aes. This is now described using: AARCH64_OPT_EXTENSION("sve2-aes", SVE2_AES, (SVE2, AES), ...) If life was simple, we could just give the name of the feature and the list of features that it requires/depends on. But sadly things are more complicated. For example: - the legacy +crypto option enables aes and sha2 only, but +nocrypto disables all crypto-related extensions, including sm4. - +fp16fml enables fp16, but armv8.4-a enables fp16fml without fp16. fp16fml only has an effect when fp16 is also present; see the comments for more details. - +bf16 enables simd, but +bf16+nosimd is valid and enables just the scalar bf16 instructions. rdma behaves similarly. To handle cases like these, the option entries have extra fields to specify what an explicit +foo enables and what an explicit +nofoo disables, in addition to the absolute dependencies. The other main changes are: - AARCH64_FL_* are now defined automatically. - the feature list for each architecture level moves from aarch64.h to aarch64-arches.def. As a consequence, we now have a (redundant) V8A feature flag. While there, the patch uses a new typedef, aarch64_feature_flags, for the set of feature flags. This should make it easier to switch to a class if we run out of bits in the uint64_t. For now the patch hardcodes the fact that crypto is the only synthetic option. A later patch will remove this field. To test for things that might not be covered by the testsuite, I made the driver print out the all_extensions, all_cores and all_archs arrays before and after the patch, with the following tweaks: - renumber the old AARCH64_FL_* bit assignments to match the .def order - remove the new V8A flag when printing the new tables - treat CRYPTO and CRYPTO | AES | SHA2 the same way when printing the core tables (On the last point: some cores enabled just CRYPTO while others enabled CRYPTO, AES and SHA2. This doesn't cause a difference in behaviour because of how the dependent macros are defined. With the new scheme, all entries with CRYPTO automatically get AES and SHA2 too.) The only difference is that +nofp now turns off dotprod. This was another instance of an incomplete transitive closure, but unlike the instances fixed in a previous patch, it had no observable effect. gcc/ * config/aarch64/aarch64-option-extensions.def: Switch to a new format. * config/aarch64/aarch64-cores.def: Use the same format to specify lists of features. * config/aarch64/aarch64-arches.def: Likewise, moving that information from aarch64.h. * config/aarch64/aarch64-opts.h (aarch64_feature_flags): New typedef. * config/aarch64/aarch64.h (aarch64_feature): New class enum. Turn AARCH64_FL_* macros into constexprs, getting the definitions from aarch64-option-extensions.def. Remove AARCH64_FL_FOR_* macros. * common/config/aarch64/aarch64-common.cc: Include aarch64-feature-deps.h. (all_extensions): Update for new .def format. (all_extensions_by_on, all_cores, all_architectures): Likewise. * config/aarch64/driver-aarch64.cc: Include aarch64-feature-deps.h. (aarch64_extensions): Update for new .def format. (aarch64_cpu_data, aarch64_arches): Likewise. * config/aarch64/aarch64.cc: Include aarch64-feature-deps.h. (all_architectures, all_cores): Update for new .def format. * config/aarch64/aarch64-sve-builtins.cc (check_required_extensions): Likewise.
2022-09-29aarch64: Avoid redundancy in aarch64-cores.defRichard Sandiford1-1/+1
The flags fields of the aarch64-cores.def always start with AARCH64_FL_FOR_<ARCH>. After previous changes, <ARCH> is always identical to the previous field, so we can drop the explicit AARCH64_FL_FOR_<ARCH> and derive it programmatically. This isn't a big saving in itself, but it helps with later patches. gcc/ * config/aarch64/aarch64-cores.def: Remove AARCH64_FL_FOR_<ARCH> from the flags field. * common/config/aarch64/aarch64-common.cc (all_cores): Add it here instead. * config/aarch64/aarch64.cc (all_cores): Likewise. * config/aarch64/driver-aarch64.cc (all_cores): Likewise.
2022-09-29aarch64: Add "V" to aarch64-arches.def namesRichard Sandiford1-1/+1
This patch completes the renaming of architecture-level related things by adding "V" to the name of the architecture in aarch64-arches.def. Since the "V" is predictable, we can easily drop it when we don't need it (as when matching /proc/cpuinfo). Having a valid C identifier is necessary for later patches. gcc/ * config/aarch64/aarch64-arches.def: Add a leading "V" to the ARCH_IDENT fields. * config/aarch64/aarch64-cores.def: Update accordingly. * common/config/aarch64/aarch64-common.cc (all_cores): Likewise. * config/aarch64/aarch64.cc (all_cores): Likewise. * config/aarch64/driver-aarch64.cc (aarch64_arches): Skip the leading "V".
2022-09-29aarch64: Rename AARCH64_FL_FOR_ARCH macrosRichard Sandiford1-1/+1
This patch renames AARCH64_FL_FOR_ARCH* macros to follow the same V<number><profile> names that we (now) use elsewhere. The names are only temporary -- a later patch will move the information to the .def file instead. However, it helps with the sequencing to do this first. gcc/ * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8): Rename to... (AARCH64_FL_FOR_V8A): ...this. (AARCH64_FL_FOR_ARCH8_1): Rename to... (AARCH64_FL_FOR_V8_1A): ...this. (AARCH64_FL_FOR_ARCH8_2): Rename to... (AARCH64_FL_FOR_V8_2A): ...this. (AARCH64_FL_FOR_ARCH8_3): Rename to... (AARCH64_FL_FOR_V8_3A): ...this. (AARCH64_FL_FOR_ARCH8_4): Rename to... (AARCH64_FL_FOR_V8_4A): ...this. (AARCH64_FL_FOR_ARCH8_5): Rename to... (AARCH64_FL_FOR_V8_5A): ...this. (AARCH64_FL_FOR_ARCH8_6): Rename to... (AARCH64_FL_FOR_V8_6A): ...this. (AARCH64_FL_FOR_ARCH8_7): Rename to... (AARCH64_FL_FOR_V8_7A): ...this. (AARCH64_FL_FOR_ARCH8_8): Rename to... (AARCH64_FL_FOR_V8_8A): ...this. (AARCH64_FL_FOR_ARCH8_R): Rename to... (AARCH64_FL_FOR_V8R): ...this. (AARCH64_FL_FOR_ARCH9): Rename to... (AARCH64_FL_FOR_V9A): ...this. (AARCH64_FL_FOR_ARCH9_1): Rename to... (AARCH64_FL_FOR_V9_1A): ...this. (AARCH64_FL_FOR_ARCH9_2): Rename to... (AARCH64_FL_FOR_V9_2A): ...this. (AARCH64_FL_FOR_ARCH9_3): Rename to... (AARCH64_FL_FOR_V9_3A): ...this. * common/config/aarch64/aarch64-common.cc (all_cores): Update accordingly. * config/aarch64/aarch64-arches.def: Likewise. * config/aarch64/aarch64-cores.def: Likewise. * config/aarch64/aarch64.cc (all_cores): Likewise.
2022-09-29aarch64: Rename AARCH64_ISA architecture-level macrosRichard Sandiford1-1/+1
All AARCH64_ISA_* architecture-level macros except AARCH64_ISA_V8_R are for the A profile: they cause __ARM_ARCH_PROFILE to be set to 'A' and they are associated with architecture names like armv8.4-a. It's convenient for later patches if we make this explicit by adding an "A" to the name. Also, rather than add an underscore (as for V8_R) it's more convenient to add the profile directly to the number, like we already do in the ARCH_IDENT field of the aarch64-arches.def entries. gcc/ * config/aarch64/aarch64.h (AARCH64_ISA_V8_2, AARCH64_ISA_V8_3) (AARCH64_ISA_V8_4, AARCH64_ISA_V8_5, AARCH64_ISA_V8_6) (AARCH64_ISA_V9, AARCH64_ISA_V9_1, AARCH64_ISA_V9_2) (AARCH64_ISA_V9_3): Add "A" to the end of the name. (AARCH64_ISA_V8_R): Rename to AARCH64_ISA_V8R. (TARGET_ARMV8_3, TARGET_JSCVT, TARGET_FRINT, TARGET_MEMTAG): Update accordingly. * common/config/aarch64/aarch64-common.cc (aarch64_get_extension_string_for_isa_flags): Likewise. * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros): Likewise.
2022-09-23RISC-V: Support poly move manipulation and selftests.zhongjuzhe1-1/+1
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Change "static void" to "void". * config.gcc: Add riscv-selftests.o * config/riscv/predicates.md: Allow const_poly_int. * config/riscv/riscv-protos.h (riscv_reinit): New function. (riscv_parse_arch_string): change as exten function. (riscv_run_selftests): New function. * config/riscv/riscv.cc (riscv_cannot_force_const_mem): Don't allow poly into const pool. (riscv_report_v_required): New function. (riscv_expand_op): New function. (riscv_expand_mult_with_const_int): New function. (riscv_legitimize_poly_move): Ditto. (riscv_legitimize_move): New function. (riscv_hard_regno_mode_ok): Add VL/VTYPE register allocation and fix vector RA. (riscv_convert_vector_bits): Fix riscv_vector_chunks configuration for -marh no 'v'. (riscv_reinit): New function. (TARGET_RUN_TARGET_SELFTESTS): New target hook support. * config/riscv/t-riscv: Add riscv-selftests.o. * config/riscv/riscv-selftests.cc: New file. gcc/testsuite/ChangeLog: * selftests/riscv/empty-func.rtl: New test.
2022-09-09RISC-V: Suppress build warningsKito Cheng1-18/+18
../../gcc/common/config/riscv/riscv-common.cc: In function 'const char* riscv_multi_lib_check(int, const char**)': ../../gcc/common/config/riscv/riscv-common.cc:1451:11: error: bare apostrophe ''' in format [-Werror=format-diag] 1451 | "Can't find suitable multilib set for %<-march=%s%>/%<-mabi=%s%>", | ^ ../../gcc/common/config/riscv/riscv-common.cc:1451:7: note: if avoiding the apostrophe is not feasible, enclose it in a pair of '%<' and '%>' directives instead 1451 | "Can't find suitable multilib set for %<-march=%s%>/%<-mabi=%s%>", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../../gcc/common/config/riscv/riscv-common.cc: At global scope: ../../gcc/common/config/riscv/riscv-common.cc:1492:1: error: 'int riscv_check_conds(const switchstr*, int, int, const std::vector<std::__cxx11::basic_string<char> >&)' defined but not used [-Werror=unused-function] 1492 | riscv_check_conds ( | ^~~~~~~~~~~~~~~~~ ../../gcc/common/config/riscv/riscv-common.cc:1374:1: error: 'const char* find_last_appear_switch(const switchstr*, int, const char*)' defined but not used [-Werror=unused-function] 1374 | find_last_appear_switch ( | ^~~~~~~~~~~~~~~~~~~~~~~ cc1plus: all warnings being treated as errors make[3]: *** [Makefile:2442: riscv-common.o] Error 1 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (RISCV_USE_CUSTOMISED_MULTI_LIB): Move forward for cover all all necessary functions for suppress unused function warnings. (riscv_multi_lib_check): Move forward, and tweak message to suppress -Werror=format-diag warning.
2022-09-05RISC-V: Support Zmmul extensionLiaoShihua1-0/+4
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zmmul. * config/riscv/riscv-opts.h (MASK_ZMMUL): New. (TARGET_ZMMUL): Ditto. * config/riscv/riscv.cc (riscv_option_override):Ditto. * config/riscv/riscv.md: Add Zmmul * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/zmmul-1.c: New test. * gcc.target/riscv/zmmul-2.c: New test.
2022-09-02RISC-V: Implement TARGET_COMPUTE_MULTILIBKito Cheng1-0/+377
Use TARGET_COMPUTE_MULTILIB to search the multi-lib reuse for riscv*-*-elf*, according following rules: 1. Check ABI is same. 2. Check both has atomic extension or both don't have atomic extension. - Because mix soft and hard atomic operation doesn't make sense and won't work as expect. 3. Check current arch is superset of the target multi-lib arch. - It might result slower performance or larger code size, but it safe to run. 4. Pick most match multi-lib set if more than one multi-lib are pass the above checking. Example for how to select multi-lib: We build code with -march=rv32imaf and -mabi=ilp32, and we have following 5 multi-lib set: 1. rv32ia/ilp32 2. rv32ima/ilp32 3. rv32imf/ilp32 4. rv32imaf/ilp32f 5. rv32imafd/ilp32 The first and second multi-lib is safe to like, 3rd multi-lib can't re-use becasue it don't have atomic extension, which is mismatch according rule 2, and the 4th multi-lib can't re-use too due to the ABI mismatch, the last multi-lib can't use since current arch is not superset of the arch of multi-lib. And emit error if not found suitable multi-lib set, the error message only emit when link with standard libraries. Example for when error will be emitted: $ riscv64-unknown-elf-gcc -print-multi-lib .; rv32i/ilp32;@march=rv32i@mabi=ilp32 rv32im/ilp32;@march=rv32im@mabi=ilp32 rv32iac/ilp32;@march=rv32iac@mabi=ilp32 rv32imac/ilp32;@march=rv32imac@mabi=ilp32 rv32imafc/ilp32f;@march=rv32imafc@mabi=ilp32f rv64imac/lp64;@march=rv64imac@mabi=lp64 // No actual linking, so no error emitted. $ riscv64-unknown-elf-gcc -print-multi-directory -march=rv32ia -mabi=ilp32 . // Link to default libc and libgcc, so check the multi-lib, and emit // error because not found suitable multilib. $ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c riscv64-unknown-elf-gcc: fatal error: can't found suitable multilib set for '-march=rv32ia'/'-mabi=ilp32' compilation terminated. // No error emitted, because not link to stdlib. $ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c -nostdlib // No error emitted, because compile only. $ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c -c gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Include <vector>. (struct riscv_multi_lib_info_t): New. (riscv_subset_list::match_score): Ditto. (find_last_appear_switch): Ditto. (prefixed_with): Ditto. (struct multi_lib_info_t): Ditto. (riscv_current_arch_str): Ditto. (riscv_current_abi_str): Ditto. (riscv_multi_lib_info_t::parse): Ditto. (riscv_check_cond): Ditto. (riscv_check_conds): Ditto. (riscv_compute_multilib): Ditto. (TARGET_COMPUTE_MULTILIB): Defined. * config/riscv/elf.h (LIB_SPEC): Call riscv_multi_lib_check if doing link. (RISCV_USE_CUSTOMISED_MULTI_LIB): New. * config/riscv/riscv.h (riscv_multi_lib_check): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_multi_lib_check. * config/riscv/riscv-subset.h (riscv_subset_list::match_score): New.
2022-09-02Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.Kito Cheng3-0/+51
Create a new hook to let target could override the multi-lib result, the motivation is RISC-V might have very complicated multi-lib re-use rule*, which is hard to maintain and use current multi-lib scripts, we even hit the "argument list too long" error when we tried to add more multi-lib reuse rule. So I think it would be great to have a target specific way to determine the multi-lib re-use rule, then we could write those rule in C, instead of expand every possible case in MULTILIB_REUSE. * Here is an example for RISC-V multi-lib rules: https://gist.github.com/kito-cheng/0289cd42d9a756382e5afeb77b42b73b gcc/ChangeLog: * common/common-target.def (compute_multilib): New. * common/common-targhooks.h (default_compute_multilib): New. * common/common-targhooks.cc (default_compute_multilib): New. * doc/tm.texi.in (TARGET_COMPUTE_MULTILIB): New. * doc/tm.texi: Regen. * gcc.cc: Include common/common-target.h. (set_multilib_dir) Call targetm_common.compute_multilib. (SWITCH_LIVE): Move to opts.h. (SWITCH_FALSE): Ditto. (SWITCH_IGNORE): Ditto. (SWITCH_IGNORE_PERMANENTLY): Ditto. (SWITCH_KEEP_FOR_GCC): Ditto. (struct switchstr): Ditto. * opts.h (SWITCH_LIVE): Move from gcc.c. (SWITCH_FALSE): Ditto. (SWITCH_IGNORE): Ditto. (SWITCH_IGNORE_PERMANENTLY): Ditto. (SWITCH_KEEP_FOR_GCC): Ditto. (struct switchstr): Ditto.
2022-08-29s390: Add -munroll-only-small-loops.Robin Dapp1-0/+5
Inspired by Power we also introduce -munroll-only-small-loops. This implies activating -funroll-loops and -munroll-only-small-loops at -O2 and above. gcc/ChangeLog: * common/config/s390/s390-common.cc: Enable -funroll-loops and -munroll-only-small-loops for OPT_LEVELS_2_PLUS_SPEED_ONLY. * config/s390/s390.cc (s390_loop_unroll_adjust): Do not unroll loops larger than 12 instructions. (s390_override_options_after_change): Set unroll options. (s390_option_override_internal): Likewise. * config/s390/s390.opt: Document munroll-only-small-loops. gcc/testsuite/ChangeLog: * gcc.target/s390/vector/vec-copysign.c: Do not unroll. * gcc.target/s390/zvector/autovec-double-quiet-uneq.c: Dito. * gcc.target/s390/zvector/autovec-double-signaling-ltgt.c: Dito. * gcc.target/s390/zvector/autovec-float-quiet-uneq.c: Dito. * gcc.target/s390/zvector/autovec-float-signaling-ltgt.c: Dito.
2022-08-26cr16: remove obsoleted portMartin Liska1-27/+0
contrib/ChangeLog: * config-list.mk: Remove cr16. gcc/ChangeLog: * doc/extend.texi: Remove cr16 related stuff. * doc/install.texi: Likewise. * doc/invoke.texi: Likewise. * doc/md.texi: Likewise. * function-tests.cc (test_expansion_to_rtl): Likewise. * common/config/cr16/cr16-common.cc: Removed. * config/cr16/constraints.md: Removed. * config/cr16/cr16-protos.h: Removed. * config/cr16/cr16.cc: Removed. * config/cr16/cr16.h: Removed. * config/cr16/cr16.md: Removed. * config/cr16/cr16.opt: Removed. * config/cr16/predicates.md: Removed. * config/cr16/t-cr16: Removed. libgcc/ChangeLog: * config.host: Remove cr16 related stuff. * config/cr16/crti.S: Removed. * config/cr16/crtlibid.S: Removed. * config/cr16/crtn.S: Removed. * config/cr16/divmodhi3.c: Removed. * config/cr16/lib1funcs.S: Removed. * config/cr16/t-cr16: Removed. * config/cr16/t-crtlibid: Removed. * config/cr16/unwind-cr16.c: Removed. * config/cr16/unwind-dw2.h: Removed. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Remove cr16 related stuff.
2022-08-16RISC-V: Support zfh and zfhmin extensionKito Cheng1-0/+8
Zfh and Zfhmin are extensions for IEEE half precision, both are ratified in Jan. 2022[1]: - Zfh has full set of operation like F or D for single or double precision. - Zfhmin has only provide minimal support for half precision operation, like conversion, load, store and move instructions. [1] https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add zfh and zfhmin. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZFHMIN): New. (MASK_ZFH): Ditto. (TARGET_ZFHMIN): Ditto. (TARGET_ZFH): Ditto. * config/riscv/riscv.cc (riscv_output_move): Handle HFmode move for zfh and zfhmin. (riscv_emit_float_compare): Handle HFmode. * config/riscv/riscv.md (ANYF): Add HF. (SOFTF): Add HF. (load): Ditto. (store): Ditto. (truncsfhf2): New. (truncdfhf2): Ditto. (extendhfsf2): Ditto. (extendhfdf2): Ditto. (*movhf_hardfloat): Ditto. (*movhf_softfloat): Make sure not ZFHMIN. * config/riscv/riscv.opt (riscv_zf_subext): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/_Float16-zfh-1.c: New. * gcc.target/riscv/_Float16-zfh-2.c: Ditto. * gcc.target/riscv/_Float16-zfh-3.c: Ditto. * gcc.target/riscv/_Float16-zfhmin-1.c: Ditto. * gcc.target/riscv/_Float16-zfhmin-2.c: Ditto. * gcc.target/riscv/_Float16-zfhmin-3.c: Ditto. * gcc.target/riscv/arch-16.c: Ditto. * gcc.target/riscv/arch-17.c: Ditto. * gcc.target/riscv/predef-21.c: Ditto. * gcc.target/riscv/predef-22.c: Ditto.
2022-08-15xtensa: Turn on -fsplit-wide-types-early by defaultTakayuki 'January June' Suwa1-0/+2
Since GCC10, the "subreg2" optimization pass was no longer tied to enabling "subreg1" unless -fsplit-wide-types-early was turned on (PR88233). However on the Xtensa port, the lack of "subreg2" can degrade the quality of the output code, especially for those that produce many D[FC]mode pseudos. This patch turns on -fsplit-wide-types-early by default in order to restore the previous behavior. gcc/ChangeLog: * common/config/xtensa/xtensa-common.cc (xtensa_option_optimization_table): Add OPT_fsplit_wide_types_early for OPT_LEVELS_ALL in order to restore pre-GCC10 behavior.
2022-07-26LoongArch: Support split symbol.Lulu Cheng1-0/+1
Add compilation option '-mexplicit-relocs', and if enable '-mexplicit-relocs' the symbolic address load instruction 'la.*' will be split into two instructions. This compilation option enabled by default. gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-fsection-anchors' when O1 and more advanced optimization. * config/loongarch/genopts/loongarch.opt.in: Add new option '-mexplicit-relocs', and enable by default. * config/loongarch/loongarch-protos.h (loongarch_split_move_insn_p): Delete function declaration. (loongarch_split_move_insn): Delete function declaration. (loongarch_split_symbol_type): Add function declaration. * config/loongarch/loongarch.cc (enum loongarch_address_type): Add new address type 'ADDRESS_LO_SUM'. (loongarch_classify_symbolic_expression): New function definitions. Classify the base of symbolic expression X, given that X appears in context CONTEXT. (loongarch_symbol_insns): Add a judgment condition TARGET_EXPLICIT_RELOCS. (loongarch_split_symbol_type): New function definitions. Determines whether the symbol load should be split into two instructions. (loongarch_valid_lo_sum_p): New function definitions. Return true if a LO_SUM can address a value of mode MODE when the LO_SUM symbol has type SYMBOL_TYPE. (loongarch_classify_address): Add handling of 'LO_SUM'. (loongarch_address_insns): Add handling of 'ADDRESS_LO_SUM'. (loongarch_signed_immediate_p): Sort code. (loongarch_12bit_offset_address_p): Return true if address type is ADDRESS_LO_SUM. (loongarch_const_insns): Add handling of 'HIGH'. (loongarch_split_move_insn_p): Add the static attribute to the function. (loongarch_emit_set): New function definitions. (loongarch_call_tls_get_addr): Add symbol handling when defining TARGET_EXPLICIT_RELOCS. (loongarch_legitimize_tls_address): Add symbol handling when defining the TARGET_EXPLICIT_RELOCS macro. (loongarch_split_symbol): New function definitions. Split symbol. (loongarch_legitimize_address): Add codes see if the address can split into a high part and a LO_SUM. (loongarch_legitimize_const_move): Add codes split moves of symbolic constants into high and low. (loongarch_split_move_insn): Delete function definitions. (loongarch_output_move): Add support for HIGH and LO_SUM. (loongarch_print_operand_reloc): New function definitions. Print symbolic operand OP, which is part of a HIGH or LO_SUM in context CONTEXT. (loongarch_memmodel_needs_release_fence): Sort code. (loongarch_print_operand): Rearrange alphabetical order and add H and L to support HIGH and LOW output. (loongarch_print_operand_address): Add handling of 'ADDRESS_LO_SUM'. (TARGET_MIN_ANCHOR_OFFSET): Define macro to -IMM_REACH/2. (TARGET_MAX_ANCHOR_OFFSET): Define macro to IMM_REACH/2-1. * config/loongarch/loongarch.md (movti): Delete the template. (*movti): Delete the template. (movtf): Delete the template. (*movtf): Delete the template. (*low<mode>): New template of normal symbol low address. (@tls_low<mode>): New template of tls symbol low address. (@ld_from_got<mode>): New template load address from got table. (@ori_l_lo12<mode>): New template. * config/loongarch/loongarch.opt: Update from loongarch.opt.in. * config/loongarch/predicates.md: Add support for symbol_type HIGH. gcc/testsuite/ChangeLog: * gcc.target/loongarch/func-call-1.c: Add build option '-mno-explicit-relocs'. * gcc.target/loongarch/func-call-2.c: Add build option '-mno-explicit-relocs'. * gcc.target/loongarch/func-call-3.c: Add build option '-mno-explicit-relocs'. * gcc.target/loongarch/func-call-4.c: Add build option '-mno-explicit-relocs'. * gcc.target/loongarch/func-call-5.c: New test. * gcc.target/loongarch/func-call-6.c: New test. * gcc.target/loongarch/func-call-7.c: New test. * gcc.target/loongarch/func-call-8.c: New test. * gcc.target/loongarch/relocs-symbol-noaddend.c: New test.
2022-07-03loongarch: use -mno-check-zero-division as the default for optimized codeXi Ruoyao1-3/+0
Integer division by zero is undefined behavior anyway, and there are already many platforms where neither the GCC port and the hardware do anything to trap on division by zero. So any portable program shall not rely on SIGFPE on division by zero, in both theory and practice. As the result, there is no real reason to cost two additional instructions just for the trap on division by zero with a new ISA. One remaining reason to trap on division by zero may be debugging, especially while -fsanitize=integer-divide-by-zero is not implemented for LoongArch yet. To make debugging easier, keep -mcheck-zero-division as the default for -O0 and -Og, but use -mno-check-zero-division as the default for all other optimization levels. Co-authored-by: Lulu Cheng <chenglulu@loongson.cn> gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_check_zero_div_p): New static function. (loongarch_idiv_insns): Use loongarch_check_zero_div_p instead of TARGET_CHECK_ZERO_DIV. (loongarch_output_division): Likewise. * common/config/loongarch/loongarch-common.cc (TARGET_DEFAULT_TARGET_FLAGS): Remove unneeded hook. * doc/invoke.texi: Update to match the new behavior. gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20101011-1.c (dg-additional-options): add -mcheck-zero-division for LoongArch targets.
2022-07-01i386: Add AVX512BW to AVX512F in MASK_ISA2Haochen Jiang1-3/+2
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA2_AVX512BW_UNSET, remove OPTION_MASK_ISA2_AVX512BF16_UNSET and OPTION_MASK_ISA2_AVX512FP16_UNSET.
2022-06-25Remove long deprecated tilegx and tilepro portsJeff Law2-112/+0
/ * MAINTAINERS: Remove tilegx and tilepro entries. * configure.ac: Remove tilegx and tilepro stanzas. * configure: Rebuilt. contrib/ * config-list.mk: Remove tilegx and tilepro entries. * gcc_update: Remove tilegx and tilepro entries. gcc/ * common/config/tilegx/tilegx-common.cc: Removed. * common/config/tilepro/tilepro-common.cc: Removed. * config.gcc: Remove tilegx and tilepro entries. * config/tilegx/constraints.md: Removed. * config/tilegx/feedback.h: Removed. * config/tilegx/linux.h: Removed. * config/tilegx/mul-tables.cc: Removed. * config/tilegx/predicates.md: Removed. * config/tilegx/sync.md: Removed. * config/tilegx/t-tilegx: Removed. * config/tilegx/tilegx-builtins.h: Removed. * config/tilegx/tilegx-c.cc: Removed. * config/tilegx/tilegx-generic.md: Removed. * config/tilegx/tilegx-modes.def: Removed. * config/tilegx/tilegx-multiply.h: Removed. * config/tilegx/tilegx-opts.h: Removed. * config/tilegx/tilegx-protos.h: Removed. * config/tilegx/tilegx.cc: Removed. * config/tilegx/tilegx.h: Removed. * config/tilegx/tilegx.md: Removed. * config/tilegx/tilegx.opt: Removed. * config/tilepro/constraints.md: Removed. * config/tilepro/feedback.h: Removed. * config/tilepro/gen-mul-tables.cc: Removed. * config/tilepro/linux.h: Removed. * config/tilepro/mul-tables.cc: Removed. * config/tilepro/predicates.md: Removed. * config/tilepro/t-tilepro: Removed. * config/tilepro/tilepro-builtins.h: Removed. * config/tilepro/tilepro-c.cc: Removed. * config/tilepro/tilepro-generic.md: Removed. * config/tilepro/tilepro-modes.def: Removed. * config/tilepro/tilepro-multiply.h: Removed. * config/tilepro/tilepro-protos.h: Removed. * config/tilepro/tilepro.cc: Removed. * config/tilepro/tilepro.h: Removed. * config/tilepro/tilepro.md: Removed. * config/tilepro/tilepro.opt: Removed. * configure.ac: Remove tilegx and tilepro entries. * configure: Rebuilt. * doc/extend.texi: Remove tilegx and tilepro entries. * doc/install.texi: Remove tilegx and tilepro entries. * doc/invoke.texi: Remove tilegx and tilepro entries. * doc/md.texi: Remove tilegx and tilepro entries. gcc/testsuite/ * gcc.dg/lower-subreg-1.c: Remove tilegx and tilepro entries. * gcc.misc-tests/linkage.exp: Remove tilegx and tilepro entries. libgcc/ * config.host: Removed tilegx and tilepro entries. * config/tilegx/sfp-machine.h: Removed. * config/tilegx/sfp-machine32.h: Removed. * config/tilegx/sfp-machine64.h: Removed. * config/tilegx/t-crtstuff: Removed. * config/tilegx/t-softfp: Removed. * config/tilegx/t-tilegx: Removed. * config/tilepro/atomic.c: Removed. * config/tilepro/atomic.h: Removed. * config/tilepro/linux-unwind.h: Removed. * config/tilepro/sfp-machine.h: Removed. * config/tilepro/softdivide.c: Removed. * config/tilepro/softmpy.S: Removed. * config/tilepro/t-crtstuff: Removed. * config/tilepro/t-tilepro: Removed.
2022-06-13x86: Require AVX for F16C and VAESH.J. Lu1-4/+4
Since F16C and VAES are only usable with AVX, require AVX for F16C and VAES. libgcc/105920 * common/config/i386/cpuinfo.h (get_available_features): Require AVX for F16C and VAES.
2022-05-24RISC-V: Add mininal support for Zicbo[mzp]ShiYulong1-0/+8
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. (MASK_ZICBOM): New. (MASK_ZICBOP): New. (TARGET_ZICBOZ): New. (TARGET_ZICBOM): New. (TARGET_ZICBOP): New. * config/riscv/riscv.opt (riscv_zicmo_subext): New.
2022-05-23[x86_64]: Zhaoxin lujiazui enablementMayshao3-1/+64
This patch fix Zhaoxin CPU vendor ID detection problem and add zhaoxin "lujiazui" processor support. Currently gcc can't recognize Zhaoxin CPU (vendor ID "CentaurHauls" and "Shanghai") if user use -march=native option, which is confusing for users. This patch enables -march=native in zhaoxin family 7th processor and -march/-mtune=lujiazui, costs and tunning are set according to the characteristics of the processor. We add a new md file to describe lujiazui pipeline. Testing: Bootstrap is ok, and no regressions for i386/x86-64 testsuite. Background: Related Zhaoxin linux kernel patch can be found at: https://lore.kernel.org/lkml/01042674b2f741b2aed1f797359bdffb@zhaoxin.com/ Related Zhaoxin glibc patch can be found at: https://sourceware.org/git/?p=glibc.git;a=commit;h=32ac0b988466785d6e3cc1dffc364bb26fc63193 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Detect the specific type of Zhaoxin CPU, and return Zhaoxin CPU name. (cpu_indicator_init): Handle Zhaoxin processors. * common/config/i386/i386-common.cc: Add lujiazui. * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add VENDOR_ZHAOXIN. (enum processor_types): Add ZHAOXIN_FAM7H. (enum processor_subtypes): Add ZHAOXIN_FAM7H_LUJIAZUI. * config.gcc: Add lujiazui. * config/i386/cpuid.h (signature_SHANGHAI_ebx): Add Signatures for zhaoxin (signature_SHANGHAI_ecx): Ditto. (signature_SHANGHAI_edx): Ditto. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize lujiazui processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add lujiazui. * config/i386/i386-options.cc (m_LUJIAZUI): New_definition. * config/i386/i386.h (enum processor_type): Ditto. * config/i386/i386.md: Add lujiazui. * config/i386/x86-tune-costs.h (struct processor_costs): Add lujiazui costs. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add lujiazui. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Add lujiazui Tunnings. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_MOVX): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_LCP_STALL): Ditto. (X86_TUNE_USE_INCDEC): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_OPT_AGU): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_EXPAND_ABS): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_USE_FFREEP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. * doc/extend.texi: Add details about lujiazui. * doc/invoke.texi: Add details about lujiazui. * config/i386/lujiazui.md: Introduce lujiazui cpu and include new md file. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Test -arch=lujiauzi and -tune=lujiazui. * g++.target/i386/mv32.C: Ditto. Signed-off-by: mayshao <mayshao-oc@zhaoxin.com>
2022-05-23RISC-V: Fix canonical extension order (K and J)Tsukasa OI1-1/+1
This commit fixes canonical extension order to follow the RISC-V ISA Manual draft-20210402-1271737 or later. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_supported_std_ext): Fix "K" extension prefix to be placed before "J". * config/riscv/arch-canonicalize: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
2022-05-16Use more ARRAY_SIZE.Martin Liska1-2/+1
gcc/ada/ChangeLog: * locales.c (iso_639_1_to_639_3): Use ARRAY_SIZE. (language_name_to_639_3): Likewise. (country_name_to_3166): Likewise. gcc/analyzer/ChangeLog: * engine.cc (exploded_node::get_dot_fillcolor): Use ARRAY_SIZE. * function-set.cc (test_stdio_example): Likewise. * sm-file.cc (get_file_using_fns): Likewise. * sm-malloc.cc (malloc_state_machine::unaffected_by_call_p): Likewise. * sm-signal.cc (get_async_signal_unsafe_fns): Likewise. gcc/ChangeLog: * attribs.cc (diag_attr_exclusions): Use ARRAY_SIZE. (decls_mismatched_attributes): Likewise. * builtins.cc (c_strlen): Likewise. * cfg.cc (DEF_BASIC_BLOCK_FLAG): Likewise. * common/config/aarch64/aarch64-common.cc (aarch64_option_init_struct): Likewise. * config/aarch64/aarch64-builtins.cc (aarch64_lookup_simd_builtin_type): Likewise. (aarch64_init_simd_builtin_types): Likewise. (aarch64_init_builtin_rsqrt): Likewise. * config/aarch64/aarch64.cc (is_madd_op): Likewise. * config/arm/arm-builtins.cc (arm_lookup_simd_builtin_type): Likewise. (arm_init_simd_builtin_types): Likewise. * config/avr/gen-avr-mmcu-texi.cc (mcus[ARRAY_SIZE): Likewise. (c_prefix): Likewise. (main): Likewise. * config/c6x/c6x.cc (N_SAVE_ORDER): Likewise. * config/darwin-c.cc (darwin_register_frameworks): Likewise. * config/gcn/mkoffload.cc (process_obj): Likewise. * config/i386/i386-builtins.cc (get_builtin_code_for_version): Likewise. (fold_builtin_cpu): Likewise. * config/m32c/m32c.cc (PUSHM_N): Likewise. * config/nvptx/mkoffload.cc (process): Likewise. * config/rs6000/driver-rs6000.cc (host_detect_local_cpu): Likewise. * config/s390/s390.cc (NR_C_MODES): Likewise. * config/tilepro/gen-mul-tables.cc (find_sequences): Likewise. (create_insn_code_compression_table): Likewise. * config/vms/vms.cc (NBR_CRTL_NAMES): Likewise. * diagnostic-format-json.cc (json_from_expanded_location): Likewise. * dwarf2out.cc (ARRAY_SIZE): Likewise. * genhooks.cc (emit_documentation): Likewise. (emit_init_macros): Likewise. * gimple-ssa-sprintf.cc (format_floating): Likewise. * gimple-ssa-warn-access.cc (memmodel_name): Likewise. * godump.cc (keyword_hash_init): Likewise. * hash-table.cc (hash_table_higher_prime_index): Likewise. * input.cc (for_each_line_table_case): Likewise. * ipa-free-lang-data.cc (free_lang_data): Likewise. * ipa-inline.cc (sanitize_attrs_match_for_inline_p): Likewise. * optc-save-gen.awk: Likewise. * spellcheck.cc (test_metric_conditions): Likewise. * tree-vect-slp-patterns.cc (sizeof): Likewise. (ARRAY_SIZE): Likewise. * tree.cc (build_common_tree_nodes): Likewise. gcc/c-family/ChangeLog: * c-common.cc (ARRAY_SIZE): Use ARRAY_SIZE. (c_common_nodes_and_builtins): Likewise. * c-format.cc (check_tokens): Likewise. (check_plain): Likewise. * c-pragma.cc (c_pp_lookup_pragma): Likewise. (init_pragma): Likewise. * known-headers.cc (get_string_macro_hint): Likewise. (get_stdlib_header_for_name): Likewise. * c-attribs.cc: Likewise. gcc/c/ChangeLog: * c-decl.cc (match_builtin_function_types): Use ARRAY_SIZE. gcc/cp/ChangeLog: * module.cc (depset::entity_kind_name): Use ARRAY_SIZE. * name-lookup.cc (get_std_name_hint): Likewise. * parser.cc (cp_parser_new): Likewise. gcc/fortran/ChangeLog: * frontend-passes.cc (gfc_code_walker): Use ARRAY_SIZE. * openmp.cc (gfc_match_omp_context_selector_specification): Likewise. * trans-intrinsic.cc (conv_intrinsic_ieee_builtin): Likewise. * trans-types.cc (gfc_get_array_descr_info): Likewise. gcc/jit/ChangeLog: * jit-builtins.cc (find_builtin_by_name): Use ARRAY_SIZE. (get_string_for_type_id): Likewise. * jit-recording.cc (recording::context::context): Likewise. gcc/lto/ChangeLog: * lto-common.cc (lto_resolution_read): Use ARRAY_SIZE. * lto-lang.cc (lto_init): Likewise.
2022-05-11i386: simplify cpu_feature handlingMartin Liska1-22/+28
The patch removes unneeded loops for cpu_features2 and CONVERT_EXPR that can be simplified with NOP_EXPR. gcc/ChangeLog: * common/config/i386/cpuinfo.h (has_cpu_feature): Directly compute index in cpu_features2. (set_cpu_feature): Likewise. * config/i386/i386-builtins.cc (fold_builtin_cpu): Also remove loop for cpu_features2 and use NOP_EXPRs.
2022-04-12IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel1-2/+2
So far z16 was identified as arch14. After the machine has been announced we can now add the real name. gcc/ChangeLog: * common/config/s390/s390-common.cc: Rename PF_ARCH14 to PF_Z16. * config.gcc: Add z16 as march/mtune switch. * config/s390/driver-native.cc (s390_host_detect_local_cpu): Recognize z16 with -march=native. * config/s390/s390-opts.h (enum processor_type): Rename PROCESSOR_ARCH14 to PROCESSOR_3931_Z16. * config/s390/s390.cc (PROCESSOR_ARCH14): Rename to ... (PROCESSOR_3931_Z16): ... throughout the file. (s390_processor processor_table): Add z16 as cpu string. * config/s390/s390.h (enum processor_flags): Rename PF_ARCH14 to PF_Z16. (TARGET_CPU_ARCH14): Rename to ... (TARGET_CPU_Z16): ... this. (TARGET_CPU_ARCH14_P): Rename to ... (TARGET_CPU_Z16_P): ... this. (TARGET_ARCH14): Rename to ... (TARGET_Z16): ... this. (TARGET_ARCH14_P): Rename to ... (TARGET_Z16_P): ... this. * config/s390/s390.md (cpu_facility): Rename arch14 to z16 and check TARGET_Z16 instead of TARGET_ARCH14. * config/s390/s390.opt: Add z16 to processor_type. * doc/invoke.texi: Document z16 and arch14.
2022-03-29LoongArch Port: gcc buildchenglulu1-0/+43
2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> Lulu Cheng <chenglulu@loongson.cn> gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: New file. * config/loongarch/genopts/genstr.sh: New file. * config/loongarch/genopts/loongarch-strings: New file. * config/loongarch/genopts/loongarch.opt.in: New file. * config/loongarch/loongarch-str.h: New file. * config/loongarch/gnu-user.h: New file. * config/loongarch/linux.h: New file. * config/loongarch/loongarch-cpu.cc: New file. * config/loongarch/loongarch-cpu.h: New file. * config/loongarch/loongarch-def.c: New file. * config/loongarch/loongarch-def.h: New file. * config/loongarch/loongarch-driver.cc: New file. * config/loongarch/loongarch-driver.h: New file. * config/loongarch/loongarch-opts.cc: New file. * config/loongarch/loongarch-opts.h: New file. * config/loongarch/loongarch.opt: New file. * config/loongarch/t-linux: New file. * config/loongarch/t-loongarch: New file. * config.gcc: Add LoongArch support. * configure.ac: Add LoongArch support. contrib/ChangeLog: * gcc_update (files_and_dependencies): Add config/loongarch/loongarch.opt and config/loongarch/loongarch-str.h.
2022-03-21x86: Disable SSE in ISA2 for -mgeneral-regs-onlyH.J. Lu1-1/+1
Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and AVX512 ISAs. gcc/ PR target/105000 * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. gcc/testsuite/ PR target/105000 * gcc.target/i386/pr105000-1.c: New test. * gcc.target/i386/pr105000-2.c: Likewise. * gcc.target/i386/pr105000-3.c: Likewise. * gcc.target/i386/pr105000-4.c: Likewise.
2022-03-21x86: Properly check FEATURE_AESKLEH.J. Lu1-2/+2
1. Pass 0x19 to __cpuid for bit_AESKLE. 2. Enable FEATURE_AESKLE only if bit_AESKLE is set. PR target/104998 * common/config/i386/cpuinfo.h (get_available_features): Pass 0x19 to __cpuid for bit_AESKLE. Enable FEATURE_AESKLE only if bit_AESKLE is set.
2022-03-21RISC-V: Implement misc macro for vector extensions.Kito Cheng1-8/+8
See also: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Update flag name and mask name. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define misc macro for vector extensions. * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ... (MASK_VECTOR_ELEN_32): ... this. (MASK_VECTOR_EEW_64): Rename to ... (MASK_VECTOR_ELEN_64): ... this. (MASK_VECTOR_EEW_FP_32): Rename to ... (MASK_VECTOR_ELEN_FP_32): ... this. (MASK_VECTOR_EEW_FP_64): Rename to ... (MASK_VECTOR_ELEN_FP_64): ... this. (TARGET_VECTOR_ELEN_32): New. (TARGET_VECTOR_ELEN_64): Ditto. (TARGET_VECTOR_ELEN_FP_32): Ditto. (TARGET_VECTOR_ELEN_FP_64): Ditto. (TARGET_MIN_VLEN): Ditto. * config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ... (riscv_vector_elen_flags): ... this. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-13.c: New. * gcc.target/riscv/arch-14.c: Ditto. * gcc.target/riscv/arch-15.c: Ditto. * gcc.target/riscv/predef-18.c: Ditto. * gcc.target/riscv/predef-19.c: Ditto. * gcc.target/riscv/predef-20.c: Ditto.
2022-03-16RISC-V: Add version info for zk, zkn and zksKito Cheng1-0/+4
We just expand `zk`, `zkn` and `zks` before, but need version for combine them back. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add version info for zk, zks and zkn.
2022-03-16RISC-V: Handle combine extension in canonical ordering.LiaoShihua1-0/+56
The crypto extension have several shorthand extensions that don't consist of any extra instructions. Take zk for example, while the extension would imply zkn, zkr, zkt. The 3 extensions should also combine back into zk to maintain the canonical order in isa strings. This patch addresses the above. And if the other extension has the same situation, you can add them in riscv_combine_info[] gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_combine_info): New. (riscv_subset_list::handle_combine_ext): Combine back into zk to maintain the canonical order in isa strings. (riscv_subset_list::parse): Ditto. * config/riscv/riscv-subset.h (handle_combine_ext): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-17.c: New test.
2022-03-04rs6000: Allow -mlong-double-64 after -mabi={ibm,ieee}longdouble [PR104208, ↵Peter Bergner1-0/+10
PR87496] The glibc build is showing a build error due to extra "error" checking from my PR87496 fix. That checking was overeager, disallowing setting the long double size to 64-bits if the 128-bit long double ABI had already been specified. Now we only emit an error if we specify a 128-bit long double ABI if our long double size is not 128 bits. This also fixes an erroneous error when -mabi=ieeelongdouble is used and ISA 2.06 is not enabled, but the long double size has been changed to 64 bits. 2022-03-04 Peter Bergner <bergner@linux.ibm.com> gcc/ PR target/87496 PR target/104208 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Make the ISA 2.06 requirement for -mabi=ieeelongdouble conditional on -mlong-double-128. Move the -mabi=ieeelongdouble and -mabi=ibmlongdouble error checking from here... * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): ... to here. gcc/testsuite/ PR target/87496 PR target/104208 * gcc.target/powerpc/pr104208-1.c: New test. * gcc.target/powerpc/pr104208-2.c: Likewise. * gcc.target/powerpc/pr87496-2.c: Swap long double options to trigger the expected error. * gcc.target/powerpc/pr87496-3.c: Likewise.
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