aboutsummaryrefslogtreecommitdiff
path: root/gcc/common
AgeCommit message (Collapse)AuthorFilesLines
2024-07-28aarch64: Extend aarch64_feature_flags to 128 bitsAndrew Carlotti1-4/+8
Replace the existing uint64_t typedef with a bbitmap<2> typedef. Most of the preparatory work was carried out in previous commits, so this patch itself is fairly small. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): Store a second uint64_t value. * config/aarch64/aarch64-opts.h (aarch64_feature_flags): Switch typedef to bbitmap<2>. * config/aarch64/aarch64.cc (aarch64_set_current_function): Extract isa mode from val[0]. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): Load a second uint64_t value. (aarch64_get_isa_flags): Ditto. (aarch64_asm_isa_flags): Ditto. (aarch64_isa_flags): Ditto. (HANDLE): Use bbitmap<2>::from_index to initialise flags. (AARCH64_FL_ISA_MODES): Do arithmetic on integer type. (AARCH64_ISA_MODE): Extract value from bbitmap<2> array. * config/aarch64/aarch64.opt (aarch64_asm_isa_flags_1): New variable. (aarch64_isa_flags_1): Ditto.
2024-07-28aarch64: Decouple feature flag option storage typeAndrew Carlotti1-5/+6
The awk scripts that process the .opt files are relatively fragile and only handle a limited set of data types correctly. The unrecognised aarch64_feature_flags type is handled as a uint64_t, which happens to be correct for now. However, that assumption will change when we extend the mask to 128 bits. This patch changes the option members to use uint64_t types, and adds a "_0" suffix to the names (both for future extensibility, and to allow the original name to be used for the full aarch64_feature_flags mask within generator files). gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): Reorder, and add suffix to names. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): Add "_0" suffix. (aarch64_get_isa_flags): Ditto. (aarch64_asm_isa_flags): Redefine using renamed uint64_t value. (aarch64_isa_flags): Ditto. * config/aarch64/aarch64.opt: (aarch64_asm_isa_flags): Rename to... (aarch64_asm_isa_flags_0): ...this, and change to uint64_t. (aarch64_isa_flags): Rename to... (aarch64_isa_flags_0): ...this, and change to uint64_t.
2024-07-28aarch64: Define aarch64_get_{asm_|}isa_flagsAndrew Carlotti1-1/+1
Building an aarch64_feature_flags value from data within a gcc_options or cl_target_option struct will get more complicated in a later commit. Use a macro to avoid doing this manually in more than one location. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_handle_option): Use new macro. * config/aarch64/aarch64.cc (aarch64_override_options_internal): Ditto. (aarch64_option_print): Ditto. (aarch64_set_current_function): Ditto. (aarch64_can_inline_p): Ditto. (aarch64_declare_function_name): Ditto. (aarch64_start_file): Ditto. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): New (aarch64_get_isa_flags): New. (aarch64_asm_isa_flags): Use new macro. (aarch64_isa_flags): Ditto.
2024-07-15RISC-V: Allow adding enabled extension via target arch attributesChristoph Müllner1-6/+11
The set of enabled extensions can be extended via target arch function attributes by listing each extension with a '+' prefix and a comma as list separator. E.g.: __attribute__((target("arch=+zba,+zbb"))) void foo(); The programmer intends to ensure that one or more extensions are enabled when building the code. This is independent of the arch string that is passed at build time via the -march= option. Therefore, it is reasonable to allow enabling extensions via target arch attributes, which have already been enabled via the -march= string. The subset list code already supports such duplication for implied extensions. This patch adds an interface so the subset list parser can be switched into a mode where duplication is allowed. This commit fixes the following regressed test cases: * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::add): Allow adding enabled extension if m_allow_adding_dup is set. * config/riscv/riscv-subset.h: Add m_allow_adding_dup and setter. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Allow adding enabled extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr115554.c: Change expected fail to expected pass. * gcc.target/riscv/target-attr-16.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-07-15RISC-V: Rewrite target attribute handlingChristoph Müllner1-109/+4
The target-arch attribute handling in RISC-V is only a few months old, but already saw a rewrite (9941f0295a14), which addressed an important issue. This rewrite introduced a hash table in the backend, which is used to keep track of target-arch attributes of all functions. The index of this hash table is the pointer to the function declaration object (fndecl). However, objects like these don't have the lifetime that is assumed here, which resulted in observing two fndecl objects with the same address for different objects (triggering the assertion in riscv_func_target_put() -- see also PR115562). This patch removes the hash table approach in favor of storing target specific options using the DECL_FUNCTION_SPECIFIC_TARGET() macro, which is also used by other backends and is specifically designed for this purpose (https://gcc.gnu.org/onlinedocs/gccint/Function-Properties.html). To have an accessible field in the target options, we need to adjust riscv.opt and introduce the field riscv_arch_string (for the already existing option '-march='). Using this macro allows to remove much code from riscv-common.cc, which controls access to the objects 'func_target_table' and 'current_subset_list'. One thing to mention is, that we had two subset lists: current_subset_list and cmdline_subset_list, with the latter being introduced recently for target attribute handling. This patch reduces them back to one (cmdline_subset_list) which contains the list of extensions that have been enabled by the command line arguments. Note that the patch keeps the existing behavior of rejecting duplications of extensions when added via the '+' operator in a function target attribute. E.g. "-march=rv64gc_zbb" and "arch=+zbb" will trigger an error (see pr115554.c). However, at the same time this patch breaks the acceptance of adding implied extensions, which causes the following six regressions (with the error "extension 'EXT' appear more than one time"): * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c New tests were added to document the behavior and to ensure it won't regress. This patch did not show any regressions for rv32/rv64 and fixes the ICEs from PR115554 and PR115562. PR target/115554 PR target/115562 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (struct riscv_func_target_info): Remove. (struct riscv_func_target_hasher): Likewise. (riscv_func_decl_hash): Likewise. (riscv_func_target_hasher::hash): Likewise. (riscv_func_target_hasher::equal): Likewise. (riscv_current_subset_list): Likewise. (riscv_cmdline_subset_list): Remove obsolete space. (riscv_func_target_table_lazy_init): Remove. (riscv_func_target_get): Likewise. (riscv_func_target_put): Likewise. (riscv_func_target_remove_and_destory): Likewise. (riscv_arch_str): Generate from cmdline_subset_list. (riscv_set_arch_by_subset_list): Don't set current_subset_list. (riscv_parse_arch_string): Remove current_subset_list. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Get subset list via riscv_cmdline_subset_list(). * config/riscv/riscv-subset.h (riscv_current_subset_list): Remove prototype. (riscv_func_target_get): Likewise. (riscv_func_target_put): Likewise. (riscv_func_target_remove_and_destory): Likewise. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Build base arch string from existing target options, if any. (riscv_target_attr_parser::update_settings): Store new arch string in target options. (riscv_process_one_target_attr): Whitespace fix. (riscv_process_target_attr): Drop opts argument. (riscv_option_valid_attribute_p): Properly save, change and restore target options. * config/riscv/riscv.cc (get_arch_str): New function. (riscv_declare_function_name): Get arch string for option-arch directive from function's target options. * config/riscv/riscv.opt: Add riscv_arch_string variable to march option. gcc/testsuite/ChangeLog: * gcc.target/riscv/target-attr-01.c: Add test for option-arch directive. * gcc.target/riscv/target-attr-02.c: Likewise. * gcc.target/riscv/target-attr-03.c: Likewise. * gcc.target/riscv/target-attr-04.c: Likewise. * gcc.target/riscv/target-attr-05.c: Fix formatting. * gcc.target/riscv/target-attr-06.c: Likewise. * gcc.target/riscv/target-attr-07.c: Likewise. * gcc.target/riscv/pr115554.c: New test. * gcc.target/riscv/pr115562.c: New test. * gcc.target/riscv/target-attr-08.c: New test. * gcc.target/riscv/target-attr-09.c: New test. * gcc.target/riscv/target-attr-10.c: New test. * gcc.target/riscv/target-attr-11.c: New test. * gcc.target/riscv/target-attr-12.c: New test. * gcc.target/riscv/target-attr-13.c: New test. * gcc.target/riscv/target-attr-14.c: New test. * gcc.target/riscv/target-attr-15.c: New test. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-07-12RISC-V: Add SiFive extensions, xsfvcp and xsfceaseKito Cheng1-0/+8
We have already upstreamed these extensions into binutils, and now we need GCC to recognize these extensions and pass them to binutils as well. We also plan to upstream intrinsics in the near future. :) gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add xsfvcp. (riscv_ext_version_table): Add xsfvcp, xsfcease. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt (riscv_sifive_subext): New. (XSFVCP): New. (XSFCEASE): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-1.c: New. * gcc.target/riscv/predef-sf-2.c: New.
2024-07-11RISC-V: c implies zca, and conditionally zcf & zcdFei Gao1-0/+12
According to Zc-1.0.4-3.pdf from https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 The rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd Signed-off-by: Fei Gao <gaofei@eswincomputing.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: c implies zca, and conditionally zcf & zcd. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: adapt TC. * gcc.target/riscv/attribute-16.c: likewise. * gcc.target/riscv/attribute-17.c: likewise. * gcc.target/riscv/attribute-18.c: likewise. * gcc.target/riscv/pr110696.c: likewise. * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. * gcc.target/riscv/arch-39.c: New test. * gcc.target/riscv/arch-40.c: New test.
2024-07-10RISC-V: Add support for B standard extensionEdwin Lu1-0/+7
This patch adds support for recognizing the B standard extension to be the collection of Zba, Zbb, Zbs extensions for consistency and conciseness across toolchains https://github.com/riscv/riscv-b/tags gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add imply rules for B extension * config/riscv/arch-canonicalize: Ditto Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-07-09RISC-V: Deduplicate arch subset list processingChristoph Müllner1-26/+6
We have a code duplication in riscv_set_arch_by_subset_list() and riscv_parse_arch_string(), where the latter function parses an ISA string into a subset_list before doing the same as the former function. riscv_parse_arch_string() is used to process command line options and riscv_set_arch_by_subset_list() processes target attributes. So, it is obvious that both functions should do the same. Let's deduplicate the code to enforce this. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_set_arch_by_subset_list): Fix overlong line. (riscv_parse_arch_string): Replace duplicated code by a call to riscv_set_arch_by_subset_list. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-07-09i386: Correct AVX10 CPUID emulationHaochen Jiang1-2/+2
AVX10 Documentaion has specified ecx value as 0 for AVX10 version and vector size under 0x24 subleaf. Although for ecx=1, the bits are all reserved for now, we still need to specify ecx as 0 to avoid dirty value in ecx. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Correct AVX10 CPUID emulation to specify ecx value.
2024-07-08[RISC-V] add implied extension repeatly until stableFei Gao1-3/+11
Call handle_implied_ext repeatly until there's no new subset added into the subset list. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::riscv_subset_list): init m_subset_num to 0. (riscv_subset_list::add): increase m_subset_num once a subset added. (riscv_subset_list::finalize): call handle_implied_ext repeatly until no change in m_subset_num. * config/riscv/riscv-subset.h: add m_subset_num member. Signed-off-by: Fei Gao <gaofei@eswincomputing.com>
2024-07-03RISC-V: Add support for Zabha extensionGianluca Guida1-0/+12
The Zabha extension adds support for subword Zaamo ops. Extension: https://github.com/riscv/riscv-zabha.git Ratification: https://jira.riscv.org/browse/RVS-1685 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip zabha when not supported by the assembler. * config.in: Regenerate. * config/riscv/arch-canonicalize: Make zabha imply zaamo. * config/riscv/iterators.md (amobh): Add iterator for amo byte/halfword. * config/riscv/riscv.opt: Add zabha. * config/riscv/sync.md (atomic_<atomic_optab><mode>): Add subword atomic op pattern. (zabha_atomic_fetch_<atomic_optab><mode>): Add subword atomic_fetch op pattern. (lrsc_atomic_fetch_<atomic_optab><mode>): Prefer zabha over lrsc for subword atomic ops. (zabha_atomic_exchange<mode>): Add subword atomic exchange pattern. (lrsc_atomic_exchange<mode>): Prefer zabha over lrsc for subword atomic exchange ops. * configure: Regenerate. * configure.ac: Add zabha assembler check. * doc/sourcebuild.texi: Add zabha documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zabha testsuite infra support. * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to test the lr/sc subword patterns. * gcc.target/riscv/amo/inline-atomics-2.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test. * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test. Co-Authored-By: Patrick O'Neill <patrick@rivosinc.com> Signed-Off-By: Gianluca Guida <gianluca@rivosinc.com> Tested-by: Andrea Parri <andrea@rivosinc.com>
2024-06-19RISC-V: Promote Zaamo/Zalrsc to a when using an old binutilsPatrick O'Neill1-0/+1
Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify both Zaamo and Zalrsc, promote them to 'a' in the -march string. This does not affect testsuite results for users with old versions of binutils. Testcases that failed due to 'call'/isa string continue to fail after this PATCH when using an old version of binutils. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add 'a' extension to riscv_combine_info. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2024-06-19i386: Zhaoxin shijidadao enablementmayshao3-3/+14
This patch enables -march/-mtune=shijidadao, costs and tunings are set according to the characteristics of the processor. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize shijidadao. * common/config/i386/i386-common.cc: Add shijidadao. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add ZHAOXIN_FAM7H_SHIJIDADAO. * config.gcc: Add shijidadao. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize shijidadao processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add shijidadao. * config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO. (m_SHIJIDADAO): New definition. * config/i386/i386.h (enum processor_type): Add PROCESSOR_SHIJIDADAO. * config/i386/x86-tune-costs.h (struct processor_costs): Add shijidadao_cost. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add m_SHIJIDADAO. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER_8PARTS): Ditto. (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. * doc/extend.texi: Add details about shijidadao. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv32.C: Handle new -march * gcc.target/i386/funcspec-56.inc: Ditto.
2024-06-17RISC-V: Add configure check for Zaamo/Zalrsc assembler supportPatrick O'Neill1-0/+11
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure check to prevent emitting Zaamo/Zalrsc in the arch string when the assember does not support it. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip zaamo/zalrsc when not supported by the assembler. * config.in: Regenerate. * configure: Regenerate. * configure.ac: Add zaamo/zalrsc assmeber check. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V
2024-06-11RISC-V: Add basic Zaamo and Zalrsc supportEdwin Lu1-2/+9
There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc. * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc. * config/riscv/riscv.opt: Add Zaamo and Zalrsc * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and TARGET_ZALRSC. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-15.c: Adjust expected arch string. * gcc.target/riscv/attribute-16.c: Ditto. * gcc.target/riscv/attribute-17.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/pr110696.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto. * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto. Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Patrick O'Neill <patrick@rivosinc.com>
2024-06-03Add AVX10.1 target_clones supportHaochen Jiang3-5/+8
Since AVX10 is the first major ISA introduced after AVX-512, we propose to add target_clones support for it. Although AVX10.1-256 won't cover 512-bit part of AVX512F, but since it is only for priority but not for implication, it won't be an issue. gcc/ChangeLog: * common/config/i386/i386-common.cc: Change Granite Rapids series CPU type to P_PROC_AVX10_1_512. * common/config/i386/i386-cpuinfo.h (enum feature_priority): Revise comment part. Add P_AVX10_1_256, P_AVX10_1_512, P_PROC_AVX10_1_512. * common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-25.c: New test. * gcc.target/i386/avx10_1-26.c: Ditto.
2024-05-20i386: Remove Xeon Phi ISA supportHaochen Jiang4-134/+5
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Remove Xeon Phi cpus. (get_available_features): Remove Xeon Phi ISAs. * common/config/i386/i386-common.cc (OPTION_MASK_ISA_AVX512PF_SET): Removed. (OPTION_MASK_ISA_AVX512ER_SET): Ditto. (OPTION_MASK_ISA2_AVX5124FMAPS_SET): Ditto. (OPTION_MASK_ISA2_AVX5124VNNIW_SET): Ditto. (OPTION_MASK_ISA_PREFETCHWT1_SET): Ditto. (OPTION_MASK_ISA_AVX512F_UNSET): Remove AVX512PF and AVX512ER. (OPTION_MASK_ISA_AVX512PF_UNSET): Removed. (OPTION_MASK_ISA_AVX512ER_UNSET): Ditto. (OPTION_MASK_ISA2_AVX5124FMAPS_UNSET): Ditto. (OPTION_MASK_ISA2_AVX5124VNNIW_UNSET): Ditto. (OPTION_MASK_ISA_PREFETCHWT1_UNSET): Ditto. (OPTION_MASK_ISA2_AVX512F_UNSET): Remove AVX5124FMAPS and AVX5125VNNIW. (ix86_handle_option): Remove Xeon Phi options. (processor_names): Remove Xeon Phi cpus. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Ditto. (enum processor_features): Remove Xeon Phi ISAs. * common/config/i386/i386-isas.h: Ditto. * config.gcc: Remove Xeon Phi cpus and ISAs. * config/i386/avx5124fmapsintrin.h: Remove intrin support. * config/i386/avx5124vnniwintrin.h: Ditto. * config/i386/avx512erintrin.h: Ditto. * config/i386/avx512pfintrin.h: Ditto. * config/i386/cpuid.h (bit_AVX512PF): Removed. (bit_AVX512ER): Ditto. (bit_PREFETCHWT1): Ditto. (bit_AVX5124VNNIW): Ditto. (bit_AVX5124FMAPS): Ditto. * config/i386/driver-i386.cc (host_detect_local_cpu): Remove Xeon Phi. * config/i386/i386-builtin-types.def: Remove unused types. * config/i386/i386-builtin.def (BDESC): Remove builtins. * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Ditto. * config/i386/i386-c.cc (ix86_target_macros_internal): Remove Xeon Phi cpus and ISAs. * config/i386/i386-expand.cc (ix86_expand_builtin): Remove Xeon Phi related handlers. (ix86_emit_swdivsf): Ditto. (ix86_emit_swsqrtsf): Ditto. * config/i386/i386-isa.def: Remove Xeon Phi ISAs. * config/i386/i386-options.cc (m_KNL): Removed. (m_KNM): Ditto. (isa2_opts): Remove Xeon Phi ISAs. (isa_opts): Ditto. (processor_cost_table): Remove Xeon Phi cpus. (ix86_valid_target_attribute_inner_p): Remove Xeon Phi ISAs. (ix86_option_override_internal): Remove Xeon Phi related handlers. * config/i386/i386-rust.cc (ix86_rust_target_cpu_info): Remove Xeon Phi ISAs. * config/i386/i386.cc (ix86_hard_regno_mode_ok): Remove Xeon Phi related handler. * config/i386/i386.h (TARGET_EMIT_VZEROUPPER): Removed. (enum processor_type): Remove Xeon Phi cpus. * config/i386/i386.md (prefetch): Remove PREFETCHWT1. (*prefetch_3dnow): Ditto. (*prefetch_prefetchwt1): Removed. * config/i386/i386.opt: Remove Xeon Phi ISAs. * config/i386/immintrin.h: Ditto. * config/i386/sse.md (VF1_AVX512ER_128_256): Removed. (rsqrt<mode>2): Change iterator from VF1_AVX512ER_128_256 to VF1_128_256. (GATHER_SCATTER_SF_MEM_MODE): Removed. (avx512pf_gatherpf<mode>sf): Ditto. (*avx512pf_gatherpf<VI48_512:mode>sf_mask): Ditto. (avx512pf_gatherpf<mode>df): Ditto. (*avx512pf_gatherpf<VI4_256_8_512:mode>df_mask): Ditto. (avx512pf_scatterpf<mode>sf): Ditto. (*avx512pf_scatterpf<VI48_512:mode>sf_mask): Ditto. (avx512pf_scatterpf<mode>df): Ditto. (*avx512pf_scatterpf<VI4_256_8_512:mode>df_mask): Ditto. (exp2<mode>2): Ditto. (avx512er_exp2<mode><mask_name><round_saeonly_name>): Ditto. (<mask_codefor>avx512er_rcp28<mode><mask_name><round_saeonly_name>): Ditto. (avx512er_vmrcp28<mode><mask_name><round_saeonly_name>): Ditto. (<mask_codefor>avx512er_rsqrt28<mode><mask_name><round_saeonly_name>): Ditto. (avx512er_vmrsqrt28<mode><mask_name><round_saeonly_name>): Ditto. (IMOD4): Ditto. (imod4_narrow): Ditto. (mov<mode>): Ditto. (*mov<mode>_internal): Ditto. (avx5124fmaddps_4fmaddps): Ditto. (avx5124fmaddps_4fmaddps_mask): Ditto. (avx5124fmaddps_4fmaddps_maskz): Ditto. (avx5124fmaddps_4fmaddss): Ditto. (avx5124fmaddps_4fmaddss_mask): Ditto. (avx5124fmaddps_4fmaddss_maskz): Ditto. (avx5124fmaddps_4fnmaddps): Ditto. (avx5124fmaddps_4fnmaddps_mask): Ditto. (avx5124fmaddps_4fnmaddps_maskz): Ditto. (avx5124fmaddps_4fnmaddss): Ditto. (avx5124fmaddps_4fnmaddss_mask): Ditto. (avx5124fmaddps_4fnmaddss_maskz): Ditto. (avx5124vnniw_vp4dpwssd): Ditto. (avx5124vnniw_vp4dpwssd_mask): Ditto. (avx5124vnniw_vp4dpwssd_maskz): Ditto. (avx5124vnniw_vp4dpwssds): Ditto. (avx5124vnniw_vp4dpwssds_mask): Ditto. (avx5124vnniw_vp4dpwssds_maskz): Ditto. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Remove Xeon Phi cpus. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Ditto. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_MOVX): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. (X86_TUNE_FOUR_JUMP_LIMIT): Ditto. (X86_TUNE_USE_INCDEC): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_OPT_AGU): Ditto. (X86_TUNE_AVOID_LEA_FOR_ADDR): Ditto. (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_CLTD): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_EXPAND_ABS): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS): Ditto. (X86_TUNE_SLOW_PSHUFB): Ditto. (X86_TUNE_EMIT_VZEROUPPER): Removed. * config/i386/xmmintrin.h (enum _mm_hint): Remove _MM_HINT_ET1. * doc/extend.texi: Remove Xeon Phi. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Remove Xeon Phi ISAs. * g++.dg/other/i386-3.C: Ditto. * g++.target/i386/mv28.C: Ditto. * gcc.target/i386/builtin_target.c: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-26.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: Removed. * gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto. * gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto. * gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto. * gcc.target/i386/avx512er-check.h: Ditto. * gcc.target/i386/avx512er-vexp2pd-1.c: Ditto. * gcc.target/i386/avx512er-vexp2pd-2.c: Ditto. * gcc.target/i386/avx512er-vexp2ps-1.c: Ditto. * gcc.target/i386/avx512er-vexp2ps-2.c: Ditto. * gcc.target/i386/avx512er-vrcp28pd-1.c: Ditto. * gcc.target/i386/avx512er-vrcp28pd-2.c: Ditto. * gcc.target/i386/avx512er-vrcp28ps-1.c: Ditto. * gcc.target/i386/avx512er-vrcp28ps-2.c: Ditto. * gcc.target/i386/avx512er-vrcp28ps-3.c: Ditto. * gcc.target/i386/avx512er-vrcp28ps-4.c: Ditto. * gcc.target/i386/avx512er-vrcp28sd-1.c: Ditto. * gcc.target/i386/avx512er-vrcp28sd-2.c: Ditto. * gcc.target/i386/avx512er-vrcp28ss-1.c: Ditto. * gcc.target/i386/avx512er-vrcp28ss-2.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28pd-1.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28pd-2.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-1.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-2.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-3.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-4.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-5.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ps-6.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28sd-1.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28sd-2.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ss-1.c: Ditto. * gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf0dpd-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf0dps-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf0qpd-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf0qps-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf1dpd-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf1dps-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf1qpd-1.c: Ditto. * gcc.target/i386/avx512pf-vgatherpf1qps-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Ditto. * gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Ditto. * gcc.target/i386/pr104448.c: Ditto. * gcc.target/i386/pr82941-2.c: Ditto. * gcc.target/i386/pr82942-2.c: Ditto. * gcc.target/i386/pr82990-1.c: Ditto. * gcc.target/i386/pr82990-3.c: Ditto. * gcc.target/i386/pr82990-6.c: Ditto. * gcc.target/i386/pr82990-7.c: Ditto. * gcc.target/i386/pr89523-5.c: Ditto. * gcc.target/i386/pr89523-6.c: Ditto. * gcc.target/i386/pr91033.c: Ditto. * gcc.target/i386/prefetchwt1-1.c: Ditto.
2024-05-16RISC-V: Add Zvfbfwma extension to the -march= optionXiao Zeng1-0/+5
This patch would like to add new sub extension (aka Zvfbfwma) to the -march= option. It introduces a new data type BF16. 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Zvfbfmin's information is in: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09> 3 Zfbfmin's formation is in: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> 4 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. 5 You can locate more information about Zvfbfwma from below spec doc: <https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfbfwma item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt: (MASK_ZVFBFWMA): New macro. (TARGET_ZVFBFWMA): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-37.c: New test. * gcc.target/riscv/arch-38.c: New test. * gcc.target/riscv/predef-36.c: New test. * gcc.target/riscv/predef-37.c: New test.
2024-05-06[PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= optionXiao Zeng1-0/+3
This patch would like to add new sub extension (aka Zfbfmin) to the -march= option. It introduces a new data type BF16. 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. You can locate more information about Zfbfmin from below spec doc. <https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf> gcc/ * common/config/riscv/riscv-common.cc (riscv_implied_info): zfbfmin implies zfhmin. (riscv_ext_version_table, riscv_ext_flag_table): Add zfbfmin. * config/riscv/riscv.opt (ZFBFMIN): Add optoion. gcc/testsuite/ * gcc.target/riscv/arch-35.c: New test. * gcc.target/riscv/arch-36.c: New test. * gcc.target/riscv/predef-34.c: New test. * gcc.target/riscv/predef-35.c: New test.
2024-04-29RISC-V: Fix parsing of Zic* extensionsChristoph Müllner1-4/+4
The extension parsing table entries for a range of Zic* extensions does not match the mask definition in riscv.opt. This results in broken TARGET_ZIC* macros, because the values of riscv_zi_subext and riscv_zicmo_subext are set wrong. This patch fixes this by moving Zic64b into riscv_zicmo_subext and all other affected Zic* extensions to riscv_zi_subext. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Move ziccamoa, ziccif, zicclsm, and ziccrse into riscv_zi_subext. * config/riscv/riscv.opt: Define MASK_ZIC64B for riscv_ziccmo_subext. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-04-22i386: Fix Sierra Forest auto dispatchHaochen Jiang1-1/+1
gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_alias_table): Let Sierra Forest map to CPU_TYPE enum.
2024-03-31RISC-V: Fix one unused varable in riscv_subset_list::parsePan Li1-1/+0
This patch would like to fix one unused variable as below: ../../gcc/common/config/riscv/riscv-common.cc: In static member function 'static riscv_subset_list* riscv_subset_list::parse(const char*, location_t)': ../../gcc/common/config/riscv/riscv-common.cc:1501:19: error: unused variable 'itr' [-Werror=unused-variable] 1501 | riscv_subset_t *itr; The variable consume code was removed but missed the var itself in previous. Thus, we have unused variable here. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Remove unused var decl. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-22RISC-V: Bugfix function target attribute pollutionPan Li1-2/+103
This patch depends on below ICE fix. https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647915.html The function target attribute should be on a per-function basis. For example, we have 3 function as below: void test_1 () {} void __attribute__((target("arch=+v"))) test_2 () {} void __attribute__((target("arch=+zfh"))) test_3 () {} void test_4 () {} The scope of the target attribute should not extend the function body. Aka, test_3 cannot have the 'v' extension, as well as the test_4 cannot have both the 'v' and 'zfh' extension. Unfortunately, for now the test_4 is able to leverage the 'v' and the 'zfh' extension which is incorrect. This patch would like to fix the sticking attribute by introduce the commandline subset_list. When parse_arch, we always clone from the cmdline_subset_list instead of the current_subset_list. Meanwhile, we correct the print information about arch like below. .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0 The riscv_declare_function_name hook is always after the hook riscv_process_target_attr. Thus, we introduce one hash_map to record the 1:1 mapping from fndel to its' subset_list in advance. And later the riscv_declare_function_name is able to get the right information about the arch. Below test are passed for this patch * The riscv fully regression test. PR target/114352 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (struct riscv_func_target_info): New struct for func decl and target name. (struct riscv_func_target_hasher): New hasher for hash table mapping from the fn_decl to fn_target_name. (riscv_func_decl_hash): New func to compute the hash for fn_decl. (riscv_func_target_hasher::hash): New func to impl hash interface. (riscv_func_target_hasher::equal): New func to impl equal interface. (riscv_cmdline_subset_list): New static var for cmdline subset list. (riscv_func_target_table_lazy_init): New func to lazy init the func target hash table. (riscv_func_target_get): New func to get target name from hash table. (riscv_func_target_put): New func to put target name into hash table. (riscv_func_target_remove_and_destory): New func to remove target info from the hash table and destory it. (riscv_parse_arch_string): Set the static var cmdline_subset_list. * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static var for cmdline subset list. (riscv_func_target_get): New func decl. (riscv_func_target_put): Ditto. (riscv_func_target_remove_and_destory): Ditto. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Take cmdline_subset_list instead of current_subset_list when clone. (riscv_process_target_attr): Record the func target info to hash table. (riscv_option_valid_attribute_p): Add new arg tree fndel. * config/riscv/riscv.cc (riscv_declare_function_name): Consume the func target info and print the arch message. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr114352-3.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-22RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))Pan Li1-10/+21
This patch would like to fix one ICE for __attribute__((target("arch=+v")) and likewise extension(s). Given we have sample code as below: void __attribute__((target("arch=+v"))) test_2 (int *a, int *b, int *out, unsigned count) { unsigned i; for (i = 0; i < count; i++) out[i] = a[i] + b[i]; } It will have ICE when build with -march=rv64gc -O3. test.c: In function ‘test_2’: test.c:4:1: internal compiler error: Floating point exception 4 | { | ^ 0x1a5891b crash_signal .../__RISC-V_BUILD__/../gcc/toplev.cc:319 0x7f0a7884251f ??? ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0 0x1f51ba4 riscv_hard_regno_nregs .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143 0x1967bb9 init_reg_modes_target() .../__RISC-V_BUILD__/../gcc/reginfo.cc:471 0x13fc029 init_emit_regs() .../__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237 0x1a5b83d target_reinit() .../__RISC-V_BUILD__/../gcc/toplev.cc:1936 0x35e374d save_target_globals() .../__RISC-V_BUILD__/../gcc/target-globals.cc:92 0x35e381f save_target_globals_default_opts() .../__RISC-V_BUILD__/../gcc/target-globals.cc:122 0x1f544cc riscv_save_restore_target_globals(tree_node*) .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138 0x1f55c36 riscv_set_current_function ... There are two reasons for this ICE. 1. The implied extension(s) of v are not well handled and the TARGET_MIN_VLEN is 0 which is not reinitialized. Then the size / TARGET_MIN_VLEN will have DivideByZero. 2. The machine modes of the vector types will be vary after the v extension is introduced. This patch passed below testsuite: 1. The riscv fully regression test. PR target/114352 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Replace implied, combine and check to func finalize. (riscv_subset_list::finalize): New func impl to take care of implied, combine ext and related checks. * config/riscv/riscv-subset.h: Add func decl for finalize. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Finalize the ext before return succeed. * config/riscv/riscv.cc (riscv_set_current_function): Reinit the machine mode before when set cur function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr114352-1.c: New test. * gcc.target/riscv/rvv/base/pr114352-2.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-03-18[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Create XCVbi extension support. * config/riscv/riscv.opt: Likewise. * config/riscv/corev.md: Implement cv_branch<mode> pattern for cv.beqimm and cv.bneimm. * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V branch instruction pattern. * config/riscv/constraints.md: Implement constraints cv_bi_s5 - signed 5-bit immediate. * config/riscv/predicates.md: Implement predicate const_int5s_operand - signed 5 bit immediate. * doc/sourcebuild.texi: Add XCVbi documentation. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test. * lib/target-supports.exp: Add proc for XCVbi.
2024-03-18Add AMD znver5 processor enablement with scheduler modelJan Hubicka3-1/+23
2024-02-14 Jan Hubicka <jh@suse.cz> Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5. * common/config/i386/i386-common.cc (processor_names): Add znver5. (processor_alias_table): Likewise. * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen family. (processor_subtypes): Add znver5. * config.gcc (x86_64-*-* |...): Likewise. * config/i386/driver-i386.cc (host_detect_local_cpu): Let march=native detect znver5 cpu's. * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5. * config/i386/i386-options.cc (m_ZNVER5): New definition (processor_cost_table): Add znver5. * config/i386/i386.cc (ix86_reassociation_width): Likewise. * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5 (PTA_ZNVER5): New definition. * config/i386/i386.md (define_attr "cpu"): Add znver5. (Scheduling descriptions) Add znver5.md. * config/i386/x86-tune-costs.h (znver5_cost): New definition. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5. (avx512_store_by_pieces): Add m_ZNVER5. * doc/extend.texi: Add znver5. * doc/invoke.texi: Likewise. * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler. gcc/testsuite/ChangeLog: * g++.target/i386/mv29.C: Handle znver5 arch. * gcc.target/i386/funcspec-56.inc:Likewise.
2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay1-0/+2
The Reduced Tiny core does not support indirect addressing with offset, which basically means that every indirect memory access with a size of more than one byte is effectively POST_INC or PRE_DEC. The lack of that addressing mode is currently handled by pretending to support it, and then let the insn printers add and subtract again offsets as needed. For example, the following C code int vars[10]; void inc_var2 (void) { ++vars[2]; } is compiled to: ldi r30,lo8(vars) ; 14 [c=4 l=2] *movhi/4 ldi r31,hi8(vars) subi r30,lo8(-(4)) ; 15 [c=8 l=6] *movhi/2 sbci r31,hi8(-(4)) ld r20,Z+ ld r21,Z subi r30,lo8((4+1)) sbci r31,hi8((4+1)) subi r20,-1 ; 16 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 subi r30,lo8(-(4+1)) ; 17 [c=4 l=4] *movhi/3 sbci r31,hi8(-(4+1)) st Z,r21 st -Z,r20 where the code could be -- and with this patch actually is -- like ldi r30,lo8(vars+4) ; 28 [c=4 l=2] *movhi/4 ldi r31,hi8(vars+4) ld r20,Z+ ; 17 [c=8 l=2] *movhi/2 ld r21,Z+ subi r20,-1 ; 19 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 st -Z,r21 ; 30 [c=4 l=2] *movhi/3 st -Z,r20 This is achieved in two steps: - A post-reload split into "real" instructions during .split2. - A new avr-specific mini pass .avr-fuse-add that runs before RTL peephole and that tries to combine the generated pointer additions into memory accesses to form POST_INC or PRE_DEC. gcc/ PR target/114100 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. * config/avr/avr.opt (-mfuse-add=): New target option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. * config/avr/avr-protos.h (avr_split_tiny_move) (make_avr_pass_fuse_add): New protos. * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses avr_split_tiny_move to split indirect memory accesses. (gen_move_clobbercc): New define_expand helper. * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. (avr_pass_fuse_add): New class from rtl_opt_pass. (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets of PLUS addressing for AVR_TINY. (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng1-0/+46
The output of -march=help is like below: ``` All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 ... ``` Also support -print-supported-extensions and --print-supported-extensions for clang compatibility. gcc/ChangeLog: PR target/109349 * common/config/riscv/riscv-common.cc (riscv_arch_help): New. * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. (RISCV_MINOR_VERSION_BASE): Ditto. (RISCV_REVISION_VERSION_BASE): Ditto. * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum rather than magic number. * config/riscv/riscv.h (riscv_arch_help): New. (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and --print-supported-extensions. * config/riscv/riscv.opt (march=help): New. (print-supported-extensions): New. (-print-supported-extensions): New. * doc/invoke.texi (RISC-V Options): Document -march=help. Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+14
The RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions These extensions don't add any new features but describe existing features. So this patch only adds parsing. Za64rs: Reservation set size of 64 bytes Za128rs: Reservation set size of 128 bytes Ziccif: Main memory supports instruction fetch with atomicity requirement Ziccrse: Main memory supports forward progress on LR/SC sequences Ziccamoa: Main memory supports all atomics in A Zicclsm: Main memory supports misaligned loads/stores Zic64b: Cache block size isf 64 bytes gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items. * config/riscv/riscv.opt: New macro for 7 new unprivileged extensions. * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions. gcc/testsuite/ChangeLog: * gcc.target/riscv/za-ext.c: New test. * gcc.target/riscv/zi-ext.c: New test.
2024-01-25RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension.
2024-01-24RISC-V: Don't make Ztso imply APalmer Dabbelt1-2/+0
I can't actually find anything in the ISA manual that makes Ztso imply A. In theory the memory ordering is just a different thing that the set of availiable instructions (ie, Ztso without A would still imply TSO for loads and stores). It also seems like a configuration that could be sane to build: without A it's all but impossible to write any meaningful multi-core code, and TSO is really cheap for a single core. That said, I think it's kind of reasonable to provide A to users asking for Ztso. So maybe even if this was a mistake it's the right thing to do? gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Remove {"ztso", "a"}.
2024-01-19RISC-V: Add the Zihpm and Zicntr extensionsPalmer Dabbelt1-0/+3
These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions and otherwise ignores them. I added these under SPEC_CLASS_NONE even though the PDF lists them as 20190614 because it seems pointless to add another spec class just to accept two extensions we then ignore. 1: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/HZGoqP1eyps/m/GTNKRLJoAQAJ 2: https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjQhChrq9Q/m/7gqdkctgAgAJ gcc/ChangeLog * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr extensions.
2024-01-19RISC-V: Remove unused function in riscv_subset_list [NFC]Kito Cheng1-179/+0
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_std_ext): Remove. (riscv_subset_list::parse_multiletter_ext): Remove. * config/riscv/riscv-subset.h (riscv_subset_list::parse_std_ext): Remove. (riscv_subset_list::parse_multiletter_ext): Remove.
2024-01-19RISC-V: Relax the -march string for accept any orderKito Cheng1-37/+54
-march was require canonical order before, however it's not easy for most user when we have so many extension, so this patch is relax the constraint, -march accept the ISA string in any order, it only has few requirement: 1. Must start with rv[32|64][e|i|g]. 2. Multi-letter and single letter extension must be separated by at least one underscore(`_`). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_single_std_ext): New parameter. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::parse): Relax the order for the input of ISA string. * config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext): New parameter. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::parse_single_ext): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-33.c: New. * gcc.target/riscv/arch-34.c: New.
2024-01-19RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]Kito Cheng1-24/+45
Minor refactor, preparation for further change. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_base_ext): New. (riscv_subset_list::parse): Extract part of logic into riscv_subset_list::parse_base_ext. * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext): New.
2024-01-18RISC-V: Introduce XTheadVector as a subset of V1.0.0Jun Sha (Joshua)1-0/+23
This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extension. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add test marco. * config/riscv/riscv.opt: Add new mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test. * gcc.target/riscv/rvv/xtheadvector.c: New test. Co-authored-by: Jin Ma <jinma@linux.alibaba.com> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-01-03Update copyright years.Jakub Jelinek56-56/+56
2023-12-16[aarch64] Add function multiversioning supportAndrew Carlotti1-0/+94
This adds initial support for function multiversioning on aarch64 using the target_version and target_clones attributes. This loosely follows the Beta specification in the ACLE [1], although with some differences that still need to be resolved (possibly as follow-up patches). Existing function multiversioning implementations are broken in various ways when used across translation units. This includes placing resolvers in the wrong translation units, and using symbol mangling that callers to unintentionally bypass the resolver in some circumstances. Fixing these issues for aarch64 will require modifications to our ACLE specification. It will also require further adjustments to existing middle end code, to facilitate different mangling and resolver placement while preserving existing target behaviours. The list of function multiversioning features specified in the ACLE is also inconsistent with the list of features supported in target option extensions. I intend to resolve some or all of these inconsistencies at a later stage. The target_version attribute is currently only supported in C++, since this is the only frontend with existing support for multiversioning using the target attribute. On the other hand, this patch happens to enable multiversioning with the target_clones attribute in Ada and D, as well as the entire C family, using their existing frontend support. This patch also does not support the following aspects of the Beta specification: - The target_clones attribute should allow an implicit unlisted "default" version. - There should be an option to disable function multiversioning at compile time. - Unrecognised target names in a target_clones attribute should be ignored (with an optional warning). This current patch raises an error instead. [1] https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning gcc/ChangeLog: * config/aarch64/aarch64-feature-deps.h (fmv_deps_<FEAT_NAME>): Define aarch64_feature_flags mask foreach FMV feature. * config/aarch64/aarch64-option-extensions.def: Use new macros to define FMV feature extensions. * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p): Check for target_version attribute after processing target attribute. (aarch64_fmv_feature_data): New. (aarch64_parse_fmv_features): New. (aarch64_process_target_version_attr): New. (aarch64_option_valid_version_attribute_p): New. (get_feature_mask_for_version): New. (compare_feature_masks): New. (aarch64_compare_version_priority): New. (build_ifunc_arg_type): New. (make_resolver_func): New. (add_condition_to_bb): New. (dispatch_function_versions): New. (aarch64_generate_version_dispatcher_body): New. (aarch64_get_function_versions_dispatcher): New. (aarch64_common_function_versions): New. (aarch64_mangle_decl_assembler_name): New. (TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): New implementation. (TARGET_OPTION_EXPANDED_CLONES_ATTRIBUTE): New implementation. (TARGET_OPTION_FUNCTION_VERSIONS): New implementation. (TARGET_COMPARE_VERSION_PRIORITY): New implementation. (TARGET_GENERATE_VERSION_DISPATCHER_BODY): New implementation. (TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): New implementation. (TARGET_MANGLE_DECL_ASSEMBLER_NAME): New implementation. * config/aarch64/aarch64.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE): Set target macro. * config/arm/aarch-common.h (enum aarch_parse_opt_result): Add new value to report duplicate FMV feature. * common/config/aarch64/cpuinfo.h: New file. libgcc/ChangeLog: * config/aarch64/cpuinfo.c (enum CPUFeatures): Move to shared copy in gcc/common gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_17.c: Reorder expected flags. * gcc.target/aarch64/cpunative/native_cpu_0.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_13.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_16.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_17.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_18.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_19.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_20.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_21.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_6.c: Ditto. * gcc.target/aarch64/cpunative/native_cpu_7.c: Ditto.
2023-12-16aarch64: Fix +nopredres, +nols64 and +nomopsAndrew Carlotti1-8/+3
For native cpu feature detection, certain features have no entry in /proc/cpuinfo, so have to be assumed to be present whenever the detected cpu is supposed to support that feature. However, the logic for this was mistakenly implemented by excluding these features from part of aarch64_get_extension_string_for_isa_flags. This function is also used elsewhere when canonicalising explicit feature sets, which may require removing features that are normally implied by the specified architecture version. This change reenables generation of +nopredres, +nols64 and +nomops during canonicalisation, by relocating the misplaced native cpu detection logic. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (struct aarch64_option_extension): Remove unused field. (all_extensions): Ditto. (aarch64_get_extension_string_for_isa_flags): Remove filtering of features without native detection. * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Explicitly add expected features that lack cpuinfo detection. gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_28.c: New test.
2023-12-16aarch64: Fix +nocrypto handlingAndrew Carlotti1-8/+27
Additionally, replace all checks for the AARCH64_FL_CRYPTO bit with checks for (AARCH64_FL_AES | AARCH64_FL_SHA2) instead. The value of the AARCH64_FL_CRYPTO bit within isa_flags is now ignored, but it is retained because removing it would make processing the data in option-extensions.def significantly more complex. This bug should have been picked up by an existing test, but a missing newline meant that the pattern incorrectly allowed "+crypto+nocrypto". gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_get_extension_string_for_isa_flags): Fix generation of the "+nocrypto" extension. * config/aarch64/aarch64.h (AARCH64_ISA_CRYPTO): Remove. (TARGET_CRYPTO): Remove. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Don't use TARGET_CRYPTO. gcc/testsuite/ChangeLog: * gcc.target/aarch64/options_set_4.c: Add terminating newline. * gcc.target/aarch64/options_set_27.c: New test.
2023-12-15[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVelw. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVelw builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-elw-elw-compile-1.c: Create test for cv.elw. * lib/target-supports.exp: Add proc for the XCVelw extension.
2023-12-15[PATCH] RISC-V: Add Zvfbfmin extension to the -march= optionXiao Zeng1-0/+4
This patch would like to add new sub extension (aka Zvfbfmin) to the -march= option. It introduces a new data type BF16. Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. You can locate more information about Zvfbfmin from below spec doc. https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfbfmin item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv.opt: (MASK_ZVFBFMIN): New macro. (MASK_VECTOR_ELEN_BF_16): Ditto. (TARGET_ZVFBFMIN): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-31.c: New test. * gcc.target/riscv/arch-32.c: New test. * gcc.target/riscv/predef-32.c: New test. * gcc.target/riscv/predef-33.c: New test.
2023-12-13RISC-V:Add crypto vector implied ISA info.Feng Wang1-0/+9
Due to the crypto vector entension is depend on the Vector extension, so add the implied ISA info with the corresponding crypto vector extension. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Modify implied ISA info. * config/riscv/arch-canonicalize: Add crypto vector implied info.
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+1
This pass adds a simple register allocator for FP & SIMD registers. Its main purpose is to make use of SME2's strided LD1, ST1 and LUTI2/4 instructions, which require a very specific grouping structure, and so would be difficult to exploit with general allocation. The allocator is very simple. It gives up on anything that would require spilling, or that it might not handle well for other reasons. The allocator needs to track liveness at the level of individual FPRs. Doing that fixes a lot of the PRs relating to redundant moves caused by structure loads and stores. That particular problem is going to be fixed more generally for GCC 15 by Lehua's RA patches. However, the early-RA pass runs before scheduling, so it has a chance to bag a spill-free allocation of vector code before the scheduler moves things around. It could therefore still be useful for non-SME code (e.g. for hand-scheduled ACLE code) even after Lehua's patches are in. The pass is controlled by a tristate switch: - -mearly-ra=all: run on all functions - -mearly-ra=strided: run on functions that have access to strided registers - -mearly-ra=none: don't run on any function The patch makes -mearly-ra=all the default at -O2 and above for now. We can revisit this for GCC 15 once Lehua's patches are in; -mearly-ra=strided might then be more appropriate. As said previously, the pass is very naive. There's much more that we could do, such as handling invariants better. The main focus is on not committing to a bad allocation, rather than on handling as much as possible. gcc/ PR rtl-optimization/106694 PR rtl-optimization/109078 PR rtl-optimization/109391 * config.gcc: Add aarch64-early-ra.o for AArch64 targets. * config/aarch64/t-aarch64 (aarch64-early-ra.o): New rule. * config/aarch64/aarch64-opts.h (aarch64_early_ra_scope): New enum. * config/aarch64/aarch64.opt (mearly_ra): New option. * doc/invoke.texi: Document it. * common/config/aarch64/aarch64-common.cc (aarch_option_optimization_table): Use -mearly-ra=strided by default for -O2 and above. * config/aarch64/aarch64-passes.def (pass_aarch64_early_ra): New pass. * config/aarch64/aarch64-protos.h (aarch64_strided_registers_p) (make_pass_aarch64_early_ra): Declare. * config/aarch64/aarch64-sme.md (@aarch64_sme_lut<LUTI_BITS><mode>): Add a stride_type attribute. (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): New pattern. (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svld1_impl::expand) (svldnt1_impl::expand, svst1_impl::expand, svstn1_impl::expand): Handle new way of defining multi-register loads and stores. * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>) (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>) (@aarch64_stnt1<SVE_FULLx24:mode>): Delete. * config/aarch64/aarch64-sve2.md (@aarch64_<LD1_COUNT:optab><mode>) (@aarch64_<LD1_COUNT:optab><mode>_strided2): New patterns. (@aarch64_<LD1_COUNT:optab><mode>_strided4): Likewise. (@aarch64_<ST1_COUNT:optab><mode>): Likewise. (@aarch64_<ST1_COUNT:optab><mode>_strided2): Likewise. (@aarch64_<ST1_COUNT:optab><mode>_strided4): Likewise. * config/aarch64/aarch64.cc (aarch64_strided_registers_p): New function. * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): Delete. (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise. (UNSPEC_STNT1_SVE_COUNT): Likewise. (stride_type): New attribute. * config/aarch64/constraints.md (Uwd, Uwt): New constraints. * config/aarch64/iterators.md (UNSPEC_LD1_COUNT, UNSPEC_LDNT1_COUNT) (UNSPEC_ST1_COUNT, UNSPEC_STNT1_COUNT): New unspecs. (optab): Handle them. (LD1_COUNT, ST1_COUNT): New iterators. * config/aarch64/aarch64-early-ra.cc: New file. gcc/testsuite/ PR rtl-optimization/106694 PR rtl-optimization/109078 PR rtl-optimization/109391 * gcc.target/aarch64/ldp_stp_16.c (cons4_4_float): Tighten expected output test. * gcc.target/aarch64/sve/shift_1.c: Allow reversed shifts for .s as well as .d. * gcc.target/aarch64/sme/strided_1.c: New test. * gcc.target/aarch64/pr109078.c: Likewise. * gcc.target/aarch64/pr109391.c: Likewise. * gcc.target/aarch64/sve/pr106694.c: Likewise.
2023-12-05RISC-V: Check if zcd conflicts with zcmt and zcmpKito Cheng1-0/+8
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): Check zcd conflicts with zcmt and zcmp. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-29.c: New test. * gcc.target/riscv/arch-30.c: New test.
2023-12-04RISC-V: Update crypto vector ISA info with latest specFeng Wang1-2/+4
This patch add the Zvkb subset of crypto vector extension. The corresponding test cases have aslo been modified. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zvkb ISA info. * config/riscv/riscv.opt: Add Mask(ZVKB) gcc/testsuite/ChangeLog: * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb. * gcc.target/riscv/zvkn.c: Ditto. * gcc.target/riscv/zvknc-1.c:Ditto. * gcc.target/riscv/zvknc-2.c:Ditto. * gcc.target/riscv/zvknc.c: Ditto. * gcc.target/riscv/zvkng-1.c:Ditto. * gcc.target/riscv/zvkng-2.c:Ditto. * gcc.target/riscv/zvkng.c: Ditto. * gcc.target/riscv/zvks-1.c: Ditto. * gcc.target/riscv/zvks.c: Ditto. * gcc.target/riscv/zvksc-1.c:Ditto. * gcc.target/riscv/zvksc-2.c:Ditto. * gcc.target/riscv/zvksc.c: Ditto. * gcc.target/riscv/zvksg-1.c:Ditto. * gcc.target/riscv/zvksg-2.c:Ditto. * gcc.target/riscv/zvksg.c: Ditto.
2023-12-04RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional ↵Kito Cheng1-11/+33
implication [NFC] RISC-V ISA implication rules become little bit complicated than before, it may come with condition, so this commit extend the capability of riscv_implied_info_t, also make it more...C++ize. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New. (riscv_implied_info_t::riscv_implied_info_t): New. (riscv_implied_info_t::match): New. (riscv_implied_info): New entry for zcf. (riscv_subset_list::handle_implied_ext): Use riscv_implied_info_t::match. (riscv_subset_list::check_implied_ext): Ditto. (riscv_subset_list::handle_combine_ext): Ditto. (riscv_subset_list::parse): Move zcf implication handling to riscv_implied_infos.
2023-12-04RISC-V: Refine riscv_subset_list::parse [NFC]Kito Cheng1-12/+19
Extract the logic of checking conflict extensions to a standard alone function, prepare to add more checking logic. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): New. (riscv_subset_list::parse): Move checking conflict ext. to check_conflict_ext. * config/riscv/riscv-subset.h: Add riscv_subset_list::check_conflict_ext.
2023-12-04i386: Fix CPUID of USER_MSR.Hu, Lin11-2/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR to the correct location. gcc/testsuite/ChangeLog: * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user an proper example.
generated by cgit v1.1 at 2025-08-04 10:03:01 +0000