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AgeCommit message (Expand)AuthorFilesLines
22 hoursRISC-V: Allow adding enabled extension via target arch attributesChristoph Müllner1-6/+11
22 hoursRISC-V: Rewrite target attribute handlingChristoph Müllner1-109/+4
22 hoursRISC-V: Deduplicate arch subset list processingChristoph Müllner1-26/+6
8 daysi386: Correct AVX10 CPUID emulationHaochen Jiang1-2/+2
2024-06-03Add AVX10.1 target_clones supportHaochen Jiang3-5/+8
2024-04-22i386: Fix Sierra Forest auto dispatchHaochen Jiang1-1/+1
2024-03-31RISC-V: Fix one unused varable in riscv_subset_list::parsePan Li1-1/+0
2024-03-22RISC-V: Bugfix function target attribute pollutionPan Li1-2/+103
2024-03-22RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))Pan Li1-10/+21
2024-03-18[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+2
2024-03-18Add AMD znver5 processor enablement with scheduler modelJan Hubicka3-1/+23
2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay1-0/+2
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng1-0/+46
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+14
2024-01-25RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+2
2024-01-24RISC-V: Don't make Ztso imply APalmer Dabbelt1-2/+0
2024-01-19RISC-V: Add the Zihpm and Zicntr extensionsPalmer Dabbelt1-0/+3
2024-01-19RISC-V: Remove unused function in riscv_subset_list [NFC]Kito Cheng1-179/+0
2024-01-19RISC-V: Relax the -march string for accept any orderKito Cheng1-37/+54
2024-01-19RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]Kito Cheng1-24/+45
2024-01-18RISC-V: Introduce XTheadVector as a subset of V1.0.0Jun Sha (Joshua)1-0/+23
2024-01-03Update copyright years.Jakub Jelinek51-51/+51
2023-12-16[aarch64] Add function multiversioning supportAndrew Carlotti1-0/+94
2023-12-16aarch64: Fix +nopredres, +nols64 and +nomopsAndrew Carlotti1-8/+3
2023-12-16aarch64: Fix +nocrypto handlingAndrew Carlotti1-8/+27
2023-12-15[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+2
2023-12-15[PATCH] RISC-V: Add Zvfbfmin extension to the -march= optionXiao Zeng1-0/+4
2023-12-13RISC-V:Add crypto vector implied ISA info.Feng Wang1-0/+9
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+1
2023-12-05RISC-V: Check if zcd conflicts with zcmt and zcmpKito Cheng1-0/+8
2023-12-04RISC-V: Update crypto vector ISA info with latest specFeng Wang1-2/+4
2023-12-04RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional i...Kito Cheng1-11/+33
2023-12-04RISC-V: Refine riscv_subset_list::parse [NFC]Kito Cheng1-12/+19
2023-12-04i386: Fix CPUID of USER_MSR.Hu, Lin11-2/+2
2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-4/+4
2023-11-20Initial support for AVX10.1Haochen Jiang4-1/+92
2023-11-15RISC-V: Fix ICE in non-canonical march parsingPatrick O'Neill1-4/+13
2023-10-30i386: Zhaoxin yongfeng enablementMayshao3-5/+12
2023-10-22RISC-V: Prohibit combination of 'E' and 'H'Tsukasa OI1-0/+4
2023-10-22RISC-V: 'Zfa' extension is now ratifiedTsukasa OI1-1/+1
2023-10-18Initial Panther Lake SupportHaochen Jiang3-0/+12
2023-10-18Initial Clearwater Forest SupportHaochen Jiang3-0/+10
2023-10-12Support Intel USER_MSRHu, Lin14-0/+19
2023-10-11RISC-V: Extend riscv_subset_list, preparatory for target attribute supportKito Cheng1-0/+209
2023-10-11[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+2
2023-10-11[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+4
2023-10-09Initial support for -mevex512Haochen Jiang1-0/+15
2023-10-07[APX_EGPR] Initial support for APX_FKong Lingling4-1/+30
2023-09-08LoongArch: Enable -fsched-pressure by default at -O1 and higher.Guo Jie1-0/+1
2023-09-07RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' supportTsukasa OI1-0/+2
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